LLVM 19.0.0git
HexagonVExtract.cpp
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1//===- HexagonVExtract.cpp ------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// This pass will replace multiple occurrences of V6_extractw from the same
9// vector register with a combination of a vector store and scalar loads.
10//===----------------------------------------------------------------------===//
11
12#include "Hexagon.h"
13#include "HexagonInstrInfo.h"
15#include "HexagonRegisterInfo.h"
16#include "HexagonSubtarget.h"
18#include "llvm/Pass.h"
25
26#include <map>
27
28using namespace llvm;
29
31 "hexagon-vextract-threshold", cl::Hidden, cl::init(1),
32 cl::desc("Threshold for triggering vextract replacement"));
33
34namespace llvm {
37}
38
39namespace {
40 class HexagonVExtract : public MachineFunctionPass {
41 public:
42 static char ID;
43 HexagonVExtract() : MachineFunctionPass(ID) {}
44
45 StringRef getPassName() const override {
46 return "Hexagon optimize vextract";
47 }
48 void getAnalysisUsage(AnalysisUsage &AU) const override {
50 }
51 bool runOnMachineFunction(MachineFunction &MF) override;
52
53 private:
54 const HexagonSubtarget *HST = nullptr;
55 const HexagonInstrInfo *HII = nullptr;
56
57 unsigned genElemLoad(MachineInstr *ExtI, unsigned BaseR,
59 };
60
61 char HexagonVExtract::ID = 0;
62}
63
64INITIALIZE_PASS(HexagonVExtract, "hexagon-vextract",
65 "Hexagon optimize vextract", false, false)
66
67unsigned HexagonVExtract::genElemLoad(MachineInstr *ExtI, unsigned BaseR,
69 MachineBasicBlock &ExtB = *ExtI->getParent();
70 DebugLoc DL = ExtI->getDebugLoc();
71 Register ElemR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
72
73 Register ExtIdxR = ExtI->getOperand(2).getReg();
74 unsigned ExtIdxS = ExtI->getOperand(2).getSubReg();
75
76 // Simplified check for a compile-time constant value of ExtIdxR.
77 if (ExtIdxS == 0) {
78 MachineInstr *DI = MRI.getVRegDef(ExtIdxR);
79 if (DI->getOpcode() == Hexagon::A2_tfrsi) {
80 unsigned V = DI->getOperand(1).getImm();
81 V &= (HST->getVectorLength()-1) & -4u;
82
83 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L2_loadri_io), ElemR)
84 .addReg(BaseR)
85 .addImm(V);
86 return ElemR;
87 }
88 }
89
90 Register IdxR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
91 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::A2_andir), IdxR)
92 .add(ExtI->getOperand(2))
93 .addImm(-4);
94 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L4_loadri_rr), ElemR)
95 .addReg(BaseR)
96 .addReg(IdxR)
97 .addImm(0);
98 return ElemR;
99}
100
101bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) {
102 HST = &MF.getSubtarget<HexagonSubtarget>();
103 HII = HST->getInstrInfo();
104 const auto &HRI = *HST->getRegisterInfo();
106 MachineFrameInfo &MFI = MF.getFrameInfo();
107 Register AR =
108 MF.getInfo<HexagonMachineFunctionInfo>()->getStackAlignBaseReg();
109 std::map<unsigned, SmallVector<MachineInstr *, 4>> VExtractMap;
110 bool Changed = false;
111
112 for (MachineBasicBlock &MBB : MF) {
113 for (MachineInstr &MI : MBB) {
114 unsigned Opc = MI.getOpcode();
115 if (Opc != Hexagon::V6_extractw)
116 continue;
117 Register VecR = MI.getOperand(1).getReg();
118 VExtractMap[VecR].push_back(&MI);
119 }
120 }
121
122 auto EmitAddr = [&] (MachineBasicBlock &BB, MachineBasicBlock::iterator At,
123 DebugLoc dl, int FI, unsigned Offset) {
124 Register AddrR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
125 unsigned FiOpc = AR != 0 ? Hexagon::PS_fia : Hexagon::PS_fi;
126 auto MIB = BuildMI(BB, At, dl, HII->get(FiOpc), AddrR);
127 if (AR)
128 MIB.addReg(AR);
129 MIB.addFrameIndex(FI).addImm(Offset);
130 return AddrR;
131 };
132
133 MaybeAlign MaxAlign;
134 for (auto &P : VExtractMap) {
135 unsigned VecR = P.first;
136 if (P.second.size() <= VExtractThreshold)
137 continue;
138
139 const auto &VecRC = *MRI.getRegClass(VecR);
140 Align Alignment = HRI.getSpillAlign(VecRC);
141 MaxAlign = std::max(MaxAlign.valueOrOne(), Alignment);
142 // Make sure this is not a spill slot: spill slots cannot be aligned
143 // if there are variable-sized objects on the stack. They must be
144 // accessible via FP (which is not aligned), because SP is unknown,
145 // and AP may not be available at the location of the load/store.
146 int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Alignment,
147 /*isSpillSlot*/ false);
148
149 MachineInstr *DefI = MRI.getVRegDef(VecR);
150 MachineBasicBlock::iterator At = std::next(DefI->getIterator());
151 MachineBasicBlock &DefB = *DefI->getParent();
152 unsigned StoreOpc = VecRC.getID() == Hexagon::HvxVRRegClassID
153 ? Hexagon::V6_vS32b_ai
154 : Hexagon::PS_vstorerw_ai;
155 Register AddrR = EmitAddr(DefB, At, DefI->getDebugLoc(), FI, 0);
156 BuildMI(DefB, At, DefI->getDebugLoc(), HII->get(StoreOpc))
157 .addReg(AddrR)
158 .addImm(0)
159 .addReg(VecR);
160
161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8;
162
163 for (MachineInstr *ExtI : P.second) {
164 assert(ExtI->getOpcode() == Hexagon::V6_extractw);
165 unsigned SR = ExtI->getOperand(1).getSubReg();
166 assert(ExtI->getOperand(1).getReg() == VecR);
167
168 MachineBasicBlock &ExtB = *ExtI->getParent();
169 DebugLoc DL = ExtI->getDebugLoc();
170 Register BaseR = EmitAddr(ExtB, ExtI, ExtI->getDebugLoc(), FI,
171 SR == 0 ? 0 : VecSize/2);
172
173 unsigned ElemR = genElemLoad(ExtI, BaseR, MRI);
174 Register ExtR = ExtI->getOperand(0).getReg();
175 MRI.replaceRegWith(ExtR, ElemR);
176 ExtB.erase(ExtI);
177 Changed = true;
178 }
179 }
180
181 if (AR && MaxAlign) {
182 // Update the required stack alignment.
183 MachineInstr *AlignaI = MRI.getVRegDef(AR);
184 assert(AlignaI->getOpcode() == Hexagon::PS_aligna);
185 MachineOperand &Op = AlignaI->getOperand(1);
186 if (*MaxAlign > Op.getImm())
187 Op.setImm(MaxAlign->value());
188 }
189
190 return Changed;
191}
192
194 return new HexagonVExtract();
195}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static cl::opt< unsigned > VExtractThreshold("hexagon-vextract-threshold", cl::Hidden, cl::init(1), cl::desc("Threshold for triggering vextract replacement"))
IRTranslator LLVM IR MI
#define P(N)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
Represent the analysis usage information of a pass.
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
Hexagon target-specific information for each MachineFunction.
const HexagonInstrInfo * getInstrInfo() const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:566
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:343
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:495
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:576
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
int64_t getImm() const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:44
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
self_iterator getIterator()
Definition: ilist_node.h:132
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
FunctionPass * createHexagonVExtract()
void initializeHexagonVExtractPass(PassRegistry &)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
Definition: Alignment.h:141