30#define DEBUG_TYPE "wasm-debug-fixup"
49char WebAssemblyDebugFixup::ID = 0;
52 "Ensures debug_value's that have been stackified become stack relative",
56 return new WebAssemblyDebugFixup();
68 if (
MI.isDebugValue() &&
MI.getDebugOperand(0).isReg() &&
69 !
MI.isUndefDebugValue()) {
72 MI.setDebugValueUndef();
79 "********** Function: "
89 std::vector<StackElem>
Stack;
94 if (
MI.isDebugValue()) {
95 auto &MO =
MI.getOperand(0);
97 if (MO.isReg() && MO.getReg().isValid() &&
104 for (
auto &Elem :
reverse(Stack)) {
105 if (MO.getReg() == Elem.Reg) {
106 auto Depth =
static_cast<unsigned>(&Elem - &
Stack[0]);
108 <<
" -> Stack Relative " <<
Depth <<
"\n");
113 Elem.DebugValue = &
MI;
125 auto Prev =
Stack.back();
127 assert(Prev.Reg == MO.getReg() &&
128 "WebAssemblyDebugFixup: Pop: Register not matched!");
131 if (Prev.DebugValue && !
MI.isTerminator()) {
136 BuildMI(*Prev.DebugValue->getParent(), std::next(MII),
137 Prev.DebugValue->getDebugLoc(),
138 TII->get(WebAssembly::DBG_VALUE),
false,
Register(),
139 Prev.DebugValue->getOperand(2).getMetadata(),
140 Prev.DebugValue->getOperand(3).getMetadata());
146 Stack.push_back({MO.getReg(),
nullptr});
152 "WebAssemblyDebugFixup: Stack not empty at end of basic block!");
const HexagonInstrInfo * TII
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static void setDanglingDebugValuesUndef(MachineBasicBlock &MBB, const TargetInstrInfo *TII)
This file provides WebAssembly-specific target descriptions.
This file declares WebAssembly-specific per-machine-function information.
This file declares the WebAssembly-specific subclass of TargetSubtarget.
This file contains the declaration of the WebAssembly-specific utility functions.
This file contains the entry points for global functions defined in the LLVM WebAssembly back-end.
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
bool isVRegStackified(unsigned VReg) const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
auto reverse(ContainerTy &&C)
FunctionPass * createWebAssemblyDebugFixup()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.