LLVM 19.0.0git
X86FastPreTileConfig.cpp
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1//===-- X86FastPreTileConfig.cpp - Fast Tile Register Configure------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file Pass to preconfig the shape of physical tile registers
10/// It inserts ldtilecfg ahead of each group of tile registers. The algorithm
11/// walk each instruction of basic block in reverse order. All the tile
12/// registers that live out the basic block would be spilled and reloaded
13/// before its user. It also check the depenedency of the shape to ensure
14/// the shape is defined before ldtilecfg.
15//
16//===----------------------------------------------------------------------===//
17
18#include "X86.h"
19#include "X86InstrBuilder.h"
21#include "X86RegisterInfo.h"
22#include "X86Subtarget.h"
24#include "llvm/ADT/Statistic.h"
29#include "llvm/CodeGen/Passes.h"
33#include "llvm/Support/Debug.h"
34
35using namespace llvm;
36
37#define DEBUG_TYPE "fastpretileconfig"
38
39STATISTIC(NumStores, "Number of stores added");
40STATISTIC(NumLoads, "Number of loads added");
41
42namespace {
43
44class X86FastPreTileConfig : public MachineFunctionPass {
45 MachineFunction *MF = nullptr;
46 const X86Subtarget *ST = nullptr;
47 const TargetInstrInfo *TII = nullptr;
48 MachineRegisterInfo *MRI = nullptr;
49 X86MachineFunctionInfo *X86FI = nullptr;
50 MachineFrameInfo *MFI = nullptr;
51 const TargetRegisterInfo *TRI = nullptr;
52 MachineBasicBlock *MBB = nullptr;
53 int CfgSS = -1;
54 struct PHIInfo {
55 Register Row;
56 Register Col;
57 Register StackAddr;
58 };
60
61 /// Maps virtual regs to the frame index where these values are spilled.
62 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
63
64 /// Has a bit set for tile virtual register for which it was determined
65 /// that it is alive across blocks.
66 BitVector MayLiveAcrossBlocks;
67
68 int getStackSpaceFor(Register VirtReg);
69 void InitializeTileConfigStackSpace();
70 bool mayLiveOut(Register VirtReg, MachineInstr *CfgMI);
71 void spill(MachineBasicBlock::iterator Before, Register VirtReg, bool Kill);
72 void reload(MachineBasicBlock::iterator UseMI, Register VirtReg,
73 MachineOperand *RowMO, MachineOperand *ColMO);
74 void canonicalizePHIs(MachineBasicBlock &MBB);
75 void convertPHI(MachineBasicBlock *MBB, MachineInstr &PHI);
76 void convertPHIs(MachineBasicBlock &MBB);
77 bool configBasicBlock(MachineBasicBlock &MBB);
78
79public:
80 X86FastPreTileConfig() : MachineFunctionPass(ID), StackSlotForVirtReg(-1) {}
81
82 /// Return the pass name.
83 StringRef getPassName() const override {
84 return "Fast Tile Register Preconfigure";
85 }
86
87 /// Perform tile register configure.
88 bool runOnMachineFunction(MachineFunction &MFunc) override;
89
90 static char ID;
91};
92
93} // end anonymous namespace
94
95char X86FastPreTileConfig::ID = 0;
96
97INITIALIZE_PASS_BEGIN(X86FastPreTileConfig, DEBUG_TYPE,
98 "Fast Tile Register Preconfigure", false, false)
99INITIALIZE_PASS_END(X86FastPreTileConfig, DEBUG_TYPE,
101
105 auto MBBEnd = MBB.end();
106 if (B == MBBEnd)
107 return true;
108
110 for (; &*I != A && &*I != B; ++I)
111 ;
112
113 return &*I == A;
114}
115
116/// This allocates space for the specified virtual register to be held on the
117/// stack.
118int X86FastPreTileConfig::getStackSpaceFor(Register VirtReg) {
119 // Find the location Reg would belong...
120 int SS = StackSlotForVirtReg[VirtReg];
121 // Already has space allocated?
122 if (SS != -1)
123 return SS;
124
125 // Allocate a new stack object for this spill location...
126 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
127 unsigned Size = TRI->getSpillSize(RC);
128 Align Alignment = TRI->getSpillAlign(RC);
129 int FrameIdx = MFI->CreateSpillStackObject(Size, Alignment);
130
131 // Assign the slot.
132 StackSlotForVirtReg[VirtReg] = FrameIdx;
133 return FrameIdx;
134}
135
136/// Returns false if \p VirtReg is known to not live out of the current config.
137/// If \p VirtReg live out of the current MBB, it must live out of the current
138/// config
139bool X86FastPreTileConfig::mayLiveOut(Register VirtReg, MachineInstr *CfgMI) {
140 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg)))
141 return true;
142
143 for (const MachineInstr &UseInst : MRI->use_nodbg_instructions(VirtReg)) {
144 if (UseInst.getParent() != MBB) {
145 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
146 return true;
147 }
148
149 // The use and def are in the same MBB. If the tile register is
150 // reconfigured, it is crobbered and we need to spill and reload
151 // tile register.
152 if (CfgMI) {
153 if (dominates(*MBB, *CfgMI, UseInst)) {
154 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
155 return true;
156 }
157 }
158 }
159
160 return false;
161}
162
163void X86FastPreTileConfig::InitializeTileConfigStackSpace() {
164 MachineBasicBlock &MBB = MF->front();
166 DebugLoc DL;
167 if (ST->hasAVX512()) {
168 Register Zmm = MRI->createVirtualRegister(&X86::VR512RegClass);
169 BuildMI(MBB, MI, DL, TII->get(X86::AVX512_512_SET0), Zmm);
170 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::VMOVUPSZmr)), CfgSS)
171 .addReg(Zmm);
172 } else if (ST->hasAVX2()) {
173 Register Ymm = MRI->createVirtualRegister(&X86::VR256RegClass);
174 BuildMI(MBB, MI, DL, TII->get(X86::AVX_SET0), Ymm);
175 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::VMOVUPSYmr)), CfgSS)
176 .addReg(Ymm);
177 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::VMOVUPSYmr)), CfgSS,
178 32)
179 .addReg(Ymm);
180 } else {
181 assert(ST->hasSSE2() && "AMX should assume SSE2 enabled");
182 unsigned StoreOpc = ST->hasAVX() ? X86::VMOVUPSmr : X86::MOVUPSmr;
183 Register Xmm = MRI->createVirtualRegister(&X86::VR128RegClass);
184 BuildMI(MBB, MI, DL, TII->get(X86::V_SET0), Xmm);
185 addFrameReference(BuildMI(MBB, MI, DL, TII->get(StoreOpc)), CfgSS)
186 .addReg(Xmm);
187 addFrameReference(BuildMI(MBB, MI, DL, TII->get(StoreOpc)), CfgSS, 16)
188 .addReg(Xmm);
189 addFrameReference(BuildMI(MBB, MI, DL, TII->get(StoreOpc)), CfgSS, 32)
190 .addReg(Xmm);
191 addFrameReference(BuildMI(MBB, MI, DL, TII->get(StoreOpc)), CfgSS, 48)
192 .addReg(Xmm);
193 }
194 // Fill in the palette first.
195 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV8mi)), CfgSS)
196 .addImm(1);
197}
198
199/// Insert spill instruction for \p AssignedReg before \p Before.
200/// TODO: Update DBG_VALUEs with \p VirtReg operands with the stack slot.
201void X86FastPreTileConfig::spill(MachineBasicBlock::iterator Before,
202 Register VirtReg, bool Kill) {
203 LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) << " \n");
204 int FI = getStackSpaceFor(VirtReg);
205 LLVM_DEBUG(dbgs() << " to stack slot #" << FI << '\n');
206
207 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
208 // Don't need shape information for tile store, becasue it is adjacent to
209 // the tile def instruction.
210 TII->storeRegToStackSlot(*MBB, Before, VirtReg, Kill, FI, &RC, TRI,
211 Register());
212 ++NumStores;
213
214 // TODO: update DBG_VALUEs
215}
216
217/// Insert reload instruction for \p PhysReg before \p Before.
218void X86FastPreTileConfig::reload(MachineBasicBlock::iterator UseMI,
219 Register OrigReg, MachineOperand *RowMO,
220 MachineOperand *ColMO) {
221 int FI = getStackSpaceFor(OrigReg);
222 const TargetRegisterClass &RC = *MRI->getRegClass(OrigReg);
223 Register TileReg;
224 // Fold copy to tileload
225 // BB1:
226 // spill src to s
227 //
228 // BB2:
229 // t = copy src
230 // -->
231 // t = tileload (s)
232 if (UseMI->isCopy())
233 TileReg = UseMI->getOperand(0).getReg();
234 else
235 TileReg = MRI->createVirtualRegister(&RC);
236 // Can't use TII->loadRegFromStackSlot(), because we need the shape
237 // information for reload.
238 // tileloadd (%sp, %idx), %tmm
239 unsigned Opc = X86::PTILELOADDV;
240 Register StrideReg = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass);
241 // FIXME: MBB is not the parent of UseMI.
243 TII->get(X86::MOV64ri), StrideReg)
244 .addImm(64);
245 NewMI = addFrameReference(
246 BuildMI(*UseMI->getParent(), UseMI, DebugLoc(), TII->get(Opc), TileReg)
247 .addReg(RowMO->getReg())
248 .addReg(ColMO->getReg()),
249 FI);
250 MachineOperand &MO = NewMI->getOperand(5);
251 MO.setReg(StrideReg);
252 MO.setIsKill(true);
253 RowMO->setIsKill(false);
254 ColMO->setIsKill(false);
255 // Erase copy instruction after it is folded.
256 if (UseMI->isCopy()) {
258 } else {
259 // Replace the register in the user MI.
260 for (auto &MO : UseMI->operands()) {
261 if (MO.isReg() && MO.getReg() == OrigReg)
262 MO.setReg(TileReg);
263 }
264 }
265
266 ++NumLoads;
267 LLVM_DEBUG(dbgs() << "Reloading " << printReg(OrigReg, TRI) << " into "
268 << printReg(TileReg, TRI) << '\n');
269}
270
272 // The instruction must have 3 operands: tile def, row, col.
273 if (MI.isDebugInstr() || MI.getNumOperands() < 3 || !MI.isPseudo())
274 return false;
275 MachineOperand &MO = MI.getOperand(0);
276
277 if (MO.isReg()) {
278 Register Reg = MO.getReg();
279 // FIXME it may be used after Greedy RA and the physical
280 // register is not rewritten yet.
281 if (Reg.isVirtual() &&
282 MRI->getRegClass(Reg)->getID() == X86::TILERegClassID)
283 return true;
284 if (Reg >= X86::TMM0 && Reg <= X86::TMM7)
285 return true;
286 }
287
288 return false;
289}
290
292 MachineInstr *MI = MRI->getVRegDef(TileReg);
293 if (isTileDef(MRI, *MI)) {
294 MachineOperand *RowMO = &MI->getOperand(1);
295 MachineOperand *ColMO = &MI->getOperand(2);
296 return ShapeT(RowMO, ColMO, MRI);
297 } else if (MI->isCopy()) {
298 TileReg = MI->getOperand(1).getReg();
299 return getShape(MRI, TileReg);
300 }
301
302 // The def should not be PHI node, because we walk the MBB in reverse post
303 // order.
304 assert(MI->isPHI() && "Unexpected PHI when get shape.");
305 llvm_unreachable("Unexpected MI when get shape.");
306}
307
308// BB0:
309// spill t0 to s0
310// BB1:
311// spill t1 to s1
312//
313// BB2:
314// t = phi [t0, bb0] [t1, bb1]
315// -->
316// row = phi [r0, bb0] [r1, bb1]
317// col = phi [c0, bb0] [c1, bb1]
318// s = phi [s0, bb0] [s1, bb1]
319// t = tileload row, col, s
320// The new instruction is inserted at the end of the phi node. The order
321// of the original phi node is not ensured.
322void X86FastPreTileConfig::convertPHI(MachineBasicBlock *MBB,
323 MachineInstr &PHI) {
324 // 1. Create instruction to get stack slot address of each incoming block.
325 // 2. Create PHI node for the stack address.
326 // 3. Create PHI node for shape. If one of the incoming shape is immediate
327 // use the immediate and delete the PHI node.
328 // 4. Create tileload instruction from the stack address.
329 Register StackAddrReg = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass);
330 MachineInstrBuilder AddrPHI = BuildMI(*MBB, ++PHI.getIterator(), DebugLoc(),
331 TII->get(X86::PHI), StackAddrReg);
332 Register RowReg = MRI->createVirtualRegister(&X86::GR16RegClass);
333 MachineInstrBuilder RowPHI = BuildMI(*MBB, ++PHI.getIterator(), DebugLoc(),
334 TII->get(X86::PHI), RowReg);
335 Register ColReg = MRI->createVirtualRegister(&X86::GR16RegClass);
336 MachineInstrBuilder ColPHI = BuildMI(*MBB, ++PHI.getIterator(), DebugLoc(),
337 TII->get(X86::PHI), ColReg);
338 // Record the mapping of phi node and its row/column information.
339 VisitedPHIs[&PHI] = {RowReg, ColReg, StackAddrReg};
340
341 for (unsigned I = 1, E = PHI.getNumOperands(); I != E; I += 2) {
342 // Get the 2 incoming value of tile register and MBB.
343 Register InTileReg = PHI.getOperand(I).getReg();
344 // Mark it as liveout, so that it will be spilled when visit
345 // the incoming MBB. Otherwise since phi will be deleted, it
346 // would miss spill when visit incoming MBB.
347 MayLiveAcrossBlocks.set(Register::virtReg2Index(InTileReg));
348 MachineBasicBlock *InMBB = PHI.getOperand(I + 1).getMBB();
349
350 MachineInstr *TileDefMI = MRI->getVRegDef(InTileReg);
352 if (TileDefMI->isPHI()) {
353 InsertPos = TileDefMI->getParent()->getFirstNonPHI();
354 if (VisitedPHIs.count(TileDefMI)) { // circular phi reference
355 // def t1
356 // / \
357 // def t2 t3 = phi(t1, t4) <--
358 // \ / |
359 // t4 = phi(t2, t3)-------------
360 //
361 // For each (row, column and stack address) append phi incoming value.
362 // Create r3 = phi(r1, r4)
363 // Create r4 = phi(r2, r3)
364 Register InRowReg = VisitedPHIs[TileDefMI].Row;
365 Register InColReg = VisitedPHIs[TileDefMI].Col;
366 Register InStackAddrReg = VisitedPHIs[TileDefMI].StackAddr;
367 RowPHI.addReg(InRowReg).addMBB(InMBB);
368 ColPHI.addReg(InColReg).addMBB(InMBB);
369 AddrPHI.addReg(InStackAddrReg).addMBB(InMBB);
370 continue;
371 } else {
372 // Recursively convert PHI to tileload
373 convertPHI(TileDefMI->getParent(), *TileDefMI);
374 // The PHI node is coverted to tileload instruction. Get the stack
375 // address from tileload operands.
376 MachineInstr *TileLoad = MRI->getVRegDef(InTileReg);
377 assert(TileLoad && TileLoad->getOpcode() == X86::PTILELOADDV);
378 Register InRowReg = TileLoad->getOperand(1).getReg();
379 Register InColReg = TileLoad->getOperand(2).getReg();
380 Register InStackAddrReg = TileLoad->getOperand(3).getReg();
381 RowPHI.addReg(InRowReg).addMBB(InMBB);
382 ColPHI.addReg(InColReg).addMBB(InMBB);
383 AddrPHI.addReg(InStackAddrReg).addMBB(InMBB);
384 }
385 } else {
386 InsertPos = TileDefMI->getIterator();
387
388 // Fill the incoming operand of row/column phi instruction.
389 ShapeT Shape = getShape(MRI, InTileReg);
390 Shape.getRow()->setIsKill(false);
391 Shape.getCol()->setIsKill(false);
392 RowPHI.addReg(Shape.getRow()->getReg()).addMBB(InMBB);
393 ColPHI.addReg(Shape.getCol()->getReg()).addMBB(InMBB);
394
395 // The incoming tile register live out of its def BB, it would be spilled.
396 // Create MI to get the spill stack slot address for the tile register
397 int FI = getStackSpaceFor(InTileReg);
398 Register InStackAddrReg =
399 MRI->createVirtualRegister(&X86::GR64_NOSPRegClass);
400 addOffset(BuildMI(*TileDefMI->getParent(), InsertPos, DebugLoc(),
401 TII->get(X86::LEA64r), InStackAddrReg)
402 .addFrameIndex(FI),
403 0);
404 AddrPHI.addReg(InStackAddrReg).addMBB(InMBB);
405 }
406 }
407
409 Register StrideReg = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass);
410 BuildMI(*MBB, InsertPos, DebugLoc(), TII->get(X86::MOV64ri), StrideReg)
411 .addImm(64);
412 Register TileReg = PHI.getOperand(0).getReg();
413 MachineInstr *NewMI = addDirectMem(
414 BuildMI(*MBB, InsertPos, DebugLoc(), TII->get(X86::PTILELOADDV), TileReg)
415 .addReg(RowReg)
416 .addReg(ColReg),
417 StackAddrReg);
418 MachineOperand &MO = NewMI->getOperand(5);
419 MO.setReg(StrideReg);
420 MO.setIsKill(true);
421 PHI.eraseFromParent();
422 VisitedPHIs.erase(&PHI);
423}
424
426 MachineOperand &MO = MI.getOperand(0);
427 if (MO.isReg() && MO.getReg().isVirtual() &&
428 MRI->getRegClass(MO.getReg())->getID() == X86::TILERegClassID)
429 return true;
430 return false;
431}
432
433void X86FastPreTileConfig::canonicalizePHIs(MachineBasicBlock &MBB) {
435
436 for (MachineInstr &MI : MBB) {
437 if (!MI.isPHI())
438 break;
439 if (!isTileRegDef(MRI, MI))
440 continue;
441 PHIs.push_back(&MI);
442 }
443 // Canonicalize the phi node first. One tile phi may depeneds previous
444 // phi node. For below case, we need convert %t4.
445 //
446 // BB0:
447 // %t3 = phi (t1 BB1, t2 BB0)
448 // %t4 = phi (t5 BB1, t3 BB0)
449 // -->
450 // %t3 = phi (t1 BB1, t2 BB0)
451 // %t4 = phi (t5 BB1, t2 BB0)
452 //
453 while (!PHIs.empty()) {
454 MachineInstr *PHI = PHIs.pop_back_val();
455
456 // Find the operand that is incoming from the same MBB and the def
457 // is also phi node.
458 MachineOperand *InMO = nullptr;
459 MachineInstr *DefMI = nullptr;
460 for (unsigned I = 1, E = PHI->getNumOperands(); I != E; I += 2) {
461 Register InTileReg = PHI->getOperand(I).getReg();
462 MachineBasicBlock *InMBB = PHI->getOperand(I + 1).getMBB();
463 DefMI = MRI->getVRegDef(InTileReg);
464 if (InMBB != &MBB || !DefMI->isPHI())
465 continue;
466
467 InMO = &PHI->getOperand(I);
468 break;
469 }
470 // If can't find such operand, do nothing.
471 if (!InMO)
472 continue;
473
474 // Current phi node depends on previous phi node. Break the
475 // dependency.
476 Register DefTileReg;
477 for (unsigned I = 1, E = DefMI->getNumOperands(); I != E; I += 2) {
478 MachineBasicBlock *InMBB = PHI->getOperand(I + 1).getMBB();
479 if (InMBB != &MBB)
480 continue;
481 DefTileReg = DefMI->getOperand(I).getReg();
482 InMO->setReg(DefTileReg);
483 break;
484 }
485 }
486}
487
488void X86FastPreTileConfig::convertPHIs(MachineBasicBlock &MBB) {
490 for (MachineInstr &MI : MBB) {
491 if (!MI.isPHI())
492 break;
493 if (!isTileRegDef(MRI, MI))
494 continue;
495 PHIs.push_back(&MI);
496 }
497 while (!PHIs.empty()) {
498 MachineInstr *MI = PHIs.pop_back_val();
499 VisitedPHIs.clear();
500 convertPHI(&MBB, *MI);
501 }
502}
503
504// PreTileConfig should configure the tile registers based on basic
505// block.
506bool X86FastPreTileConfig::configBasicBlock(MachineBasicBlock &MBB) {
507 this->MBB = &MBB;
508 bool Change = false;
509 MachineInstr *LastShapeMI = nullptr;
510 MachineInstr *LastTileCfg = nullptr;
511 bool HasUnconfigTile = false;
512
513 auto Config = [&](MachineInstr &Before) {
514 if (CfgSS == -1)
515 CfgSS = MFI->CreateStackObject(ST->getTileConfigSize(),
516 ST->getTileConfigAlignment(), false);
517 LastTileCfg = addFrameReference(
518 BuildMI(MBB, Before, DebugLoc(), TII->get(X86::PLDTILECFGV)), CfgSS);
519 LastShapeMI = nullptr;
520 Change = true;
521 };
522 auto HasTileOperand = [](MachineRegisterInfo *MRI, MachineInstr &MI) {
523 for (const MachineOperand &MO : MI.operands()) {
524 if (!MO.isReg())
525 continue;
526 Register Reg = MO.getReg();
527 if (Reg.isVirtual() &&
528 MRI->getRegClass(Reg)->getID() == X86::TILERegClassID)
529 return true;
530 }
531 return false;
532 };
533 for (MachineInstr &MI : reverse(MBB)) {
534 // We have transformed phi node before configuring BB.
535 if (MI.isPHI())
536 break;
537 // Don't collect the shape of used tile, the tile should be defined
538 // before the tile use. Spill and reload would happen if there is only
539 // tile use after ldtilecfg, so the shape can be collected from reload.
540 // Take below code for example. %t would be reloaded before tilestore
541 // call
542 // ....
543 // tilestore %r, %c, %t
544 // -->
545 // call
546 // ldtilecfg
547 // %t = tileload %r, %c
548 // tilestore %r, %c, %t
549 if (HasTileOperand(MRI, MI))
550 HasUnconfigTile = true;
551 // According to AMX ABI, all the tile registers including config register
552 // are volatile. Caller need to save/restore config register.
553 if (MI.isCall() && HasUnconfigTile) {
555 if (LastShapeMI && dominates(MBB, MI, LastShapeMI))
556 I = ++LastShapeMI->getIterator();
557 else
558 I = ++MI.getIterator();
559 Config(*I);
560 HasUnconfigTile = false;
561 continue;
562 }
563 if (!isTileDef(MRI, MI))
564 continue;
565 //
566 //---------------------------------------------------------------------
567 // Don't handle COPY instruction. If the src and dst of the COPY can be
568 // in the same config in below case, we just check the shape of t0.
569 // def row0
570 // def col0
571 // ldtilecfg
572 // t0 = tielzero(row0, col0)
573 // t1 = copy t0
574 // ...
575 // If the src and dst of the COPY can NOT be in the same config in below
576 // case. Reload would be generated befor the copy instruction.
577 // def row0
578 // def col0
579 // t0 = tielzero(row0, col0)
580 // spill t0
581 // ...
582 // def row1
583 // def col1
584 // ldtilecfg
585 // t1 = tilezero(row1, col1)
586 // reload t0
587 // t1 = copy t0
588 //---------------------------------------------------------------------
589 //
590 // If MI dominate the last shape def instruction, we need insert
591 // ldtilecfg after LastShapeMI now. The config doesn't include
592 // current MI.
593 // def row0
594 // def col0
595 // tilezero(row0, col0) <- MI
596 // def row1
597 // def col1
598 // ldtilecfg <- insert
599 // tilezero(row1, col1)
600 if (LastShapeMI && dominates(MBB, MI, LastShapeMI))
601 Config(*(++LastShapeMI->getIterator()));
602 MachineOperand *RowMO = &MI.getOperand(1);
603 MachineOperand *ColMO = &MI.getOperand(2);
604 MachineInstr *RowMI = MRI->getVRegDef(RowMO->getReg());
605 MachineInstr *ColMI = MRI->getVRegDef(ColMO->getReg());
606 // If the shape is defined in current MBB, check the domination.
607 // FIXME how about loop?
608 if (RowMI->getParent() == &MBB) {
609 if (!LastShapeMI)
610 LastShapeMI = RowMI;
611 else if (dominates(MBB, LastShapeMI, RowMI))
612 LastShapeMI = RowMI;
613 }
614 if (ColMI->getParent() == &MBB) {
615 if (!LastShapeMI)
616 LastShapeMI = ColMI;
617 else if (dominates(MBB, LastShapeMI, ColMI))
618 LastShapeMI = ColMI;
619 }
620 // If there is user live out of the tilecfg, spill it and reload in
621 // before the user.
622 Register TileReg = MI.getOperand(0).getReg();
623 if (mayLiveOut(TileReg, LastTileCfg))
624 spill(++MI.getIterator(), TileReg, false);
625 for (MachineInstr &UseMI : MRI->use_instructions(TileReg)) {
626 if (UseMI.getParent() == &MBB) {
627 // check user should not across ldtilecfg
628 if (!LastTileCfg || !dominates(MBB, LastTileCfg, UseMI))
629 continue;
630 // reload befor UseMI
631 reload(UseMI.getIterator(), TileReg, RowMO, ColMO);
632 } else {
633 // Don't reload for phi instruction, we handle phi reload separately.
634 // TODO: merge the reload for the same user MBB.
635 if (!UseMI.isPHI())
636 reload(UseMI.getIterator(), TileReg, RowMO, ColMO);
637 }
638 }
639 }
640
641 // Configure tile registers at the head of the MBB
642 if (HasUnconfigTile) {
644 if (LastShapeMI == nullptr || LastShapeMI->isPHI())
646 else
647 Before = &*(++LastShapeMI->getIterator());
648
649 Config(*Before);
650 }
651
652 return Change;
653}
654
655bool X86FastPreTileConfig::runOnMachineFunction(MachineFunction &MFunc) {
656 MF = &MFunc;
657 MRI = &MFunc.getRegInfo();
658 ST = &MFunc.getSubtarget<X86Subtarget>();
659 TII = ST->getInstrInfo();
660 X86FI = MFunc.getInfo<X86MachineFunctionInfo>();
661 MFI = &MFunc.getFrameInfo();
662 TRI = ST->getRegisterInfo();
663 CfgSS = -1;
664
665 unsigned NumVirtRegs = MRI->getNumVirtRegs();
666 // Abandon early if there is no tile register to config.
667 bool HasVirtTileReg = false;
668 for (unsigned I = 0, E = NumVirtRegs; I != E; ++I) {
670 if (!MRI->reg_nodbg_empty(VirtReg) &&
671 MRI->getRegClass(VirtReg)->getID() == X86::TILERegClassID) {
672 HasVirtTileReg = true;
673 break;
674 }
675 }
676 if (!HasVirtTileReg)
677 return false;
678
679 StackSlotForVirtReg.resize(NumVirtRegs);
680 MayLiveAcrossBlocks.clear();
681 // We will create register during config. *3 is to make sure
682 // the virtual register number doesn't exceed the size of
683 // the bit vector.
684 MayLiveAcrossBlocks.resize(NumVirtRegs * 3);
685 bool Change = false;
686 assert(MRI->isSSA());
687
688 // Canonicalize the phi node first.
689 for (MachineBasicBlock &MBB : MFunc)
690 canonicalizePHIs(MBB);
691
692 // Loop over all of the basic blocks in reverse post order and insert
693 // ldtilecfg for tile registers. The reserse post order is to facilitate
694 // PHI node convert.
696 for (MachineBasicBlock *MBB : RPOT) {
697 convertPHIs(*MBB);
698 Change |= configBasicBlock(*MBB);
699 }
700
701 if (Change)
702 InitializeTileConfigStackSpace();
703
704 StackSlotForVirtReg.clear();
705 return Change;
706}
707
709 return new X86FastPreTileConfig();
710}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Rewrite undef for PHI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Size
RelaxConfig Config
Definition: ELF_riscv.cpp:506
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
Fast Tile Register static false bool dominates(MachineBasicBlock &MBB, MachineBasicBlock::const_iterator A, MachineBasicBlock::const_iterator B)
static bool isTileRegDef(MachineRegisterInfo *MRI, MachineInstr &MI)
Fast Tile Register Preconfigure
static ShapeT getShape(MachineRegisterInfo *MRI, Register TileReg)
#define DEBUG_TYPE
static bool isTileDef(MachineRegisterInfo *MRI, MachineInstr &MI)
A debug info location.
Definition: DebugLoc.h:33
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:546
bool isCopy() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:329
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:549
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:662
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool isPHI() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:556
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
void setIsKill(bool Val=true)
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
MachineOperand * getRow() const
Definition: TileShapeInfo.h:56
MachineOperand * getCol() const
Definition: TileShapeInfo.h:58
bool empty() const
Definition: SmallVector.h:94
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
self_iterator getIterator()
Definition: ilist_node.h:109
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ SS
Definition: X86.h:207
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
FunctionPass * createX86FastPreTileConfigPass()
Return a pass that preconfig the tile registers before fast reg allocation.
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:419
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
static const MachineInstrBuilder & addOffset(const MachineInstrBuilder &MIB, int Offset)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
static const MachineInstrBuilder & addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg)
addDirectMem - This function is used to add a direct memory reference to the current instruction – th...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39