32 if (Preheader ==
Loop)
33 Preheader = *std::next(
Loop->pred_begin());
36 Exit = *std::next(
Loop->succ_begin());
42 MF.
insert(std::next(
Loop->getIterator()), NewBB);
45 auto InsertPt = NewBB->
end();
48 NewBB->
insert(InsertPt, NewMI);
54 R =
MRI.createVirtualRegister(
MRI.getRegClass(OrigR));
62 for (
auto &
Use :
MRI.use_operands(OrigR))
63 if (
Use.getParent()->getParent() !=
Loop)
67 MRI.constrainRegClass(R,
MRI.getRegClass(
Use->getReg()));
68 assert(ConstrainRegClass &&
69 "Expected a valid constrained register class!");
70 (void)ConstrainRegClass;
79 if (MO.isReg() && Remaps.
count(MO.getReg()))
80 MO.setReg(Remaps[MO.getReg()]);
82 for (
auto I = NewBB->
begin();
I->isPHI(); ++
I) {
84 unsigned LoopRegIdx = 3, InitRegIdx = 1;
85 if (
MI.getOperand(2).getMBB() != Preheader)
92 Register R =
MI.getOperand(LoopRegIdx).getReg();
96 MI.removeOperand(LoopRegIdx + 1);
97 MI.removeOperand(LoopRegIdx + 0);
102 MI.getOperand(LoopRegIdx).setReg(LoopReg);
103 MI.removeOperand(InitRegIdx + 1);
104 MI.removeOperand(InitRegIdx + 0);
112 Loop->replacePhiUsesWith(Preheader, NewBB);
117 Loop->replaceSuccessor(Exit, NewBB);
118 Exit->replacePhiUsesWith(
Loop, NewBB);
125 assert(CanAnalyzeBr &&
"Must be able to analyze the loop branch!");
128 FBB == Exit ? NewBB : FBB,
Cond,
DL);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Rewrite Partial Register Uses
const HexagonInstrInfo * TII
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
Represents a single loop in the control flow graph.
instr_iterator instr_begin()
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
void updateTerminator(MachineBasicBlock *PreviousLayoutSuccessor)
Update the terminator instructions in block to account for changes to block layout which may have bee...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Instructions::iterator instr_iterator
void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New)
Given a machine basic block that branched to 'Old', change the code and CFG so that it branches to 'N...
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
Representation of each machine instruction.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
A Use represents the edge between a Value definition and its users.
This is an optimization pass for GlobalISel generic memory operations.
MachineBasicBlock * PeelSingleBlockLoop(LoopPeelDirection Direction, MachineBasicBlock *Loop, MachineRegisterInfo &MRI, const TargetInstrInfo *TII)
Peels a single block loop.
@ LPD_Back
Peel the last iteration of the loop.
@ LPD_Front
Peel the first iteration of the loop.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Direction
An enum for the direction of the loop.