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16 cl::desc(
"Disable scheduling addi instruction before"
20 cl::desc(
"Enable scheduling addi instruction as early"
21 "as possible post ra"),
24 static bool isADDIInstr(
const GenericScheduler::SchedCandidate &Cand) {
25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI ||
26 Cand.SU->getInstr()->getOpcode() == PPC::ADDI8;
29 bool PPCPreRASchedStrategy::biasAddiLoadCandidate(SchedCandidate &Cand,
30 SchedCandidate &TryCand,
35 SchedCandidate &FirstCand = Zone.
isTop() ? TryCand : Cand;
36 SchedCandidate &SecondCand = Zone.
isTop() ? Cand : TryCand;
37 if (
isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) {
38 TryCand.Reason =
Stall;
41 if (FirstCand.SU->getInstr()->mayLoad() &&
isADDIInstr(SecondCand)) {
82 bool SameBoundary = Zone !=
nullptr;
103 const SUnit *CandNextClusterSU =
105 const SUnit *TryCandNextClusterSU =
108 Cand.
SU == CandNextClusterSU, TryCand, Cand,
Cluster))
158 if (biasAddiLoadCandidate(Cand, TryCand, *Zone))
unsigned DemandedResources
const TargetRegisterInfo * TRI
This is an optimization pass for GlobalISel generic memory operations.
void initialize(ScheduleDAGMI *Dag) override
Initialize the strategy after building the DAG for a new region.
const TargetSchedModel * SchedModel
bool tryGreater(int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)
void initialize(ScheduleDAGMI *Dag) override
Initialize the strategy after building the DAG for a new region.
SUnit * pickNode(bool &IsTopNode) override
Pick the next node to schedule.
bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary *Zone) const override
PressureChange CurrentMax
bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone)
unsigned NodeNum
Entry # of node in the node vector.
bool IsAcyclicLatencyLimited
bool DisableLatencyHeuristic
static bool isADDIInstr(const GenericScheduler::SchedCandidate &Cand)
static cl::opt< bool > DisableAddiLoadHeuristic("disable-ppc-sched-addi-load", cl::desc("Disable scheduling addi instruction before" "load for ppc"), cl::Hidden)
void enterMBB(MachineBasicBlock *MBB) override
Tell the strategy that MBB is about to be processed.
MachineSchedPolicy RegionPolicy
void leaveMBB() override
Tell the strategy that current MBB is done.
bool tryLess(int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)
Return true if this heuristic determines order.
Store the state used by GenericScheduler heuristics, required for the lifetime of one invocation of p...
virtual void enterMBB(MachineBasicBlock *MBB)
Tell the strategy that MBB is about to be processed.
bool tryPressure(const PressureChange &TryP, const PressureChange &CandP, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason, const TargetRegisterInfo *TRI, const MachineFunction &MF)
unsigned getLatencyStallCycles(SUnit *SU)
Get the difference between the given SUnit's ready time and the current cycle.
initializer< Ty > init(const Ty &Val)
unsigned getCurrMOps() const
Micro-ops issued in the current cycle.
PressureChange CriticalMax
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
MachineFunction & MF
Machine function.
int biasPhysReg(const SUnit *SU, bool isTop)
Minimize physical register live ranges.
bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) override
Apply a set of heuristics to a new candidate for PostRA scheduling.
SchedResourceDelta ResDelta
void initResourceDelta(const ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel)
virtual void leaveMBB()
Tell the strategy that current MBB is done.
const SUnit * getNextClusterPred() const
const SUnit * getNextClusterSucc() const
bool isTrackingPressure() const
Return true if register pressure tracking is enabled.
Each Scheduling boundary is associated with ready queues.
SUnit * pickNode(bool &IsTopNode) override
Pick the next node to schedule.
static cl::opt< bool > EnableAddiHeuristic("ppc-postra-bias-addi", cl::desc("Enable scheduling addi instruction as early" "as possible post ra"), cl::Hidden, cl::init(true))
Scheduling unit. This is a node in the scheduling DAG.
unsigned getWeakLeft(const SUnit *SU, bool isTop)
bool biasAddiCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) const