LLVM 18.0.0git
SplitKit.cpp
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1//===- SplitKit.cpp - Toolkit for splitting live ranges -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the SplitAnalysis class as well as mutator functions for
10// live range splitting.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SplitKit.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/ADT/Statistic.h"
31#include "llvm/Config/llvm-config.h"
32#include "llvm/IR/DebugLoc.h"
35#include "llvm/Support/Debug.h"
38#include <algorithm>
39#include <cassert>
40#include <iterator>
41#include <limits>
42#include <tuple>
43
44using namespace llvm;
45
46#define DEBUG_TYPE "regalloc"
47
48STATISTIC(NumFinished, "Number of splits finished");
49STATISTIC(NumSimple, "Number of splits that were simple");
50STATISTIC(NumCopies, "Number of copies inserted for splitting");
51STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
52
53//===----------------------------------------------------------------------===//
54// Last Insert Point Analysis
55//===----------------------------------------------------------------------===//
56
58 unsigned BBNum)
59 : LIS(lis), LastInsertPoint(BBNum) {}
60
62InsertPointAnalysis::computeLastInsertPoint(const LiveInterval &CurLI,
63 const MachineBasicBlock &MBB) {
64 unsigned Num = MBB.getNumber();
65 std::pair<SlotIndex, SlotIndex> &LIP = LastInsertPoint[Num];
66 SlotIndex MBBEnd = LIS.getMBBEndIdx(&MBB);
67
69 bool EHPadSuccessor = false;
70 for (const MachineBasicBlock *SMBB : MBB.successors()) {
71 if (SMBB->isEHPad()) {
72 ExceptionalSuccessors.push_back(SMBB);
73 EHPadSuccessor = true;
74 } else if (SMBB->isInlineAsmBrIndirectTarget())
75 ExceptionalSuccessors.push_back(SMBB);
76 }
77
78 // Compute insert points on the first call. The pair is independent of the
79 // current live interval.
80 if (!LIP.first.isValid()) {
82 if (FirstTerm == MBB.end())
83 LIP.first = MBBEnd;
84 else
85 LIP.first = LIS.getInstructionIndex(*FirstTerm);
86
87 // If there is a landing pad or inlineasm_br successor, also find the
88 // instruction. If there is no such instruction, we don't need to do
89 // anything special. We assume there cannot be multiple instructions that
90 // are Calls with EHPad successors or INLINEASM_BR in a block. Further, we
91 // assume that if there are any, they will be after any other call
92 // instructions in the block.
93 if (ExceptionalSuccessors.empty())
94 return LIP.first;
95 for (const MachineInstr &MI : llvm::reverse(MBB)) {
96 if ((EHPadSuccessor && MI.isCall()) ||
97 MI.getOpcode() == TargetOpcode::INLINEASM_BR) {
98 LIP.second = LIS.getInstructionIndex(MI);
99 break;
100 }
101 }
102 }
103
104 // If CurLI is live into a landing pad successor, move the last insert point
105 // back to the call that may throw.
106 if (!LIP.second)
107 return LIP.first;
108
109 if (none_of(ExceptionalSuccessors, [&](const MachineBasicBlock *EHPad) {
110 return LIS.isLiveInToMBB(CurLI, EHPad);
111 }))
112 return LIP.first;
113
114 // Find the value leaving MBB.
115 const VNInfo *VNI = CurLI.getVNInfoBefore(MBBEnd);
116 if (!VNI)
117 return LIP.first;
118
119 // The def of statepoint instruction is a gc relocation and it should be alive
120 // in landing pad. So we cannot split interval after statepoint instruction.
121 if (SlotIndex::isSameInstr(VNI->def, LIP.second))
122 if (auto *I = LIS.getInstructionFromIndex(LIP.second))
123 if (I->getOpcode() == TargetOpcode::STATEPOINT)
124 return LIP.second;
125
126 // If the value leaving MBB was defined after the call in MBB, it can't
127 // really be live-in to the landing pad. This can happen if the landing pad
128 // has a PHI, and this register is undef on the exceptional edge.
129 if (!SlotIndex::isEarlierInstr(VNI->def, LIP.second) && VNI->def < MBBEnd)
130 return LIP.first;
131
132 // Value is properly live-in to the landing pad.
133 // Only allow inserts before the call.
134 return LIP.second;
135}
136
140 SlotIndex LIP = getLastInsertPoint(CurLI, MBB);
141 if (LIP == LIS.getMBBEndIdx(&MBB))
142 return MBB.end();
143 return LIS.getInstructionFromIndex(LIP);
144}
145
146//===----------------------------------------------------------------------===//
147// Split Analysis
148//===----------------------------------------------------------------------===//
149
151 const MachineLoopInfo &mli)
152 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli),
153 TII(*MF.getSubtarget().getInstrInfo()), IPA(lis, MF.getNumBlockIDs()) {}
154
156 UseSlots.clear();
157 UseBlocks.clear();
158 ThroughBlocks.clear();
159 CurLI = nullptr;
160}
161
162/// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
163void SplitAnalysis::analyzeUses() {
164 assert(UseSlots.empty() && "Call clear first");
165
166 // First get all the defs from the interval values. This provides the correct
167 // slots for early clobbers.
168 for (const VNInfo *VNI : CurLI->valnos)
169 if (!VNI->isPHIDef() && !VNI->isUnused())
170 UseSlots.push_back(VNI->def);
171
172 // Get use slots form the use-def chain.
174 for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg()))
175 if (!MO.isUndef())
176 UseSlots.push_back(LIS.getInstructionIndex(*MO.getParent()).getRegSlot());
177
178 array_pod_sort(UseSlots.begin(), UseSlots.end());
179
180 // Remove duplicates, keeping the smaller slot for each instruction.
181 // That is what we want for early clobbers.
182 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
184 UseSlots.end());
185
186 // Compute per-live block info.
187 calcLiveBlockInfo();
188
189 LLVM_DEBUG(dbgs() << "Analyze counted " << UseSlots.size() << " instrs in "
190 << UseBlocks.size() << " blocks, through "
191 << NumThroughBlocks << " blocks.\n");
192}
193
194/// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
195/// where CurLI is live.
196void SplitAnalysis::calcLiveBlockInfo() {
197 ThroughBlocks.resize(MF.getNumBlockIDs());
198 NumThroughBlocks = NumGapBlocks = 0;
199 if (CurLI->empty())
200 return;
201
202 LiveInterval::const_iterator LVI = CurLI->begin();
203 LiveInterval::const_iterator LVE = CurLI->end();
204
206 UseI = UseSlots.begin();
207 UseE = UseSlots.end();
208
209 // Loop over basic blocks where CurLI is live.
211 LIS.getMBBFromIndex(LVI->start)->getIterator();
212 while (true) {
213 BlockInfo BI;
214 BI.MBB = &*MFI;
215 SlotIndex Start, Stop;
216 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
217
218 // If the block contains no uses, the range must be live through. At one
219 // point, RegisterCoalescer could create dangling ranges that ended
220 // mid-block.
221 if (UseI == UseE || *UseI >= Stop) {
222 ++NumThroughBlocks;
223 ThroughBlocks.set(BI.MBB->getNumber());
224 // The range shouldn't end mid-block if there are no uses. This shouldn't
225 // happen.
226 assert(LVI->end >= Stop && "range ends mid block with no uses");
227 } else {
228 // This block has uses. Find the first and last uses in the block.
229 BI.FirstInstr = *UseI;
230 assert(BI.FirstInstr >= Start);
231 do ++UseI;
232 while (UseI != UseE && *UseI < Stop);
233 BI.LastInstr = UseI[-1];
234 assert(BI.LastInstr < Stop);
235
236 // LVI is the first live segment overlapping MBB.
237 BI.LiveIn = LVI->start <= Start;
238
239 // When not live in, the first use should be a def.
240 if (!BI.LiveIn) {
241 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
242 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
243 BI.FirstDef = BI.FirstInstr;
244 }
245
246 // Look for gaps in the live range.
247 BI.LiveOut = true;
248 while (LVI->end < Stop) {
249 SlotIndex LastStop = LVI->end;
250 if (++LVI == LVE || LVI->start >= Stop) {
251 BI.LiveOut = false;
252 BI.LastInstr = LastStop;
253 break;
254 }
255
256 if (LastStop < LVI->start) {
257 // There is a gap in the live range. Create duplicate entries for the
258 // live-in snippet and the live-out snippet.
259 ++NumGapBlocks;
260
261 // Push the Live-in part.
262 BI.LiveOut = false;
263 UseBlocks.push_back(BI);
264 UseBlocks.back().LastInstr = LastStop;
265
266 // Set up BI for the live-out part.
267 BI.LiveIn = false;
268 BI.LiveOut = true;
269 BI.FirstInstr = BI.FirstDef = LVI->start;
270 }
271
272 // A Segment that starts in the middle of the block must be a def.
273 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
274 if (!BI.FirstDef)
275 BI.FirstDef = LVI->start;
276 }
277
278 UseBlocks.push_back(BI);
279
280 // LVI is now at LVE or LVI->end >= Stop.
281 if (LVI == LVE)
282 break;
283 }
284
285 // Live segment ends exactly at Stop. Move to the next segment.
286 if (LVI->end == Stop && ++LVI == LVE)
287 break;
288
289 // Pick the next basic block.
290 if (LVI->start < Stop)
291 ++MFI;
292 else
293 MFI = LIS.getMBBFromIndex(LVI->start)->getIterator();
294 }
295
296 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
297}
298
300 if (cli->empty())
301 return 0;
302 LiveInterval *li = const_cast<LiveInterval*>(cli);
303 LiveInterval::iterator LVI = li->begin();
304 LiveInterval::iterator LVE = li->end();
305 unsigned Count = 0;
306
307 // Loop over basic blocks where li is live.
309 LIS.getMBBFromIndex(LVI->start)->getIterator();
310 SlotIndex Stop = LIS.getMBBEndIdx(&*MFI);
311 while (true) {
312 ++Count;
313 LVI = li->advanceTo(LVI, Stop);
314 if (LVI == LVE)
315 return Count;
316 do {
317 ++MFI;
318 Stop = LIS.getMBBEndIdx(&*MFI);
319 } while (Stop <= LVI->start);
320 }
321}
322
324 Register OrigReg = VRM.getOriginal(CurLI->reg());
325 const LiveInterval &Orig = LIS.getInterval(OrigReg);
326 assert(!Orig.empty() && "Splitting empty interval?");
328
329 // Range containing Idx should begin at Idx.
330 if (I != Orig.end() && I->start <= Idx)
331 return I->start == Idx;
332
333 // Range does not contain Idx, previous must end at Idx.
334 return I != Orig.begin() && (--I)->end == Idx;
335}
336
338 clear();
339 CurLI = li;
340 analyzeUses();
341}
342
343//===----------------------------------------------------------------------===//
344// Split Editor
345//===----------------------------------------------------------------------===//
346
347/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
351 : SA(SA), LIS(LIS), VRM(VRM), MRI(VRM.getMachineFunction().getRegInfo()),
352 MDT(MDT), TII(*VRM.getMachineFunction().getSubtarget().getInstrInfo()),
353 TRI(*VRM.getMachineFunction().getSubtarget().getRegisterInfo()),
354 MBFI(MBFI), VRAI(VRAI), RegAssign(Allocator) {}
355
357 Edit = &LRE;
358 SpillMode = SM;
359 OpenIdx = 0;
360 RegAssign.clear();
361 Values.clear();
362
363 // Reset the LiveIntervalCalc instances needed for this spill mode.
364 LICalc[0].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
365 &LIS.getVNInfoAllocator());
366 if (SpillMode)
367 LICalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
368 &LIS.getVNInfoAllocator());
369
370 Edit->anyRematerializable();
371}
372
373#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
375 if (RegAssign.empty()) {
376 dbgs() << " empty\n";
377 return;
378 }
379
380 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
381 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
382 dbgs() << '\n';
383}
384#endif
385
386/// Find a subrange corresponding to the exact lane mask @p LM in the live
387/// interval @p LI. The interval @p LI is assumed to contain such a subrange.
388/// This function is used to find corresponding subranges between the
389/// original interval and the new intervals.
390template <typename T> auto &getSubrangeImpl(LaneBitmask LM, T &LI) {
391 for (auto &S : LI.subranges())
392 if (S.LaneMask == LM)
393 return S;
394 llvm_unreachable("SubRange for this mask not found");
395}
396
398 LiveInterval &LI) {
399 return getSubrangeImpl(LM, LI);
400}
401
403 const LiveInterval &LI) {
404 return getSubrangeImpl(LM, LI);
405}
406
407/// Find a subrange corresponding to the lane mask @p LM, or a superset of it,
408/// in the live interval @p LI. The interval @p LI is assumed to contain such
409/// a subrange. This function is used to find corresponding subranges between
410/// the original interval and the new intervals.
412 const LiveInterval &LI) {
413 for (const LiveInterval::SubRange &S : LI.subranges())
414 if ((S.LaneMask & LM) == LM)
415 return S;
416 llvm_unreachable("SubRange for this mask not found");
417}
418
419void SplitEditor::addDeadDef(LiveInterval &LI, VNInfo *VNI, bool Original) {
420 if (!LI.hasSubRanges()) {
421 LI.createDeadDef(VNI);
422 return;
423 }
424
425 SlotIndex Def = VNI->def;
426 if (Original) {
427 // If we are transferring a def from the original interval, make sure
428 // to only update the subranges for which the original subranges had
429 // a def at this location.
430 for (LiveInterval::SubRange &S : LI.subranges()) {
431 auto &PS = getSubRangeForMask(S.LaneMask, Edit->getParent());
432 VNInfo *PV = PS.getVNInfoAt(Def);
433 if (PV != nullptr && PV->def == Def)
434 S.createDeadDef(Def, LIS.getVNInfoAllocator());
435 }
436 } else {
437 // This is a new def: either from rematerialization, or from an inserted
438 // copy. Since rematerialization can regenerate a definition of a sub-
439 // register, we need to check which subranges need to be updated.
441 assert(DefMI != nullptr);
442 LaneBitmask LM;
443 for (const MachineOperand &DefOp : DefMI->defs()) {
444 Register R = DefOp.getReg();
445 if (R != LI.reg())
446 continue;
447 if (unsigned SR = DefOp.getSubReg())
448 LM |= TRI.getSubRegIndexLaneMask(SR);
449 else {
450 LM = MRI.getMaxLaneMaskForVReg(R);
451 break;
452 }
453 }
454 for (LiveInterval::SubRange &S : LI.subranges())
455 if ((S.LaneMask & LM).any())
456 S.createDeadDef(Def, LIS.getVNInfoAllocator());
457 }
458}
459
460VNInfo *SplitEditor::defValue(unsigned RegIdx,
461 const VNInfo *ParentVNI,
463 bool Original) {
464 assert(ParentVNI && "Mapping NULL value");
465 assert(Idx.isValid() && "Invalid SlotIndex");
466 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
467 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
468
469 // Create a new value.
470 VNInfo *VNI = LI->getNextValue(Idx, LIS.getVNInfoAllocator());
471
472 bool Force = LI->hasSubRanges();
473 ValueForcePair FP(Force ? nullptr : VNI, Force);
474 // Use insert for lookup, so we can add missing values with a second lookup.
475 std::pair<ValueMap::iterator, bool> InsP =
476 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), FP));
477
478 // This was the first time (RegIdx, ParentVNI) was mapped, and it is not
479 // forced. Keep it as a simple def without any liveness.
480 if (!Force && InsP.second)
481 return VNI;
482
483 // If the previous value was a simple mapping, add liveness for it now.
484 if (VNInfo *OldVNI = InsP.first->second.getPointer()) {
485 addDeadDef(*LI, OldVNI, Original);
486
487 // No longer a simple mapping. Switch to a complex mapping. If the
488 // interval has subranges, make it a forced mapping.
489 InsP.first->second = ValueForcePair(nullptr, Force);
490 }
491
492 // This is a complex mapping, add liveness for VNI
493 addDeadDef(*LI, VNI, Original);
494 return VNI;
495}
496
497void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) {
498 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI.id)];
499 VNInfo *VNI = VFP.getPointer();
500
501 // ParentVNI was either unmapped or already complex mapped. Either way, just
502 // set the force bit.
503 if (!VNI) {
504 VFP.setInt(true);
505 return;
506 }
507
508 // This was previously a single mapping. Make sure the old def is represented
509 // by a trivial live range.
510 addDeadDef(LIS.getInterval(Edit->get(RegIdx)), VNI, false);
511
512 // Mark as complex mapped, forced.
513 VFP = ValueForcePair(nullptr, true);
514}
515
516SlotIndex SplitEditor::buildSingleSubRegCopy(
517 Register FromReg, Register ToReg, MachineBasicBlock &MBB,
518 MachineBasicBlock::iterator InsertBefore, unsigned SubIdx,
519 LiveInterval &DestLI, bool Late, SlotIndex Def, const MCInstrDesc &Desc) {
520 bool FirstCopy = !Def.isValid();
521 MachineInstr *CopyMI = BuildMI(MBB, InsertBefore, DebugLoc(), Desc)
522 .addReg(ToReg, RegState::Define | getUndefRegState(FirstCopy)
523 | getInternalReadRegState(!FirstCopy), SubIdx)
524 .addReg(FromReg, 0, SubIdx);
525
526 SlotIndexes &Indexes = *LIS.getSlotIndexes();
527 if (FirstCopy) {
528 Def = Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
529 } else {
530 CopyMI->bundleWithPred();
531 }
532 return Def;
533}
534
535SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg,
537 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) {
538 const MCInstrDesc &Desc =
539 TII.get(TII.getLiveRangeSplitOpcode(FromReg, *MBB.getParent()));
540 SlotIndexes &Indexes = *LIS.getSlotIndexes();
541 if (LaneMask.all() || LaneMask == MRI.getMaxLaneMaskForVReg(FromReg)) {
542 // The full vreg is copied.
543 MachineInstr *CopyMI =
544 BuildMI(MBB, InsertBefore, DebugLoc(), Desc, ToReg).addReg(FromReg);
545 return Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
546 }
547
548 // Only a subset of lanes needs to be copied. The following is a simple
549 // heuristic to construct a sequence of COPYs. We could add a target
550 // specific callback if this turns out to be suboptimal.
551 LiveInterval &DestLI = LIS.getInterval(Edit->get(RegIdx));
552
553 // First pass: Try to find a perfectly matching subregister index. If none
554 // exists find the one covering the most lanemask bits.
555 const TargetRegisterClass *RC = MRI.getRegClass(FromReg);
556 assert(RC == MRI.getRegClass(ToReg) && "Should have same reg class");
557
558 SmallVector<unsigned, 8> SubIndexes;
559
560 // Abort if we cannot possibly implement the COPY with the given indexes.
561 if (!TRI.getCoveringSubRegIndexes(MRI, RC, LaneMask, SubIndexes))
562 report_fatal_error("Impossible to implement partial COPY");
563
565 for (unsigned BestIdx : SubIndexes) {
566 Def = buildSingleSubRegCopy(FromReg, ToReg, MBB, InsertBefore, BestIdx,
567 DestLI, Late, Def, Desc);
568 }
569
570 BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator();
571 DestLI.refineSubRanges(
572 Allocator, LaneMask,
573 [Def, &Allocator](LiveInterval::SubRange &SR) {
574 SR.createDeadDef(Def, Allocator);
575 },
576 Indexes, TRI);
577
578 return Def;
579}
580
581VNInfo *SplitEditor::defFromParent(unsigned RegIdx, const VNInfo *ParentVNI,
585 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
586
587 // We may be trying to avoid interference that ends at a deleted instruction,
588 // so always begin RegIdx 0 early and all others late.
589 bool Late = RegIdx != 0;
590
591 // Attempt cheap-as-a-copy rematerialization.
592 Register Original = VRM.getOriginal(Edit->get(RegIdx));
593 LiveInterval &OrigLI = LIS.getInterval(Original);
594 VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx);
595
596 Register Reg = LI->reg();
597 bool DidRemat = false;
598 if (OrigVNI) {
599 LiveRangeEdit::Remat RM(ParentVNI);
600 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def);
601 if (Edit->canRematerializeAt(RM, OrigVNI, UseIdx, true)) {
602 Def = Edit->rematerializeAt(MBB, I, Reg, RM, TRI, Late);
603 ++NumRemats;
604 DidRemat = true;
605 }
606 }
607 if (!DidRemat) {
608 LaneBitmask LaneMask;
609 if (OrigLI.hasSubRanges()) {
610 LaneMask = LaneBitmask::getNone();
611 for (LiveInterval::SubRange &S : OrigLI.subranges()) {
612 if (S.liveAt(UseIdx))
613 LaneMask |= S.LaneMask;
614 }
615 } else {
616 LaneMask = LaneBitmask::getAll();
617 }
618
619 if (LaneMask.none()) {
620 const MCInstrDesc &Desc = TII.get(TargetOpcode::IMPLICIT_DEF);
621 MachineInstr *ImplicitDef = BuildMI(MBB, I, DebugLoc(), Desc, Reg);
622 SlotIndexes &Indexes = *LIS.getSlotIndexes();
623 Def = Indexes.insertMachineInstrInMaps(*ImplicitDef, Late).getRegSlot();
624 } else {
625 ++NumCopies;
626 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx);
627 }
628 }
629
630 // Define the value in Reg.
631 return defValue(RegIdx, ParentVNI, Def, false);
632}
633
634/// Create a new virtual register and live interval.
636 // Create the complement as index 0.
637 if (Edit->empty())
638 Edit->createEmptyInterval();
639
640 // Create the open interval.
641 OpenIdx = Edit->size();
642 Edit->createEmptyInterval();
643 return OpenIdx;
644}
645
647 assert(Idx != 0 && "Cannot select the complement interval");
648 assert(Idx < Edit->size() && "Can only select previously opened interval");
649 LLVM_DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
650 OpenIdx = Idx;
651}
652
654 assert(OpenIdx && "openIntv not called before enterIntvBefore");
655 LLVM_DEBUG(dbgs() << " enterIntvBefore " << Idx);
656 Idx = Idx.getBaseIndex();
657 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
658 if (!ParentVNI) {
659 LLVM_DEBUG(dbgs() << ": not live\n");
660 return Idx;
661 }
662 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
664 assert(MI && "enterIntvBefore called with invalid index");
665
666 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
667 return VNI->def;
668}
669
671 assert(OpenIdx && "openIntv not called before enterIntvAfter");
672 LLVM_DEBUG(dbgs() << " enterIntvAfter " << Idx);
673 Idx = Idx.getBoundaryIndex();
674 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
675 if (!ParentVNI) {
676 LLVM_DEBUG(dbgs() << ": not live\n");
677 return Idx;
678 }
679 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
681 assert(MI && "enterIntvAfter called with invalid index");
682
683 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
684 std::next(MachineBasicBlock::iterator(MI)));
685 return VNI->def;
686}
687
689 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
691 SlotIndex Last = End.getPrevSlot();
692 LLVM_DEBUG(dbgs() << " enterIntvAtEnd " << printMBBReference(MBB) << ", "
693 << Last);
694 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
695 if (!ParentVNI) {
696 LLVM_DEBUG(dbgs() << ": not live\n");
697 return End;
698 }
700 if (LSP < Last) {
701 // It could be that the use after LSP is a def, and thus the ParentVNI
702 // just selected starts at that def. For this case to exist, the def
703 // must be part of a tied def/use pair (as otherwise we'd have split
704 // distinct live ranges into individual live intervals), and thus we
705 // can insert the def into the VNI of the use and the tied def/use
706 // pair can live in the resulting interval.
707 Last = LSP;
708 ParentVNI = Edit->getParent().getVNInfoAt(Last);
709 if (!ParentVNI) {
710 // undef use --> undef tied def
711 LLVM_DEBUG(dbgs() << ": tied use not live\n");
712 return End;
713 }
714 }
715
716 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id);
717 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
719 RegAssign.insert(VNI->def, End, OpenIdx);
720 LLVM_DEBUG(dump());
721 return VNI->def;
722}
723
724/// useIntv - indicate that all instructions in MBB should use OpenLI.
727}
728
730 assert(OpenIdx && "openIntv not called before useIntv");
731 LLVM_DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
732 RegAssign.insert(Start, End, OpenIdx);
733 LLVM_DEBUG(dump());
734}
735
737 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
738 LLVM_DEBUG(dbgs() << " leaveIntvAfter " << Idx);
739
740 // The interval must be live beyond the instruction at Idx.
741 SlotIndex Boundary = Idx.getBoundaryIndex();
742 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Boundary);
743 if (!ParentVNI) {
744 LLVM_DEBUG(dbgs() << ": not live\n");
745 return Boundary.getNextSlot();
746 }
747 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
748 MachineInstr *MI = LIS.getInstructionFromIndex(Boundary);
749 assert(MI && "No instruction at index");
750
751 // In spill mode, make live ranges as short as possible by inserting the copy
752 // before MI. This is only possible if that instruction doesn't redefine the
753 // value. The inserted COPY is not a kill, and we don't need to recompute
754 // the source live range. The spiller also won't try to hoist this copy.
755 if (SpillMode && !SlotIndex::isSameInstr(ParentVNI->def, Idx) &&
756 MI->readsVirtualRegister(Edit->getReg())) {
757 forceRecompute(0, *ParentVNI);
758 defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
759 return Idx;
760 }
761
762 VNInfo *VNI = defFromParent(0, ParentVNI, Boundary, *MI->getParent(),
763 std::next(MachineBasicBlock::iterator(MI)));
764 return VNI->def;
765}
766
768 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
769 LLVM_DEBUG(dbgs() << " leaveIntvBefore " << Idx);
770
771 // The interval must be live into the instruction at Idx.
772 Idx = Idx.getBaseIndex();
773 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
774 if (!ParentVNI) {
775 LLVM_DEBUG(dbgs() << ": not live\n");
776 return Idx.getNextSlot();
777 }
778 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
779
781 assert(MI && "No instruction at index");
782 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
783 return VNI->def;
784}
785
787 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
788 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
789 LLVM_DEBUG(dbgs() << " leaveIntvAtTop " << printMBBReference(MBB) << ", "
790 << Start);
791
792 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
793 if (!ParentVNI) {
794 LLVM_DEBUG(dbgs() << ": not live\n");
795 return Start;
796 }
797
798 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
800 RegAssign.insert(Start, VNI->def, OpenIdx);
801 LLVM_DEBUG(dump());
802 return VNI->def;
803}
804
805static bool hasTiedUseOf(MachineInstr &MI, unsigned Reg) {
806 return any_of(MI.defs(), [Reg](const MachineOperand &MO) {
807 return MO.isReg() && MO.isTied() && MO.getReg() == Reg;
808 });
809}
810
812 assert(OpenIdx && "openIntv not called before overlapIntv");
813 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
814 assert(ParentVNI == Edit->getParent().getVNInfoBefore(End) &&
815 "Parent changes value in extended range");
816 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
817 "Range cannot span basic blocks");
818
819 // The complement interval will be extended as needed by LICalc.extend().
820 if (ParentVNI)
821 forceRecompute(0, *ParentVNI);
822
823 // If the last use is tied to a def, we can't mark it as live for the
824 // interval which includes only the use. That would cause the tied pair
825 // to end up in two different intervals.
826 if (auto *MI = LIS.getInstructionFromIndex(End))
827 if (hasTiedUseOf(*MI, Edit->getReg())) {
828 LLVM_DEBUG(dbgs() << "skip overlap due to tied def at end\n");
829 return;
830 }
831
832 LLVM_DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
833 RegAssign.insert(Start, End, OpenIdx);
834 LLVM_DEBUG(dump());
835}
836
837//===----------------------------------------------------------------------===//
838// Spill modes
839//===----------------------------------------------------------------------===//
840
841void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
842 LiveInterval *LI = &LIS.getInterval(Edit->get(0));
843 LLVM_DEBUG(dbgs() << "Removing " << Copies.size() << " back-copies.\n");
845 AssignI.setMap(RegAssign);
846
847 for (const VNInfo *C : Copies) {
848 SlotIndex Def = C->def;
850 assert(MI && "No instruction for back-copy");
851
852 MachineBasicBlock *MBB = MI->getParent();
854 bool AtBegin;
855 do AtBegin = MBBI == MBB->begin();
856 while (!AtBegin && (--MBBI)->isDebugOrPseudoInstr());
857
858 LLVM_DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
859 LIS.removeVRegDefAt(*LI, Def);
861 MI->eraseFromParent();
862
863 // Adjust RegAssign if a register assignment is killed at Def. We want to
864 // avoid calculating the live range of the source register if possible.
865 AssignI.find(Def.getPrevSlot());
866 if (!AssignI.valid() || AssignI.start() >= Def)
867 continue;
868 // If MI doesn't kill the assigned register, just leave it.
869 if (AssignI.stop() != Def)
870 continue;
871 unsigned RegIdx = AssignI.value();
872 // We could hoist back-copy right after another back-copy. As a result
873 // MMBI points to copy instruction which is actually dead now.
874 // We cannot set its stop to MBBI which will be the same as start and
875 // interval does not support that.
876 SlotIndex Kill =
877 AtBegin ? SlotIndex() : LIS.getInstructionIndex(*MBBI).getRegSlot();
878 if (AtBegin || !MBBI->readsVirtualRegister(Edit->getReg()) ||
879 Kill <= AssignI.start()) {
880 LLVM_DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx
881 << '\n');
882 forceRecompute(RegIdx, *Edit->getParent().getVNInfoAt(Def));
883 } else {
884 LLVM_DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
885 AssignI.setStop(Kill);
886 }
887 }
888}
889
891SplitEditor::findShallowDominator(MachineBasicBlock *MBB,
892 MachineBasicBlock *DefMBB) {
893 if (MBB == DefMBB)
894 return MBB;
895 assert(MDT.dominates(DefMBB, MBB) && "MBB must be dominated by the def.");
896
897 const MachineLoopInfo &Loops = SA.Loops;
898 const MachineLoop *DefLoop = Loops.getLoopFor(DefMBB);
899 MachineDomTreeNode *DefDomNode = MDT[DefMBB];
900
901 // Best candidate so far.
902 MachineBasicBlock *BestMBB = MBB;
903 unsigned BestDepth = std::numeric_limits<unsigned>::max();
904
905 while (true) {
906 const MachineLoop *Loop = Loops.getLoopFor(MBB);
907
908 // MBB isn't in a loop, it doesn't get any better. All dominators have a
909 // higher frequency by definition.
910 if (!Loop) {
911 LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB)
912 << " dominates " << printMBBReference(*MBB)
913 << " at depth 0\n");
914 return MBB;
915 }
916
917 // We'll never be able to exit the DefLoop.
918 if (Loop == DefLoop) {
919 LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB)
920 << " dominates " << printMBBReference(*MBB)
921 << " in the same loop\n");
922 return MBB;
923 }
924
925 // Least busy dominator seen so far.
926 unsigned Depth = Loop->getLoopDepth();
927 if (Depth < BestDepth) {
928 BestMBB = MBB;
929 BestDepth = Depth;
930 LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB)
931 << " dominates " << printMBBReference(*MBB)
932 << " at depth " << Depth << '\n');
933 }
934
935 // Leave loop by going to the immediate dominator of the loop header.
936 // This is a bigger stride than simply walking up the dominator tree.
937 MachineDomTreeNode *IDom = MDT[Loop->getHeader()]->getIDom();
938
939 // Too far up the dominator tree?
940 if (!IDom || !MDT.dominates(DefDomNode, IDom))
941 return BestMBB;
942
943 MBB = IDom->getBlock();
944 }
945}
946
947void SplitEditor::computeRedundantBackCopies(
948 DenseSet<unsigned> &NotToHoistSet, SmallVectorImpl<VNInfo *> &BackCopies) {
949 LiveInterval *LI = &LIS.getInterval(Edit->get(0));
950 const LiveInterval *Parent = &Edit->getParent();
952 SmallPtrSet<VNInfo *, 8> DominatedVNIs;
953
954 // Aggregate VNIs having the same value as ParentVNI.
955 for (VNInfo *VNI : LI->valnos) {
956 if (VNI->isUnused())
957 continue;
958 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
959 EqualVNs[ParentVNI->id].insert(VNI);
960 }
961
962 // For VNI aggregation of each ParentVNI, collect dominated, i.e.,
963 // redundant VNIs to BackCopies.
964 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
965 const VNInfo *ParentVNI = Parent->getValNumInfo(i);
966 if (!NotToHoistSet.count(ParentVNI->id))
967 continue;
968 SmallPtrSetIterator<VNInfo *> It1 = EqualVNs[ParentVNI->id].begin();
970 for (; It1 != EqualVNs[ParentVNI->id].end(); ++It1) {
971 It2 = It1;
972 for (++It2; It2 != EqualVNs[ParentVNI->id].end(); ++It2) {
973 if (DominatedVNIs.count(*It1) || DominatedVNIs.count(*It2))
974 continue;
975
976 MachineBasicBlock *MBB1 = LIS.getMBBFromIndex((*It1)->def);
977 MachineBasicBlock *MBB2 = LIS.getMBBFromIndex((*It2)->def);
978 if (MBB1 == MBB2) {
979 DominatedVNIs.insert((*It1)->def < (*It2)->def ? (*It2) : (*It1));
980 } else if (MDT.dominates(MBB1, MBB2)) {
981 DominatedVNIs.insert(*It2);
982 } else if (MDT.dominates(MBB2, MBB1)) {
983 DominatedVNIs.insert(*It1);
984 }
985 }
986 }
987 if (!DominatedVNIs.empty()) {
988 forceRecompute(0, *ParentVNI);
989 append_range(BackCopies, DominatedVNIs);
990 DominatedVNIs.clear();
991 }
992 }
993}
994
995/// For SM_Size mode, find a common dominator for all the back-copies for
996/// the same ParentVNI and hoist the backcopies to the dominator BB.
997/// For SM_Speed mode, if the common dominator is hot and it is not beneficial
998/// to do the hoisting, simply remove the dominated backcopies for the same
999/// ParentVNI.
1000void SplitEditor::hoistCopies() {
1001 // Get the complement interval, always RegIdx 0.
1002 LiveInterval *LI = &LIS.getInterval(Edit->get(0));
1003 const LiveInterval *Parent = &Edit->getParent();
1004
1005 // Track the nearest common dominator for all back-copies for each ParentVNI,
1006 // indexed by ParentVNI->id.
1007 using DomPair = std::pair<MachineBasicBlock *, SlotIndex>;
1008 SmallVector<DomPair, 8> NearestDom(Parent->getNumValNums());
1009 // The total cost of all the back-copies for each ParentVNI.
1011 // The ParentVNI->id set for which hoisting back-copies are not beneficial
1012 // for Speed.
1013 DenseSet<unsigned> NotToHoistSet;
1014
1015 // Find the nearest common dominator for parent values with multiple
1016 // back-copies. If a single back-copy dominates, put it in DomPair.second.
1017 for (VNInfo *VNI : LI->valnos) {
1018 if (VNI->isUnused())
1019 continue;
1020 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
1021 assert(ParentVNI && "Parent not live at complement def");
1022
1023 // Don't hoist remats. The complement is probably going to disappear
1024 // completely anyway.
1025 if (Edit->didRematerialize(ParentVNI))
1026 continue;
1027
1028 MachineBasicBlock *ValMBB = LIS.getMBBFromIndex(VNI->def);
1029
1030 DomPair &Dom = NearestDom[ParentVNI->id];
1031
1032 // Keep directly defined parent values. This is either a PHI or an
1033 // instruction in the complement range. All other copies of ParentVNI
1034 // should be eliminated.
1035 if (VNI->def == ParentVNI->def) {
1036 LLVM_DEBUG(dbgs() << "Direct complement def at " << VNI->def << '\n');
1037 Dom = DomPair(ValMBB, VNI->def);
1038 continue;
1039 }
1040 // Skip the singly mapped values. There is nothing to gain from hoisting a
1041 // single back-copy.
1042 if (Values.lookup(std::make_pair(0, ParentVNI->id)).getPointer()) {
1043 LLVM_DEBUG(dbgs() << "Single complement def at " << VNI->def << '\n');
1044 continue;
1045 }
1046
1047 if (!Dom.first) {
1048 // First time we see ParentVNI. VNI dominates itself.
1049 Dom = DomPair(ValMBB, VNI->def);
1050 } else if (Dom.first == ValMBB) {
1051 // Two defs in the same block. Pick the earlier def.
1052 if (!Dom.second.isValid() || VNI->def < Dom.second)
1053 Dom.second = VNI->def;
1054 } else {
1055 // Different basic blocks. Check if one dominates.
1057 MDT.findNearestCommonDominator(Dom.first, ValMBB);
1058 if (Near == ValMBB)
1059 // Def ValMBB dominates.
1060 Dom = DomPair(ValMBB, VNI->def);
1061 else if (Near != Dom.first)
1062 // None dominate. Hoist to common dominator, need new def.
1063 Dom = DomPair(Near, SlotIndex());
1064 Costs[ParentVNI->id] += MBFI.getBlockFreq(ValMBB);
1065 }
1066
1067 LLVM_DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@'
1068 << VNI->def << " for parent " << ParentVNI->id << '@'
1069 << ParentVNI->def << " hoist to "
1070 << printMBBReference(*Dom.first) << ' ' << Dom.second
1071 << '\n');
1072 }
1073
1074 // Insert the hoisted copies.
1075 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
1076 DomPair &Dom = NearestDom[i];
1077 if (!Dom.first || Dom.second.isValid())
1078 continue;
1079 // This value needs a hoisted copy inserted at the end of Dom.first.
1080 const VNInfo *ParentVNI = Parent->getValNumInfo(i);
1081 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(ParentVNI->def);
1082 // Get a less loopy dominator than Dom.first.
1083 Dom.first = findShallowDominator(Dom.first, DefMBB);
1084 if (SpillMode == SM_Speed &&
1085 MBFI.getBlockFreq(Dom.first) > Costs[ParentVNI->id]) {
1086 NotToHoistSet.insert(ParentVNI->id);
1087 continue;
1088 }
1089 SlotIndex LSP = SA.getLastSplitPoint(Dom.first);
1090 if (LSP <= ParentVNI->def) {
1091 NotToHoistSet.insert(ParentVNI->id);
1092 continue;
1093 }
1094 Dom.second = defFromParent(0, ParentVNI, LSP, *Dom.first,
1095 SA.getLastSplitPointIter(Dom.first))->def;
1096 }
1097
1098 // Remove redundant back-copies that are now known to be dominated by another
1099 // def with the same value.
1100 SmallVector<VNInfo*, 8> BackCopies;
1101 for (VNInfo *VNI : LI->valnos) {
1102 if (VNI->isUnused())
1103 continue;
1104 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
1105 const DomPair &Dom = NearestDom[ParentVNI->id];
1106 if (!Dom.first || Dom.second == VNI->def ||
1107 NotToHoistSet.count(ParentVNI->id))
1108 continue;
1109 BackCopies.push_back(VNI);
1110 forceRecompute(0, *ParentVNI);
1111 }
1112
1113 // If it is not beneficial to hoist all the BackCopies, simply remove
1114 // redundant BackCopies in speed mode.
1115 if (SpillMode == SM_Speed && !NotToHoistSet.empty())
1116 computeRedundantBackCopies(NotToHoistSet, BackCopies);
1117
1118 removeBackCopies(BackCopies);
1119}
1120
1121/// transferValues - Transfer all possible values to the new live ranges.
1122/// Values that were rematerialized are left alone, they need LICalc.extend().
1123bool SplitEditor::transferValues() {
1124 bool Skipped = false;
1125 RegAssignMap::const_iterator AssignI = RegAssign.begin();
1126 for (const LiveRange::Segment &S : Edit->getParent()) {
1127 LLVM_DEBUG(dbgs() << " blit " << S << ':');
1128 VNInfo *ParentVNI = S.valno;
1129 // RegAssign has holes where RegIdx 0 should be used.
1130 SlotIndex Start = S.start;
1131 AssignI.advanceTo(Start);
1132 do {
1133 unsigned RegIdx;
1134 SlotIndex End = S.end;
1135 if (!AssignI.valid()) {
1136 RegIdx = 0;
1137 } else if (AssignI.start() <= Start) {
1138 RegIdx = AssignI.value();
1139 if (AssignI.stop() < End) {
1140 End = AssignI.stop();
1141 ++AssignI;
1142 }
1143 } else {
1144 RegIdx = 0;
1145 End = std::min(End, AssignI.start());
1146 }
1147
1148 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
1149 LLVM_DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx << '('
1150 << printReg(Edit->get(RegIdx)) << ')');
1151 LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
1152
1153 // Check for a simply defined value that can be blitted directly.
1154 ValueForcePair VFP = Values.lookup(std::make_pair(RegIdx, ParentVNI->id));
1155 if (VNInfo *VNI = VFP.getPointer()) {
1156 LLVM_DEBUG(dbgs() << ':' << VNI->id);
1157 LI.addSegment(LiveInterval::Segment(Start, End, VNI));
1158 Start = End;
1159 continue;
1160 }
1161
1162 // Skip values with forced recomputation.
1163 if (VFP.getInt()) {
1164 LLVM_DEBUG(dbgs() << "(recalc)");
1165 Skipped = true;
1166 Start = End;
1167 continue;
1168 }
1169
1170 LiveIntervalCalc &LIC = getLICalc(RegIdx);
1171
1172 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
1173 // so the live range is accurate. Add live-in blocks in [Start;End) to the
1174 // LiveInBlocks.
1176 SlotIndex BlockStart, BlockEnd;
1177 std::tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(&*MBB);
1178
1179 // The first block may be live-in, or it may have its own def.
1180 if (Start != BlockStart) {
1181 VNInfo *VNI = LI.extendInBlock(BlockStart, std::min(BlockEnd, End));
1182 assert(VNI && "Missing def for complex mapped value");
1183 LLVM_DEBUG(dbgs() << ':' << VNI->id << "*" << printMBBReference(*MBB));
1184 // MBB has its own def. Is it also live-out?
1185 if (BlockEnd <= End)
1186 LIC.setLiveOutValue(&*MBB, VNI);
1187
1188 // Skip to the next block for live-in.
1189 ++MBB;
1190 BlockStart = BlockEnd;
1191 }
1192
1193 // Handle the live-in blocks covered by [Start;End).
1194 assert(Start <= BlockStart && "Expected live-in block");
1195 while (BlockStart < End) {
1196 LLVM_DEBUG(dbgs() << ">" << printMBBReference(*MBB));
1197 BlockEnd = LIS.getMBBEndIdx(&*MBB);
1198 if (BlockStart == ParentVNI->def) {
1199 // This block has the def of a parent PHI, so it isn't live-in.
1200 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
1201 VNInfo *VNI = LI.extendInBlock(BlockStart, std::min(BlockEnd, End));
1202 assert(VNI && "Missing def for complex mapped parent PHI");
1203 if (End >= BlockEnd)
1204 LIC.setLiveOutValue(&*MBB, VNI); // Live-out as well.
1205 } else {
1206 // This block needs a live-in value. The last block covered may not
1207 // be live-out.
1208 if (End < BlockEnd)
1209 LIC.addLiveInBlock(LI, MDT[&*MBB], End);
1210 else {
1211 // Live-through, and we don't know the value.
1212 LIC.addLiveInBlock(LI, MDT[&*MBB]);
1213 LIC.setLiveOutValue(&*MBB, nullptr);
1214 }
1215 }
1216 BlockStart = BlockEnd;
1217 ++MBB;
1218 }
1219 Start = End;
1220 } while (Start != S.end);
1221 LLVM_DEBUG(dbgs() << '\n');
1222 }
1223
1224 LICalc[0].calculateValues();
1225 if (SpillMode)
1226 LICalc[1].calculateValues();
1227
1228 return Skipped;
1229}
1230
1232 const LiveRange::Segment *Seg = LR.getSegmentContaining(Def);
1233 if (Seg == nullptr)
1234 return true;
1235 if (Seg->end != Def.getDeadSlot())
1236 return false;
1237 // This is a dead PHI. Remove it.
1238 LR.removeSegment(*Seg, true);
1239 return true;
1240}
1241
1242void SplitEditor::extendPHIRange(MachineBasicBlock &B, LiveIntervalCalc &LIC,
1243 LiveRange &LR, LaneBitmask LM,
1244 ArrayRef<SlotIndex> Undefs) {
1245 for (MachineBasicBlock *P : B.predecessors()) {
1246 SlotIndex End = LIS.getMBBEndIdx(P);
1247 SlotIndex LastUse = End.getPrevSlot();
1248 // The predecessor may not have a live-out value. That is OK, like an
1249 // undef PHI operand.
1250 const LiveInterval &PLI = Edit->getParent();
1251 // Need the cast because the inputs to ?: would otherwise be deemed
1252 // "incompatible": SubRange vs LiveInterval.
1253 const LiveRange &PSR = !LM.all() ? getSubRangeForMaskExact(LM, PLI)
1254 : static_cast<const LiveRange &>(PLI);
1255 if (PSR.liveAt(LastUse))
1256 LIC.extend(LR, End, /*PhysReg=*/0, Undefs);
1257 }
1258}
1259
1260void SplitEditor::extendPHIKillRanges() {
1261 // Extend live ranges to be live-out for successor PHI values.
1262
1263 // Visit each PHI def slot in the parent live interval. If the def is dead,
1264 // remove it. Otherwise, extend the live interval to reach the end indexes
1265 // of all predecessor blocks.
1266
1267 const LiveInterval &ParentLI = Edit->getParent();
1268 for (const VNInfo *V : ParentLI.valnos) {
1269 if (V->isUnused() || !V->isPHIDef())
1270 continue;
1271
1272 unsigned RegIdx = RegAssign.lookup(V->def);
1273 LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
1274 LiveIntervalCalc &LIC = getLICalc(RegIdx);
1275 MachineBasicBlock &B = *LIS.getMBBFromIndex(V->def);
1276 if (!removeDeadSegment(V->def, LI))
1277 extendPHIRange(B, LIC, LI, LaneBitmask::getAll(), /*Undefs=*/{});
1278 }
1279
1281 LiveIntervalCalc SubLIC;
1282
1283 for (const LiveInterval::SubRange &PS : ParentLI.subranges()) {
1284 for (const VNInfo *V : PS.valnos) {
1285 if (V->isUnused() || !V->isPHIDef())
1286 continue;
1287 unsigned RegIdx = RegAssign.lookup(V->def);
1288 LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
1289 LiveInterval::SubRange &S = getSubRangeForMaskExact(PS.LaneMask, LI);
1290 if (removeDeadSegment(V->def, S))
1291 continue;
1292
1293 MachineBasicBlock &B = *LIS.getMBBFromIndex(V->def);
1294 SubLIC.reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
1295 &LIS.getVNInfoAllocator());
1296 Undefs.clear();
1297 LI.computeSubRangeUndefs(Undefs, PS.LaneMask, MRI, *LIS.getSlotIndexes());
1298 extendPHIRange(B, SubLIC, S, PS.LaneMask, Undefs);
1299 }
1300 }
1301}
1302
1303/// rewriteAssigned - Rewrite all uses of Edit->getReg().
1304void SplitEditor::rewriteAssigned(bool ExtendRanges) {
1305 struct ExtPoint {
1306 ExtPoint(const MachineOperand &O, unsigned R, SlotIndex N)
1307 : MO(O), RegIdx(R), Next(N) {}
1308
1309 MachineOperand MO;
1310 unsigned RegIdx;
1311 SlotIndex Next;
1312 };
1313
1314 SmallVector<ExtPoint,4> ExtPoints;
1315
1316 for (MachineOperand &MO :
1317 llvm::make_early_inc_range(MRI.reg_operands(Edit->getReg()))) {
1318 MachineInstr *MI = MO.getParent();
1319 // LiveDebugVariables should have handled all DBG_VALUE instructions.
1320 if (MI->isDebugValue()) {
1321 LLVM_DEBUG(dbgs() << "Zapping " << *MI);
1322 MO.setReg(0);
1323 continue;
1324 }
1325
1326 // <undef> operands don't really read the register, so it doesn't matter
1327 // which register we choose. When the use operand is tied to a def, we must
1328 // use the same register as the def, so just do that always.
1330 if (MO.isDef() || MO.isUndef())
1331 Idx = Idx.getRegSlot(MO.isEarlyClobber());
1332
1333 // Rewrite to the mapped register at Idx.
1334 unsigned RegIdx = RegAssign.lookup(Idx);
1335 LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
1336 MO.setReg(LI.reg());
1337 LLVM_DEBUG(dbgs() << " rewr " << printMBBReference(*MI->getParent())
1338 << '\t' << Idx << ':' << RegIdx << '\t' << *MI);
1339
1340 // Extend liveness to Idx if the instruction reads reg.
1341 if (!ExtendRanges || MO.isUndef())
1342 continue;
1343
1344 // Skip instructions that don't read Reg.
1345 if (MO.isDef()) {
1346 if (!MO.getSubReg() && !MO.isEarlyClobber())
1347 continue;
1348 // We may want to extend a live range for a partial redef, or for a use
1349 // tied to an early clobber.
1350 if (!Edit->getParent().liveAt(Idx.getPrevSlot()))
1351 continue;
1352 } else {
1353 assert(MO.isUse());
1354 bool IsEarlyClobber = false;
1355 if (MO.isTied()) {
1356 // We want to extend a live range into `e` slot rather than `r` slot if
1357 // tied-def is early clobber, because the `e` slot already contained
1358 // in the live range of early-clobber tied-def operand, give an example
1359 // here:
1360 // 0 %0 = ...
1361 // 16 early-clobber %0 = Op %0 (tied-def 0), ...
1362 // 32 ... = Op %0
1363 // Before extend:
1364 // %0 = [0r, 0d) [16e, 32d)
1365 // The point we want to extend is 0d to 16e not 16r in this case, but if
1366 // we use 16r here we will extend nothing because that already contained
1367 // in [16e, 32d).
1368 unsigned OpIdx = MO.getOperandNo();
1369 unsigned DefOpIdx = MI->findTiedOperandIdx(OpIdx);
1370 const MachineOperand &DefOp = MI->getOperand(DefOpIdx);
1371 IsEarlyClobber = DefOp.isEarlyClobber();
1372 }
1373
1374 Idx = Idx.getRegSlot(IsEarlyClobber);
1375 }
1376
1377 SlotIndex Next = Idx;
1378 if (LI.hasSubRanges()) {
1379 // We have to delay extending subranges until we have seen all operands
1380 // defining the register. This is because a <def,read-undef> operand
1381 // will create an "undef" point, and we cannot extend any subranges
1382 // until all of them have been accounted for.
1383 if (MO.isUse())
1384 ExtPoints.push_back(ExtPoint(MO, RegIdx, Next));
1385 } else {
1386 LiveIntervalCalc &LIC = getLICalc(RegIdx);
1387 LIC.extend(LI, Next, 0, ArrayRef<SlotIndex>());
1388 }
1389 }
1390
1391 for (ExtPoint &EP : ExtPoints) {
1392 LiveInterval &LI = LIS.getInterval(Edit->get(EP.RegIdx));
1393 assert(LI.hasSubRanges());
1394
1395 LiveIntervalCalc SubLIC;
1396 Register Reg = EP.MO.getReg(), Sub = EP.MO.getSubReg();
1397 LaneBitmask LM = Sub != 0 ? TRI.getSubRegIndexLaneMask(Sub)
1398 : MRI.getMaxLaneMaskForVReg(Reg);
1399 for (LiveInterval::SubRange &S : LI.subranges()) {
1400 if ((S.LaneMask & LM).none())
1401 continue;
1402 // The problem here can be that the new register may have been created
1403 // for a partially defined original register. For example:
1404 // %0:subreg_hireg<def,read-undef> = ...
1405 // ...
1406 // %1 = COPY %0
1407 if (S.empty())
1408 continue;
1409 SubLIC.reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
1410 &LIS.getVNInfoAllocator());
1412 LI.computeSubRangeUndefs(Undefs, S.LaneMask, MRI, *LIS.getSlotIndexes());
1413 SubLIC.extend(S, EP.Next, 0, Undefs);
1414 }
1415 }
1416
1417 for (Register R : *Edit) {
1418 LiveInterval &LI = LIS.getInterval(R);
1419 if (!LI.hasSubRanges())
1420 continue;
1421 LI.clear();
1424 }
1425}
1426
1427void SplitEditor::deleteRematVictims() {
1429 for (const Register &R : *Edit) {
1430 LiveInterval *LI = &LIS.getInterval(R);
1431 for (const LiveRange::Segment &S : LI->segments) {
1432 // Dead defs end at the dead slot.
1433 if (S.end != S.valno->def.getDeadSlot())
1434 continue;
1435 if (S.valno->isPHIDef())
1436 continue;
1438 assert(MI && "Missing instruction for dead def");
1439 MI->addRegisterDead(LI->reg(), &TRI);
1440
1441 if (!MI->allDefsAreDead())
1442 continue;
1443
1444 LLVM_DEBUG(dbgs() << "All defs dead: " << *MI);
1445 Dead.push_back(MI);
1446 }
1447 }
1448
1449 if (Dead.empty())
1450 return;
1451
1452 Edit->eliminateDeadDefs(Dead, std::nullopt);
1453}
1454
1455void SplitEditor::forceRecomputeVNI(const VNInfo &ParentVNI) {
1456 // Fast-path for common case.
1457 if (!ParentVNI.isPHIDef()) {
1458 for (unsigned I = 0, E = Edit->size(); I != E; ++I)
1459 forceRecompute(I, ParentVNI);
1460 return;
1461 }
1462
1463 // Trace value through phis.
1464 SmallPtrSet<const VNInfo *, 8> Visited; ///< whether VNI was/is in worklist.
1466 Visited.insert(&ParentVNI);
1467 WorkList.push_back(&ParentVNI);
1468
1469 const LiveInterval &ParentLI = Edit->getParent();
1470 const SlotIndexes &Indexes = *LIS.getSlotIndexes();
1471 do {
1472 const VNInfo &VNI = *WorkList.back();
1473 WorkList.pop_back();
1474 for (unsigned I = 0, E = Edit->size(); I != E; ++I)
1475 forceRecompute(I, VNI);
1476 if (!VNI.isPHIDef())
1477 continue;
1478
1479 MachineBasicBlock &MBB = *Indexes.getMBBFromIndex(VNI.def);
1480 for (const MachineBasicBlock *Pred : MBB.predecessors()) {
1481 SlotIndex PredEnd = Indexes.getMBBEndIdx(Pred);
1482 VNInfo *PredVNI = ParentLI.getVNInfoBefore(PredEnd);
1483 assert(PredVNI && "Value available in PhiVNI predecessor");
1484 if (Visited.insert(PredVNI).second)
1485 WorkList.push_back(PredVNI);
1486 }
1487 } while(!WorkList.empty());
1488}
1489
1491 ++NumFinished;
1492
1493 // At this point, the live intervals in Edit contain VNInfos corresponding to
1494 // the inserted copies.
1495
1496 // Add the original defs from the parent interval.
1497 for (const VNInfo *ParentVNI : Edit->getParent().valnos) {
1498 if (ParentVNI->isUnused())
1499 continue;
1500 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
1501 defValue(RegIdx, ParentVNI, ParentVNI->def, true);
1502
1503 // Force rematted values to be recomputed everywhere.
1504 // The new live ranges may be truncated.
1505 if (Edit->didRematerialize(ParentVNI))
1506 forceRecomputeVNI(*ParentVNI);
1507 }
1508
1509 // Hoist back-copies to the complement interval when in spill mode.
1510 switch (SpillMode) {
1511 case SM_Partition:
1512 // Leave all back-copies as is.
1513 break;
1514 case SM_Size:
1515 case SM_Speed:
1516 // hoistCopies will behave differently between size and speed.
1517 hoistCopies();
1518 }
1519
1520 // Transfer the simply mapped values, check if any are skipped.
1521 bool Skipped = transferValues();
1522
1523 // Rewrite virtual registers, possibly extending ranges.
1524 rewriteAssigned(Skipped);
1525
1526 if (Skipped)
1527 extendPHIKillRanges();
1528 else
1529 ++NumSimple;
1530
1531 // Delete defs that were rematted everywhere.
1532 if (Skipped)
1533 deleteRematVictims();
1534
1535 // Get rid of unused values and set phi-kill flags.
1536 for (Register Reg : *Edit) {
1537 LiveInterval &LI = LIS.getInterval(Reg);
1539 LI.RenumberValues();
1540 }
1541
1542 // Provide a reverse mapping from original indices to Edit ranges.
1543 if (LRMap) {
1544 auto Seq = llvm::seq<unsigned>(0, Edit->size());
1545 LRMap->assign(Seq.begin(), Seq.end());
1546 }
1547
1548 // Now check if any registers were separated into multiple components.
1549 ConnectedVNInfoEqClasses ConEQ(LIS);
1550 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
1551 // Don't use iterators, they are invalidated by create() below.
1552 Register VReg = Edit->get(i);
1553 LiveInterval &LI = LIS.getInterval(VReg);
1555 LIS.splitSeparateComponents(LI, SplitLIs);
1556 Register Original = VRM.getOriginal(VReg);
1557 for (LiveInterval *SplitLI : SplitLIs)
1558 VRM.setIsSplitFromReg(SplitLI->reg(), Original);
1559
1560 // The new intervals all map back to i.
1561 if (LRMap)
1562 LRMap->resize(Edit->size(), i);
1563 }
1564
1565 // Calculate spill weight and allocation hints for new intervals.
1566 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), VRAI);
1567
1568 assert(!LRMap || LRMap->size() == Edit->size());
1569}
1570
1571//===----------------------------------------------------------------------===//
1572// Single Block Splitting
1573//===----------------------------------------------------------------------===//
1574
1576 bool SingleInstrs) const {
1577 // Always split for multiple instructions.
1578 if (!BI.isOneInstr())
1579 return true;
1580 // Don't split for single instructions unless explicitly requested.
1581 if (!SingleInstrs)
1582 return false;
1583 // Splitting a live-through range always makes progress.
1584 if (BI.LiveIn && BI.LiveOut)
1585 return true;
1586 // No point in isolating a copy. It has no register class constraints.
1588 bool copyLike = TII.isCopyInstr(*MI) || MI->isSubregToReg();
1589 if (copyLike)
1590 return false;
1591 // Finally, don't isolate an end point that was created by earlier splits.
1592 return isOriginalEndpoint(BI.FirstInstr);
1593}
1594
1596 openIntv();
1597 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB);
1598 SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstInstr,
1599 LastSplitPoint));
1600 if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
1601 useIntv(SegStart, leaveIntvAfter(BI.LastInstr));
1602 } else {
1603 // The last use is after the last valid split point.
1604 SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
1605 useIntv(SegStart, SegStop);
1606 overlapIntv(SegStop, BI.LastInstr);
1607 }
1608}
1609
1610//===----------------------------------------------------------------------===//
1611// Global Live Range Splitting Support
1612//===----------------------------------------------------------------------===//
1613
1614// These methods support a method of global live range splitting that uses a
1615// global algorithm to decide intervals for CFG edges. They will insert split
1616// points and color intervals in basic blocks while avoiding interference.
1617//
1618// Note that splitSingleBlock is also useful for blocks where both CFG edges
1619// are on the stack.
1620
1622 unsigned IntvIn, SlotIndex LeaveBefore,
1623 unsigned IntvOut, SlotIndex EnterAfter){
1624 SlotIndex Start, Stop;
1625 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
1626
1627 LLVM_DEBUG(dbgs() << "%bb." << MBBNum << " [" << Start << ';' << Stop
1628 << ") intf " << LeaveBefore << '-' << EnterAfter
1629 << ", live-through " << IntvIn << " -> " << IntvOut);
1630
1631 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
1632
1633 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
1634 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1635 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
1636
1638
1639 if (!IntvOut) {
1640 LLVM_DEBUG(dbgs() << ", spill on entry.\n");
1641 //
1642 // <<<<<<<<< Possible LeaveBefore interference.
1643 // |-----------| Live through.
1644 // -____________ Spill on entry.
1645 //
1646 selectIntv(IntvIn);
1648 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1649 (void)Idx;
1650 return;
1651 }
1652
1653 if (!IntvIn) {
1654 LLVM_DEBUG(dbgs() << ", reload on exit.\n");
1655 //
1656 // >>>>>>> Possible EnterAfter interference.
1657 // |-----------| Live through.
1658 // ___________-- Reload on exit.
1659 //
1660 selectIntv(IntvOut);
1662 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1663 (void)Idx;
1664 return;
1665 }
1666
1667 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1668 LLVM_DEBUG(dbgs() << ", straight through.\n");
1669 //
1670 // |-----------| Live through.
1671 // ------------- Straight through, same intv, no interference.
1672 //
1673 selectIntv(IntvOut);
1674 useIntv(Start, Stop);
1675 return;
1676 }
1677
1678 // We cannot legally insert splits after LSP.
1679 SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
1680 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
1681
1682 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1683 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1684 LLVM_DEBUG(dbgs() << ", switch avoiding interference.\n");
1685 //
1686 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
1687 // |-----------| Live through.
1688 // ------======= Switch intervals between interference.
1689 //
1690 selectIntv(IntvOut);
1691 SlotIndex Idx;
1692 if (LeaveBefore && LeaveBefore < LSP) {
1693 Idx = enterIntvBefore(LeaveBefore);
1694 useIntv(Idx, Stop);
1695 } else {
1697 }
1698 selectIntv(IntvIn);
1699 useIntv(Start, Idx);
1700 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1701 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1702 return;
1703 }
1704
1705 LLVM_DEBUG(dbgs() << ", create local intv for interference.\n");
1706 //
1707 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1708 // |-----------| Live through.
1709 // ==---------== Switch intervals before/after interference.
1710 //
1711 assert(LeaveBefore <= EnterAfter && "Missed case");
1712
1713 selectIntv(IntvOut);
1714 SlotIndex Idx = enterIntvAfter(EnterAfter);
1715 useIntv(Idx, Stop);
1716 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1717
1718 selectIntv(IntvIn);
1719 Idx = leaveIntvBefore(LeaveBefore);
1720 useIntv(Start, Idx);
1721 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1722}
1723
1725 unsigned IntvIn, SlotIndex LeaveBefore) {
1726 SlotIndex Start, Stop;
1727 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1728
1729 LLVM_DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';'
1730 << Stop << "), uses " << BI.FirstInstr << '-'
1731 << BI.LastInstr << ", reg-in " << IntvIn
1732 << ", leave before " << LeaveBefore
1733 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1734
1735 assert(IntvIn && "Must have register in");
1736 assert(BI.LiveIn && "Must be live-in");
1737 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1738
1739 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1740 LLVM_DEBUG(dbgs() << " before interference.\n");
1741 //
1742 // <<< Interference after kill.
1743 // |---o---x | Killed in block.
1744 // ========= Use IntvIn everywhere.
1745 //
1746 selectIntv(IntvIn);
1747 useIntv(Start, BI.LastInstr);
1748 return;
1749 }
1750
1751 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB);
1752
1753 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1754 //
1755 // <<< Possible interference after last use.
1756 // |---o---o---| Live-out on stack.
1757 // =========____ Leave IntvIn after last use.
1758 //
1759 // < Interference after last use.
1760 // |---o---o--o| Live-out on stack, late last use.
1761 // ============ Copy to stack after LSP, overlap IntvIn.
1762 // \_____ Stack interval is live-out.
1763 //
1764 if (BI.LastInstr < LSP) {
1765 LLVM_DEBUG(dbgs() << ", spill after last use before interference.\n");
1766 selectIntv(IntvIn);
1768 useIntv(Start, Idx);
1769 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1770 } else {
1771 LLVM_DEBUG(dbgs() << ", spill before last split point.\n");
1772 selectIntv(IntvIn);
1775 useIntv(Start, Idx);
1776 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1777 }
1778 return;
1779 }
1780
1781 // The interference is overlapping somewhere we wanted to use IntvIn. That
1782 // means we need to create a local interval that can be allocated a
1783 // different register.
1784 unsigned LocalIntv = openIntv();
1785 (void)LocalIntv;
1786 LLVM_DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1787
1788 if (!BI.LiveOut || BI.LastInstr < LSP) {
1789 //
1790 // <<<<<<< Interference overlapping uses.
1791 // |---o---o---| Live-out on stack.
1792 // =====----____ Leave IntvIn before interference, then spill.
1793 //
1795 SlotIndex From = enterIntvBefore(LeaveBefore);
1796 useIntv(From, To);
1797 selectIntv(IntvIn);
1798 useIntv(Start, From);
1799 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1800 return;
1801 }
1802
1803 // <<<<<<< Interference overlapping uses.
1804 // |---o---o--o| Live-out on stack, late last use.
1805 // =====------- Copy to stack before LSP, overlap LocalIntv.
1806 // \_____ Stack interval is live-out.
1807 //
1808 SlotIndex To = leaveIntvBefore(LSP);
1809 overlapIntv(To, BI.LastInstr);
1810 SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1811 useIntv(From, To);
1812 selectIntv(IntvIn);
1813 useIntv(Start, From);
1814 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1815}
1816
1818 unsigned IntvOut, SlotIndex EnterAfter) {
1819 SlotIndex Start, Stop;
1820 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1821
1822 LLVM_DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';'
1823 << Stop << "), uses " << BI.FirstInstr << '-'
1824 << BI.LastInstr << ", reg-out " << IntvOut
1825 << ", enter after " << EnterAfter
1826 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1827
1828 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB);
1829
1830 assert(IntvOut && "Must have register out");
1831 assert(BI.LiveOut && "Must be live-out");
1832 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1833
1834 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1835 LLVM_DEBUG(dbgs() << " after interference.\n");
1836 //
1837 // >>>> Interference before def.
1838 // | o---o---| Defined in block.
1839 // ========= Use IntvOut everywhere.
1840 //
1841 selectIntv(IntvOut);
1842 useIntv(BI.FirstInstr, Stop);
1843 return;
1844 }
1845
1846 if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1847 LLVM_DEBUG(dbgs() << ", reload after interference.\n");
1848 //
1849 // >>>> Interference before def.
1850 // |---o---o---| Live-through, stack-in.
1851 // ____========= Enter IntvOut before first use.
1852 //
1853 selectIntv(IntvOut);
1854 SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstInstr));
1855 useIntv(Idx, Stop);
1856 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1857 return;
1858 }
1859
1860 // The interference is overlapping somewhere we wanted to use IntvOut. That
1861 // means we need to create a local interval that can be allocated a
1862 // different register.
1863 LLVM_DEBUG(dbgs() << ", interference overlaps uses.\n");
1864 //
1865 // >>>>>>> Interference overlapping uses.
1866 // |---o---o---| Live-through, stack-in.
1867 // ____---====== Create local interval for interference range.
1868 //
1869 selectIntv(IntvOut);
1870 SlotIndex Idx = enterIntvAfter(EnterAfter);
1871 useIntv(Idx, Stop);
1872 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1873
1874 openIntv();
1875 SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstInstr));
1876 useIntv(From, Idx);
1877}
1878
1880 OS << "{" << printMBBReference(*MBB) << ", "
1881 << "uses " << FirstInstr << " to " << LastInstr << ", "
1882 << "1st def " << FirstDef << ", "
1883 << (LiveIn ? "live in" : "dead in") << ", "
1884 << (LiveOut ? "live out" : "dead out") << "}";
1885}
1886
1888 print(dbgs());
1889 dbgs() << "\n";
1890}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
aarch64 promote const
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator MBBI
This file defines the BumpPtrAllocator interface.
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:510
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define LLVM_DEBUG(X)
Definition: Debug.h:101
bool End
Definition: ELF_riscv.cpp:469
const HexagonInstrInfo * TII
Hexagon Hardware Loops
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
#define P(N)
Basic Register Allocator
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI Lower i1 Copies
This file contains some templates that are useful if you are working with the STL at all.
raw_pwrite_stream & OS
LiveInterval::SubRange & getSubRangeForMaskExact(LaneBitmask LM, LiveInterval &LI)
Definition: SplitKit.cpp:397
static bool hasTiedUseOf(MachineInstr &MI, unsigned Reg)
Definition: SplitKit.cpp:805
static bool removeDeadSegment(SlotIndex Def, LiveRange &LR)
Definition: SplitKit.cpp:1231
auto & getSubrangeImpl(LaneBitmask LM, T &LI)
Find a subrange corresponding to the exact lane mask LM in the live interval LI.
Definition: SplitKit.cpp:390
const LiveInterval::SubRange & getSubRangeForMask(LaneBitmask LM, const LiveInterval &LI)
Find a subrange corresponding to the lane mask LM, or a superset of it, in the live interval LI.
Definition: SplitKit.cpp:411
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:341
void clear()
clear - Removes all bits from the bitvector.
Definition: BitVector.h:335
BitVector & set()
Definition: BitVector.h:351
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
Definition: LiveInterval.h:998
A debug info location.
Definition: DebugLoc.h:33
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:202
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:220
Implements a dense probed hash-table based set.
Definition: DenseSet.h:271
Base class for the actual dominator tree node.
NodeT * getBlock() const
MachineBasicBlock::iterator getLastInsertPointIter(const LiveInterval &CurLI, MachineBasicBlock &MBB)
Returns the last insert point as an iterator for \pCurLI in \pMBB.
Definition: SplitKit.cpp:138
SlotIndex getLastInsertPoint(const LiveInterval &CurLI, const MachineBasicBlock &MBB)
Return the base index of the last valid insert point for \pCurLI in \pMBB.
Definition: SplitKit.h:67
InsertPointAnalysis(const LiveIntervals &lis, unsigned BBNum)
Definition: SplitKit.cpp:57
const_iterator begin() const
Definition: IntervalMap.h:1146
void insert(KeyT a, KeyT b, ValT y)
insert - Add a mapping of [a;b] to y, coalesce with adjacent intervals.
Definition: IntervalMap.h:1129
ValT lookup(KeyT x, ValT NotFound=ValT()) const
lookup - Return the mapped value at x or NotFound.
Definition: IntervalMap.h:1119
bool empty() const
empty - Return true when no intervals are mapped.
Definition: IntervalMap.h:1101
void clear()
clear - Remove all entries.
Definition: IntervalMap.h:1330
A live range for subregisters.
Definition: LiveInterval.h:693
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
Register reg() const
Definition: LiveInterval.h:717
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:803
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:775
void refineSubRanges(BumpPtrAllocator &Allocator, LaneBitmask LaneMask, std::function< void(LiveInterval::SubRange &)> Apply, const SlotIndexes &Indexes, const TargetRegisterInfo &TRI, unsigned ComposeSubRegIdx=0)
Refines the subranges to support LaneMask.
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndexes * getSlotIndexes() const
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
VNInfo::Allocator & getVNInfoAllocator()
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveInterval & getInterval(Register Reg)
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos.
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range.
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
void addLiveInBlock(LiveRange &LR, MachineDomTreeNode *DomNode, SlotIndex Kill=SlotIndex())
addLiveInBlock - Add a block with an unknown live-in value.
void reset(const MachineFunction *mf, SlotIndexes *SI, MachineDominatorTree *MDT, VNInfo::Allocator *VNIA)
reset - Prepare caches for a new set of non-overlapping live ranges.
void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, ArrayRef< SlotIndex > Undefs)
Extend the live range of LR to reach Use.
void calculateValues()
calculateValues - Calculate the value that will be live-in to each block added with addLiveInBlock.
void setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI)
setLiveOutValue - Indicate that VNI is live out from MBB.
bool empty() const
unsigned size() const
Register get(unsigned idx) const
LiveInterval & createEmptyInterval()
create - Create a new register with the same class and original slot as parent.
const LiveInterval & getParent() const
Register getReg() const
SlotIndex rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, const Remat &RM, const TargetRegisterInfo &, bool Late=false, unsigned SubIdx=0, MachineInstr *ReplaceIndexMI=nullptr)
rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an instruction into MBB before...
bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, bool cheapAsAMove)
canRematerializeAt - Determine if ParentVNI can be rematerialized at UseIdx.
bool didRematerialize(const VNInfo *ParentVNI) const
didRematerialize - Return true if ParentVNI was rematerialized anywhere.
bool anyRematerializable()
anyRematerializable - Return true if any parent values may be rematerializable.
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
Definition: LiveInterval.h:317
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
Definition: LiveInterval.h:408
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:401
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)
createDeadDef - Make sure the range has a value defined at Def.
iterator advanceTo(iterator I, SlotIndex Pos)
advanceTo - Advance the specified iterator to point to the Segment containing the specified position,...
Definition: LiveInterval.h:271
bool empty() const
Definition: LiveInterval.h:382
void RenumberValues()
RenumberValues - Renumber all values in order of appearance and remove unused values.
iterator end()
Definition: LiveInterval.h:216
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
Definition: LiveInterval.h:429
std::pair< VNInfo *, bool > extendInBlock(ArrayRef< SlotIndex > Undefs, SlotIndex StartIdx, SlotIndex Kill)
Attempt to extend a value defined after StartIdx to include Use.
unsigned getNumValNums() const
Definition: LiveInterval.h:313
iterator begin()
Definition: LiveInterval.h:215
Segments segments
Definition: LiveInterval.h:203
VNInfoList valnos
Definition: LiveInterval.h:204
VNInfo * getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:331
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:421
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
BlockT * getHeader() const
unsigned getLoopDepth() const
Return the nesting level of this loop.
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:47
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
iterator SkipPHIsLabelsAndDebug(iterator I, bool SkipPseudoOp=true)
Return the first instruction in MBB after I that is not a PHI, label or debug.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< succ_iterator > successors()
iterator_range< pred_iterator > predecessors()
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B.
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
void bundleWithPred()
Bundle this instruction with its predecessor.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:696
MachineOperand class - Representation of each machine instruction operand.
bool isEarlyClobber() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:68
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:180
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:246
static bool isEarlierInstr(SlotIndex A, SlotIndex B)
isEarlierInstr - Return true if A refers to an instruction earlier than B.
Definition: SlotIndexes.h:186
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
Definition: SlotIndexes.h:235
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
Definition: SlotIndexes.h:228
SlotIndex getNextSlot() const
Returns the next slot in the index list.
Definition: SlotIndexes.h:256
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:241
SlotIndexes pass.
Definition: SlotIndexes.h:301
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:522
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
Definition: SlotIndexes.h:501
const std::pair< SlotIndex, SlotIndex > & getMBBRange(unsigned Num) const
Return the (start,end) range of the given basic block number.
Definition: SlotIndexes.h:442
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:463
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:384
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:366
SmallPtrSetIterator - This implements a const_iterator for SmallPtrSet.
Definition: SmallPtrSet.h:269
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:451
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
void assign(size_type NumElts, ValueParamT Elt)
Definition: SmallVector.h:708
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:582
void resize(size_type N)
Definition: SmallVector.h:642
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
SplitAnalysis - Analyze a LiveInterval, looking for live range splitting opportunities.
Definition: SplitKit.h:96
SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis, const MachineLoopInfo &mli)
Definition: SplitKit.cpp:150
const MachineFunction & MF
Definition: SplitKit.h:98
MachineBasicBlock::iterator getLastSplitPointIter(MachineBasicBlock *BB)
Definition: SplitKit.h:237
bool isOriginalEndpoint(SlotIndex Idx) const
isOriginalEndpoint - Return true if the original live range was killed or (re-)defined at Idx.
Definition: SplitKit.cpp:323
unsigned countLiveBlocks(const LiveInterval *li) const
countLiveBlocks - Return the number of blocks where li is live.
Definition: SplitKit.cpp:299
SlotIndex getLastSplitPoint(unsigned Num)
Definition: SplitKit.h:229
const LiveIntervals & LIS
Definition: SplitKit.h:100
void analyze(const LiveInterval *li)
analyze - set CurLI to the specified interval, and analyze how it may be split.
Definition: SplitKit.cpp:337
void clear()
clear - clear all data structures so SplitAnalysis is ready to analyze a new interval.
Definition: SplitKit.cpp:155
const MachineLoopInfo & Loops
Definition: SplitKit.h:101
const TargetInstrInfo & TII
Definition: SplitKit.h:102
unsigned getNumLiveBlocks() const
getNumLiveBlocks - Return the number of blocks where CurLI is live.
Definition: SplitKit.h:208
const VirtRegMap & VRM
Definition: SplitKit.h:99
bool shouldSplitSingleBlock(const BlockInfo &BI, bool SingleInstrs) const
shouldSplitSingleBlock - Returns true if it would help to create a local live range for the instructi...
Definition: SplitKit.cpp:1575
void overlapIntv(SlotIndex Start, SlotIndex End)
overlapIntv - Indicate that all instructions in range should use the open interval if End does not ha...
Definition: SplitKit.cpp:811
unsigned openIntv()
Create a new virtual register and live interval.
Definition: SplitKit.cpp:635
SplitEditor(SplitAnalysis &SA, LiveIntervals &LIS, VirtRegMap &VRM, MachineDominatorTree &MDT, MachineBlockFrequencyInfo &MBFI, VirtRegAuxInfo &VRAI)
Create a new SplitEditor for editing the LiveInterval analyzed by SA.
Definition: SplitKit.cpp:348
void splitRegOutBlock(const SplitAnalysis::BlockInfo &BI, unsigned IntvOut, SlotIndex EnterAfter)
splitRegOutBlock - Split CurLI in the given block such that it enters the block on the stack (or isn'...
Definition: SplitKit.cpp:1817
SlotIndex enterIntvAfter(SlotIndex Idx)
enterIntvAfter - Enter the open interval after the instruction at Idx.
Definition: SplitKit.cpp:670
SlotIndex enterIntvBefore(SlotIndex Idx)
enterIntvBefore - Enter the open interval before the instruction at Idx.
Definition: SplitKit.cpp:653
void useIntv(const MachineBasicBlock &MBB)
useIntv - indicate that all instructions in MBB should use OpenLI.
Definition: SplitKit.cpp:725
SlotIndex leaveIntvAfter(SlotIndex Idx)
leaveIntvAfter - Leave the open interval after the instruction at Idx.
Definition: SplitKit.cpp:736
void reset(LiveRangeEdit &, ComplementSpillMode=SM_Partition)
reset - Prepare for a new split.
Definition: SplitKit.cpp:356
SlotIndex enterIntvAtEnd(MachineBasicBlock &MBB)
enterIntvAtEnd - Enter the open interval at the end of MBB.
Definition: SplitKit.cpp:688
SlotIndex leaveIntvAtTop(MachineBasicBlock &MBB)
leaveIntvAtTop - Leave the interval at the top of MBB.
Definition: SplitKit.cpp:786
SlotIndex leaveIntvBefore(SlotIndex Idx)
leaveIntvBefore - Leave the open interval before the instruction at Idx.
Definition: SplitKit.cpp:767
void finish(SmallVectorImpl< unsigned > *LRMap=nullptr)
finish - after all the new live ranges have been created, compute the remaining live range,...
Definition: SplitKit.cpp:1490
void splitRegInBlock(const SplitAnalysis::BlockInfo &BI, unsigned IntvIn, SlotIndex LeaveBefore)
splitRegInBlock - Split CurLI in the given block such that it enters the block in IntvIn and leaves i...
Definition: SplitKit.cpp:1724
void splitLiveThroughBlock(unsigned MBBNum, unsigned IntvIn, SlotIndex LeaveBefore, unsigned IntvOut, SlotIndex EnterAfter)
splitLiveThroughBlock - Split CurLI in the given block such that it enters the block in IntvIn and le...
Definition: SplitKit.cpp:1621
ComplementSpillMode
ComplementSpillMode - Select how the complement live range should be created.
Definition: SplitKit.h:275
@ SM_Partition
SM_Partition(Default) - Try to create the complement interval so it doesn't overlap any other interva...
Definition: SplitKit.h:280
@ SM_Speed
SM_Speed - Overlap intervals to minimize the expected execution frequency of the inserted copies.
Definition: SplitKit.h:292
@ SM_Size
SM_Size - Overlap intervals to minimize the number of inserted COPY instructions.
Definition: SplitKit.h:287
void selectIntv(unsigned Idx)
selectIntv - Select a previously opened interval index.
Definition: SplitKit.cpp:646
void splitSingleBlock(const SplitAnalysis::BlockInfo &BI)
splitSingleBlock - Split CurLI into a separate live interval around the uses in a single block.
Definition: SplitKit.cpp:1595
void dump() const
dump - print the current interval mapping to dbgs().
Definition: SplitKit.cpp:374
virtual unsigned getLiveRangeSplitOpcode(Register Reg, const MachineFunction &MF) const
Allows targets to use appropriate copy instruction while spilitting live range of a register in regis...
std::optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:81
unsigned id
The ID number of this value.
Definition: LiveInterval.h:58
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:78
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint.
void setIsSplitFromReg(Register virtReg, Register SReg)
records virtReg is a split live interval from SReg.
Definition: VirtRegMap.h:153
Register getOriginal(Register VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting.
Definition: VirtRegMap.h:169
MachineFunction & getMachineFunction() const
Definition: VirtRegMap.h:87
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
Definition: DenseSet.h:97
Iterator for intrusive lists based on ilist_node.
self_iterator getIterator()
Definition: ilist_node.h:82
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ Dead
Unused definition.
@ Define
Register definition.
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< DefNode * > Def
Definition: RDFGraph.h:384
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1685
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
Definition: STLExtras.h:2037
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:666
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1734
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:429
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1741
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
unsigned getInternalReadRegState(bool B)
unsigned getUndefRegState(bool B)
void array_pod_sort(IteratorTy Start, IteratorTy End)
array_pod_sort - This sorts an array with the specified start and end extent.
Definition: STLExtras.h:1612
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
#define N
Description of the encoding of one expression Op.
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:82
constexpr bool none() const
Definition: LaneBitmask.h:52
constexpr bool all() const
Definition: LaneBitmask.h:54
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:81
Remat - Information needed to rematerialize at a specific location.
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
Additional information about basic blocks where the current variable is live.
Definition: SplitKit.h:121
SlotIndex FirstDef
First non-phi valno->def, or SlotIndex().
Definition: SplitKit.h:125
bool LiveOut
Current reg is live out.
Definition: SplitKit.h:127
bool LiveIn
Current reg is live in.
Definition: SplitKit.h:126
bool isOneInstr() const
isOneInstr - Returns true when this BlockInfo describes a single instruction.
Definition: SplitKit.h:131
MachineBasicBlock * MBB
Definition: SplitKit.h:122
void print(raw_ostream &OS) const
Definition: SplitKit.cpp:1879
SlotIndex LastInstr
Last instr accessing current reg.
Definition: SplitKit.h:124
SlotIndex FirstInstr
First instr accessing current reg.
Definition: SplitKit.h:123