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NVPTXPeephole.cpp
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1 //===-- NVPTXPeephole.cpp - NVPTX Peephole Optimiztions -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // In NVPTX, NVPTXFrameLowering will emit following instruction at the beginning
10 // of a MachineFunction.
11 //
12 // mov %SPL, %depot
13 // cvta.local %SP, %SPL
14 //
15 // Because Frame Index is a generic address and alloca can only return generic
16 // pointer, without this pass the instructions producing alloca'ed address will
17 // be based on %SP. NVPTXLowerAlloca tends to help replace store and load on
18 // this address with their .local versions, but this may introduce a lot of
19 // cvta.to.local instructions. Performance can be improved if we avoid casting
20 // address back and forth and directly calculate local address based on %SPL.
21 // This peephole pass optimizes these cases, for example
22 //
23 // It will transform the following pattern
24 // %0 = LEA_ADDRi64 %VRFrame, 4
25 // %1 = cvta_to_local_yes_64 %0
26 //
27 // into
28 // %1 = LEA_ADDRi64 %VRFrameLocal, 4
29 //
30 // %VRFrameLocal is the virtual register name of %SPL
31 //
32 //===----------------------------------------------------------------------===//
33 
34 #include "NVPTX.h"
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "nvptx-peephole"
44 
45 namespace llvm {
47 }
48 
49 namespace {
50 struct NVPTXPeephole : public MachineFunctionPass {
51  public:
52  static char ID;
53  NVPTXPeephole() : MachineFunctionPass(ID) {
55  }
56 
57  bool runOnMachineFunction(MachineFunction &MF) override;
58 
59  StringRef getPassName() const override {
60  return "NVPTX optimize redundant cvta.to.local instruction";
61  }
62 
63  void getAnalysisUsage(AnalysisUsage &AU) const override {
65  }
66 };
67 }
68 
69 char NVPTXPeephole::ID = 0;
70 
71 INITIALIZE_PASS(NVPTXPeephole, "nvptx-peephole", "NVPTX Peephole", false, false)
72 
74  auto &MBB = *Root.getParent();
75  auto &MF = *MBB.getParent();
76  // Check current instruction is cvta.to.local
77  if (Root.getOpcode() != NVPTX::cvta_to_local_yes_64 &&
78  Root.getOpcode() != NVPTX::cvta_to_local_yes)
79  return false;
80 
81  auto &Op = Root.getOperand(1);
82  const auto &MRI = MF.getRegInfo();
83  MachineInstr *GenericAddrDef = nullptr;
84  if (Op.isReg() && Register::isVirtualRegister(Op.getReg())) {
85  GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg());
86  }
87 
88  // Check the register operand is uniquely defined by LEA_ADDRi instruction
89  if (!GenericAddrDef || GenericAddrDef->getParent() != &MBB ||
90  (GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi64 &&
91  GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi)) {
92  return false;
93  }
94 
95  // Check the LEA_ADDRi operand is Frame index
96  auto &BaseAddrOp = GenericAddrDef->getOperand(1);
97  if (BaseAddrOp.isReg() && BaseAddrOp.getReg() == NVPTX::VRFrame) {
98  return true;
99  }
100 
101  return false;
102 }
103 
104 static void CombineCVTAToLocal(MachineInstr &Root) {
105  auto &MBB = *Root.getParent();
106  auto &MF = *MBB.getParent();
107  const auto &MRI = MF.getRegInfo();
108  const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
109  auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
110 
111  MachineInstrBuilder MIB =
112  BuildMI(MF, Root.getDebugLoc(), TII->get(Prev.getOpcode()),
113  Root.getOperand(0).getReg())
114  .addReg(NVPTX::VRFrameLocal)
115  .add(Prev.getOperand(2));
116 
118 
119  // Check if MRI has only one non dbg use, which is Root
120  if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) {
121  Prev.eraseFromParentAndMarkDBGValuesForRemoval();
122  }
123  Root.eraseFromParentAndMarkDBGValuesForRemoval();
124 }
125 
126 bool NVPTXPeephole::runOnMachineFunction(MachineFunction &MF) {
127  if (skipFunction(MF.getFunction()))
128  return false;
129 
130  bool Changed = false;
131  // Loop over all of the basic blocks.
132  for (auto &MBB : MF) {
133  // Traverse the basic block.
134  auto BlockIter = MBB.begin();
135 
136  while (BlockIter != MBB.end()) {
137  auto &MI = *BlockIter++;
140  Changed = true;
141  }
142  } // Instruction
143  } // Basic Block
144 
145  // Remove unnecessary %VRFrame = cvta.local %VRFrameLocal
146  const auto &MRI = MF.getRegInfo();
147  if (MRI.use_empty(NVPTX::VRFrame)) {
148  if (auto MI = MRI.getUniqueVRegDef(NVPTX::VRFrame)) {
149  MI->eraseFromParentAndMarkDBGValuesForRemoval();
150  }
151  }
152 
153  return Changed;
154 }
155 
156 MachineFunctionPass *llvm::createNVPTXPeephole() { return new NVPTXPeephole(); }
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:23
CombineCVTAToLocal
static void CombineCVTAToLocal(MachineInstr &Root)
Definition: NVPTXPeephole.cpp:104
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
llvm::initializeNVPTXPeepholePass
void initializeNVPTXPeepholePass(PassRegistry &)
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:411
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
TargetInstrInfo.h
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
NVPTX.h
MachineRegisterInfo.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:487
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::MachineRegisterInfo::use_empty
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:506
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:417
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:63
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
MachineFunctionPass.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:98
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:477
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:419
isCVTAToLocalCombinationCandidate
static bool isCVTAToLocalCombinationCandidate(MachineInstr &Root)
Definition: NVPTXPeephole.cpp:73
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:285
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:302
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1335
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:329
llvm::createNVPTXPeephole
MachineFunctionPass * createNVPTXPeephole()
Definition: NVPTXPeephole.cpp:156
llvm::MachineInstrBundleIterator< MachineInstr >
TargetRegisterInfo.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37