LLVM 17.0.0git
NVPTXRegisterInfo.cpp
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1//===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the NVPTX implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTXRegisterInfo.h"
14#include "NVPTX.h"
15#include "NVPTXSubtarget.h"
16#include "NVPTXTargetMachine.h"
17#include "llvm/ADT/BitVector.h"
23
24using namespace llvm;
25
26#define DEBUG_TYPE "nvptx-reg-info"
27
28namespace llvm {
30 if (RC == &NVPTX::Float32RegsRegClass)
31 return ".f32";
32 if (RC == &NVPTX::Float16RegsRegClass)
33 // Ideally fp16 registers should be .f16, but this syntax is only
34 // supported on sm_53+. On the other hand, .b16 registers are
35 // accepted for all supported fp16 instructions on all GPU
36 // variants, so we can use them instead.
37 return ".b16";
38 if (RC == &NVPTX::Float16x2RegsRegClass)
39 return ".b32";
40 if (RC == &NVPTX::Float64RegsRegClass)
41 return ".f64";
42 if (RC == &NVPTX::Int64RegsRegClass)
43 // We use untyped (.b) integer registers here as NVCC does.
44 // Correctness of generated code does not depend on register type,
45 // but using .s/.u registers runs into ptxas bug that prevents
46 // assembly of otherwise valid PTX into SASS. Despite PTX ISA
47 // specifying only argument size for fp16 instructions, ptxas does
48 // not allow using .s16 or .u16 arguments for .fp16
49 // instructions. At the same time it allows using .s32/.u32
50 // arguments for .fp16v2 instructions:
51 //
52 // .reg .b16 rb16
53 // .reg .s16 rs16
54 // add.f16 rb16,rb16,rb16; // OK
55 // add.f16 rs16,rs16,rs16; // Arguments mismatch for instruction 'add'
56 // but:
57 // .reg .b32 rb32
58 // .reg .s32 rs32
59 // add.f16v2 rb32,rb32,rb32; // OK
60 // add.f16v2 rs32,rs32,rs32; // OK
61 return ".b64";
62 if (RC == &NVPTX::Int32RegsRegClass)
63 return ".b32";
64 if (RC == &NVPTX::Int16RegsRegClass)
65 return ".b16";
66 if (RC == &NVPTX::Int1RegsRegClass)
67 return ".pred";
68 if (RC == &NVPTX::SpecialRegsRegClass)
69 return "!Special!";
70 return "INTERNAL";
71}
72
74 if (RC == &NVPTX::Float32RegsRegClass)
75 return "%f";
76 if (RC == &NVPTX::Float16RegsRegClass)
77 return "%h";
78 if (RC == &NVPTX::Float16x2RegsRegClass)
79 return "%hh";
80 if (RC == &NVPTX::Float64RegsRegClass)
81 return "%fd";
82 if (RC == &NVPTX::Int64RegsRegClass)
83 return "%rd";
84 if (RC == &NVPTX::Int32RegsRegClass)
85 return "%r";
86 if (RC == &NVPTX::Int16RegsRegClass)
87 return "%rs";
88 if (RC == &NVPTX::Int1RegsRegClass)
89 return "%p";
90 if (RC == &NVPTX::SpecialRegsRegClass)
91 return "!Special!";
92 return "INTERNAL";
93}
94}
95
97 : NVPTXGenRegisterInfo(0), StrPool(StrAlloc) {}
98
99#define GET_REGINFO_TARGET_DESC
100#include "NVPTXGenRegisterInfo.inc"
101
102/// NVPTX Callee Saved Registers
103const MCPhysReg *
105 static const MCPhysReg CalleeSavedRegs[] = { 0 };
106 return CalleeSavedRegs;
107}
108
110 BitVector Reserved(getNumRegs());
111 for (unsigned Reg = NVPTX::ENVREG0; Reg <= NVPTX::ENVREG31; ++Reg) {
112 markSuperRegs(Reserved, Reg);
113 }
114 markSuperRegs(Reserved, NVPTX::VRFrame32);
115 markSuperRegs(Reserved, NVPTX::VRFrameLocal32);
116 markSuperRegs(Reserved, NVPTX::VRFrame64);
117 markSuperRegs(Reserved, NVPTX::VRFrameLocal64);
118 markSuperRegs(Reserved, NVPTX::VRDepot);
119 return Reserved;
120}
121
123 int SPAdj, unsigned FIOperandNum,
124 RegScavenger *RS) const {
125 assert(SPAdj == 0 && "Unexpected");
126
127 MachineInstr &MI = *II;
128 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
129
130 MachineFunction &MF = *MI.getParent()->getParent();
131 int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) +
132 MI.getOperand(FIOperandNum + 1).getImm();
133
134 // Using I0 as the frame pointer
135 MI.getOperand(FIOperandNum).ChangeToRegister(getFrameRegister(MF), false);
136 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
137 return false;
138}
139
141 const NVPTXTargetMachine &TM =
142 static_cast<const NVPTXTargetMachine &>(MF.getTarget());
143 return TM.is64Bit() ? NVPTX::VRFrame64 : NVPTX::VRFrame32;
144}
145
148 const NVPTXTargetMachine &TM =
149 static_cast<const NVPTXTargetMachine &>(MF.getTarget());
150 return TM.is64Bit() ? NVPTX::VRFrameLocal64 : NVPTX::VRFrameLocal32;
151}
This file implements the BitVector class.
IRTranslator LLVM IR MI
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Representation of each machine instruction.
Definition: MachineInstr.h:68
Register getFrameLocalRegister(const MachineFunction &MF) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
NVPTX Callee Saved Registers.
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
Register getFrameRegister(const MachineFunction &MF) const override
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
std::string getNVPTXRegClassName(TargetRegisterClass const *RC)
std::string getNVPTXRegClassStr(TargetRegisterClass const *RC)