26 #define DEBUG_TYPE "nvptx-reg-info"
30 if (RC == &NVPTX::Float32RegsRegClass)
32 if (RC == &NVPTX::Float16RegsRegClass)
38 if (RC == &NVPTX::Float16x2RegsRegClass)
40 if (RC == &NVPTX::Float64RegsRegClass)
42 if (RC == &NVPTX::Int64RegsRegClass)
62 if (RC == &NVPTX::Int32RegsRegClass)
64 if (RC == &NVPTX::Int16RegsRegClass)
66 if (RC == &NVPTX::Int1RegsRegClass)
68 if (RC == &NVPTX::SpecialRegsRegClass)
74 if (RC == &NVPTX::Float32RegsRegClass)
76 if (RC == &NVPTX::Float16RegsRegClass)
78 if (RC == &NVPTX::Float16x2RegsRegClass)
80 if (RC == &NVPTX::Float64RegsRegClass)
82 if (RC == &NVPTX::Int64RegsRegClass)
84 if (RC == &NVPTX::Int32RegsRegClass)
86 if (RC == &NVPTX::Int16RegsRegClass)
88 if (RC == &NVPTX::Int1RegsRegClass)
90 if (RC == &NVPTX::SpecialRegsRegClass)
98 #define GET_REGINFO_TARGET_DESC
99 #include "NVPTXGenRegisterInfo.inc"
104 static const MCPhysReg CalleeSavedRegs[] = { 0 };
105 return CalleeSavedRegs;
110 for (
unsigned Reg = NVPTX::ENVREG0;
Reg <= NVPTX::ENVREG31; ++
Reg) {
111 markSuperRegs(Reserved,
Reg);
113 markSuperRegs(Reserved, NVPTX::VRFrame32);
114 markSuperRegs(Reserved, NVPTX::VRFrameLocal32);
115 markSuperRegs(Reserved, NVPTX::VRFrame64);
116 markSuperRegs(Reserved, NVPTX::VRFrameLocal64);
117 markSuperRegs(Reserved, NVPTX::VRDepot);
122 int SPAdj,
unsigned FIOperandNum,
124 assert(SPAdj == 0 &&
"Unexpected");
127 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
131 MI.getOperand(FIOperandNum + 1).getImm();
135 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
141 return TM.is64Bit() ? NVPTX::VRFrame64 : NVPTX::VRFrame32;
148 return TM.is64Bit() ? NVPTX::VRFrameLocal64 : NVPTX::VRFrameLocal32;