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GCNSchedStrategy.h
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1 //===-- GCNSchedStrategy.h - GCN Scheduler Strategy -*- C++ -*-------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_GCNSCHEDSTRATEGY_H
14 #define LLVM_LIB_TARGET_AMDGPU_GCNSCHEDSTRATEGY_H
15 
16 #include "GCNRegPressure.h"
17 #include "llvm/ADT/MapVector.h"
19 
20 namespace llvm {
21 
22 class SIMachineFunctionInfo;
23 class SIRegisterInfo;
24 class GCNSubtarget;
25 
26 /// This is a minimal scheduler strategy. The main difference between this
27 /// and the GenericScheduler is that GCNSchedStrategy uses different
28 /// heuristics to determine excess/critical pressure sets. Its goal is to
29 /// maximize kernel occupancy (i.e. maximum number of waves per simd).
31  friend class GCNScheduleDAGMILive;
32 
33  SUnit *pickNodeBidirectional(bool &IsTopNode);
34 
35  void pickNodeFromQueue(SchedBoundary &Zone, const CandPolicy &ZonePolicy,
36  const RegPressureTracker &RPTracker,
37  SchedCandidate &Cand);
38 
39  void initCandidate(SchedCandidate &Cand, SUnit *SU,
40  bool AtTop, const RegPressureTracker &RPTracker,
41  const SIRegisterInfo *SRI,
42  unsigned SGPRPressure, unsigned VGPRPressure);
43 
44  std::vector<unsigned> Pressure;
45  std::vector<unsigned> MaxPressure;
46 
47  unsigned SGPRExcessLimit;
48  unsigned VGPRExcessLimit;
49  unsigned SGPRCriticalLimit;
50  unsigned VGPRCriticalLimit;
51 
52  unsigned TargetOccupancy;
53 
54  // schedule() have seen a clustered memory operation. Set it to false
55  // before a region scheduling to know if the region had such clusters.
56  bool HasClusteredNodes;
57 
58  // schedule() have seen an excess register pressure and had to track
59  // register pressure for actual scheduling heuristics.
60  bool HasExcessPressure;
61 
62  MachineFunction *MF;
63 
64 public:
66 
67  SUnit *pickNode(bool &IsTopNode) override;
68 
69  void initialize(ScheduleDAGMI *DAG) override;
70 
71  void setTargetOccupancy(unsigned Occ) { TargetOccupancy = Occ; }
72 };
73 
75 
76  enum : unsigned {
77  Collect,
78  InitialSchedule,
79  UnclusteredReschedule,
80  ClusteredLowOccupancyReschedule,
81  PreRARematerialize,
82  LastStage = PreRARematerialize
83  };
84 
85  const GCNSubtarget &ST;
86 
88 
89  // Occupancy target at the beginning of function scheduling cycle.
90  unsigned StartingOccupancy;
91 
92  // Minimal real occupancy recorder for the function.
93  unsigned MinOccupancy;
94 
95  // Scheduling stage number.
96  unsigned Stage;
97 
98  // Current region index.
99  size_t RegionIdx;
100 
101  // Vector of regions recorder for later rescheduling
103  MachineBasicBlock::iterator>, 32> Regions;
104 
105  // Records if a region is not yet scheduled, or schedule has been reverted,
106  // or we generally desire to reschedule it.
107  BitVector RescheduleRegions;
108 
109  // Record regions which use clustered loads/stores.
110  BitVector RegionsWithClusters;
111 
112  // Record regions with high register pressure.
113  BitVector RegionsWithHighRP;
114 
115  // Regions that has the same occupancy as the latest MinOccupancy
116  BitVector RegionsWithMinOcc;
117 
118  // Region live-in cache.
120 
121  // Region pressure cache.
123 
124  // Each region at MinOccupancy will have their own list of trivially
125  // rematerializable instructions we can remat to reduce RP. The list maps an
126  // instruction to the position we should remat before, usually the MI using
127  // the rematerializable instruction.
129  RematerializableInsts;
130 
131  // Map a trivially remateriazable def to a list of regions at MinOccupancy
132  // that has the defined reg as a live-in.
133  DenseMap<MachineInstr *, SmallVector<unsigned, 4>> RematDefToLiveInRegions;
134 
135  // Temporary basic block live-in cache.
137 
140 
141  // Collect all trivially rematerializable VGPR instructions with a single def
142  // and single use outside the defining block into RematerializableInsts.
143  void collectRematerializableInstructions();
144 
145  bool isTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA);
146 
147  // TODO: Should also attempt to reduce RP of SGPRs and AGPRs
148  // Attempt to reduce RP of VGPR by sinking trivially rematerializable
149  // instructions. Returns true if we were able to sink instruction(s).
150  bool sinkTriviallyRematInsts(const GCNSubtarget &ST,
151  const TargetInstrInfo *TII);
152 
153  // Return current region pressure.
154  GCNRegPressure getRealRegPressure() const;
155 
156  // Compute and cache live-ins and pressure for all regions in block.
157  void computeBlockPressure(const MachineBasicBlock *MBB);
158 
159  // Update region boundaries when removing MI or inserting NewMI before MI.
160  void updateRegionBoundaries(
162  MachineBasicBlock::iterator>> &RegionBoundaries,
164  bool Removing = false);
165 
166 public:
168  std::unique_ptr<MachineSchedStrategy> S);
169 
170  void schedule() override;
171 
172  void finalizeSchedule() override;
173 };
174 
175 } // End namespace llvm
176 
177 #endif // LLVM_LIB_TARGET_AMDGPU_GCNSCHEDSTRATEGY_H
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::GCNRegPressure
Definition: GCNRegPressure.h:30
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
MapVector.h
llvm::RegPressureTracker
Track the current register pressure at some position in the instruction stream, and remember the high...
Definition: RegisterPressure.h:357
llvm::GCNScheduleDAGMILive
Definition: GCNSchedStrategy.h:74
llvm::MapVector
This class implements a map that also provides access to all stored values in a deterministic order.
Definition: MapVector.h:37
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::GCNScheduleDAGMILive::finalizeSchedule
void finalizeSchedule() override
Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
Definition: GCNSchedStrategy.cpp:590
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::AAResults
Definition: AliasAnalysis.h:511
llvm::GCNMaxOccupancySchedStrategy
This is a minimal scheduler strategy.
Definition: GCNSchedStrategy.h:30
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::GenericSchedulerBase::CandPolicy
Policy for scheduling the next instruction in the candidate's zone.
Definition: MachineScheduler.h:823
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::BitVector
Definition: BitVector.h:75
llvm::GCNMaxOccupancySchedStrategy::setTargetOccupancy
void setTargetOccupancy(unsigned Occ)
Definition: GCNSchedStrategy.h:71
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::GenericSchedulerBase::SchedCandidate
Store the state used by GenericScheduler heuristics, required for the lifetime of one invocation of p...
Definition: MachineScheduler.h:861
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::DenseMap
Definition: DenseMap.h:716
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:125
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:242
llvm::GenericScheduler::DAG
ScheduleDAGMILive * DAG
Definition: MachineScheduler.h:997
llvm::GCNScheduleDAGMILive::schedule
void schedule() override
Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.
Definition: GCNSchedStrategy.cpp:316
llvm::GCNMaxOccupancySchedStrategy::pickNode
SUnit * pickNode(bool &IsTopNode) override
Pick the best node to balance the schedule. Implements MachineSchedStrategy.
Definition: GCNSchedStrategy.cpp:253
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::GCNMaxOccupancySchedStrategy::GCNMaxOccupancySchedStrategy
GCNMaxOccupancySchedStrategy(const MachineSchedContext *C)
Definition: GCNSchedStrategy.cpp:22
llvm::GCNMaxOccupancySchedStrategy::initialize
void initialize(ScheduleDAGMI *DAG) override
Initialize the strategy after building the DAG for a new region.
Definition: GCNSchedStrategy.cpp:27
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::ScheduleDAG::TII
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
GCNRegPressure.h
llvm::SchedBoundary
Each Scheduling boundary is associated with ready queues.
Definition: MachineScheduler.h:609
AA
MachineScheduler.h
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:348
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:390
llvm::GenericScheduler
GenericScheduler shrinks the unscheduled zone using heuristics to balance the schedule.
Definition: MachineScheduler.h:952
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::GCNScheduleDAGMILive::GCNScheduleDAGMILive
GCNScheduleDAGMILive(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
Definition: GCNSchedStrategy.cpp:305