llvm::PreRARematStage Class Reference

Attempts to reduce function spilling or, if there is no spilling, to increase function occupancy by one with respect to register usage by sinking rematerializable instructions to their use. More...

#include "Target/AMDGPU/GCNSchedStrategy.h"

Inheritance diagram for llvm::PreRARematStage:

Public Member Functions
bool	initGCNSchedStage () override
bool	initGCNRegion () override
bool	shouldRevertScheduling (unsigned WavesAfter) override
	PreRARematStage (GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Public Member Functions inherited from llvm::GCNSchedStage
void	setupNewBlock ()
void	finalizeGCNRegion ()
void	checkScheduling ()
ScheduleMetrics	getScheduleMetrics (const std::vector< SUnit > &InputSchedule)
ScheduleMetrics	getScheduleMetrics (const GCNScheduleDAGMILive &DAG)
unsigned	computeSUnitReadyCycle (const SUnit &SU, unsigned CurrCycle, DenseMap< unsigned, unsigned > &ReadyCycles, const TargetSchedModel &SM)
bool	isRegionWithExcessRP () const
unsigned	getRegionIdx ()
bool	mayCauseSpilling (unsigned WavesAfter)
void	revertScheduling ()
void	advanceRegion ()
virtual	~GCNSchedStage ()=default

Additional Inherited Members
Protected Member Functions inherited from llvm::GCNSchedStage
	GCNSchedStage (GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Protected Attributes inherited from llvm::GCNSchedStage
GCNScheduleDAGMILive &	DAG
GCNSchedStrategy &	S
MachineFunction &	MF
SIMachineFunctionInfo &	MFI
const GCNSubtarget &	ST
const GCNSchedStageID	StageID
MachineBasicBlock *	CurrentMBB = nullptr
unsigned	RegionIdx = 0
std::vector< MachineInstr * >	Unsched
GCNRegPressure	PressureBefore
GCNRegPressure	PressureAfter
std::vector< std::unique_ptr< ScheduleDAGMutation > >	SavedMutations

Detailed Description

Attempts to reduce function spilling or, if there is no spilling, to increase function occupancy by one with respect to register usage by sinking rematerializable instructions to their use.

When the stage estimates that reducing spilling or increasing occupancy is possible, it tries to rematerialize as few registers as possible to reduce potential negative effects on function latency.

The stage only supports rematerializing registers that meet all of the following constraints.

1. The register is virtual and has a single defining instruction.
2. The single defining instruction is either deemed rematerializable by the target-independent logic, or if not, has no non-constant and non-ignorable physical register use. 3 The register has no virtual register use whose live range would be extended by the rematerialization.
3. The register has a single non-debug user in a different region from its defining region.
4. The register is not used by or using another register that is going to be rematerialized.

Definition at line 468 of file GCNSchedStrategy.h.

Constructor & Destructor Documentation

PreRARematStage()

llvm::PreRARematStage::PreRARematStage ( GCNSchedStageID StageID, GCNScheduleDAGMILive & DAG )

inline

Definition at line 678 of file GCNSchedStrategy.h.

References llvm::GCNSchedStage::DAG, llvm::GCNSchedStage::GCNSchedStage(), llvm::size(), and llvm::GCNSchedStage::StageID.

Member Function Documentation

initGCNRegion()

bool PreRARematStage::initGCNRegion ( )

overridevirtual

Reimplemented from llvm::GCNSchedStage.

Definition at line 1649 of file GCNSchedStrategy.cpp.

References llvm::GCNSchedStage::initGCNRegion(), and llvm::GCNSchedStage::RegionIdx.

initGCNSchedStage()

bool PreRARematStage::initGCNSchedStage ( )

overridevirtual

Reimplemented from llvm::GCNSchedStage.

Definition at line 1294 of file GCNSchedStrategy.cpp.

References assert(), llvm::GCNSchedStage::DAG, llvm::dbgs(), llvm::SmallVectorImpl< T >::emplace_back(), llvm::MachineBasicBlock::end(), llvm::enumerate(), llvm::RegionBase< Tr >::getParent(), I, llvm::GCNSchedStage::initGCNSchedStage(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), LLVM_DEBUG, llvm::GCNSchedStage::MF, llvm::GCNSchedStage::MFI, MI, llvm::PreRARematStage::ScoredRemat::FreqInfo::Regions, REMAT_DEBUG, REMAT_PREFIX, llvm::BitVector::reset(), llvm::reverse(), llvm::GCNSchedStage::S, llvm::BitVector::size(), llvm::sort(), and llvm::GCNSchedStage::ST.

shouldRevertScheduling()

bool PreRARematStage::shouldRevertScheduling ( unsigned WavesAfter )

overridevirtual

Reimplemented from llvm::GCNSchedStage.

Definition at line 1954 of file GCNSchedStrategy.cpp.

References llvm::GCNSchedStage::mayCauseSpilling(), and llvm::GCNSchedStage::shouldRevertScheduling().

Referenced by llvm::GCNSchedStage::checkScheduling().

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The documentation for this class was generated from the following files:

• lib/Target/AMDGPU/GCNSchedStrategy.h
• lib/Target/AMDGPU/GCNSchedStrategy.cpp