LLVM 19.0.0git
SPIRVModuleAnalysis.h
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1//===- SPIRVModuleAnalysis.h - analysis of global instrs & regs -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// The analysis collects instructions that should be output at the module level
10// and performs the global register numbering.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVMODULEANALYSIS_H
15#define LLVM_LIB_TARGET_SPIRV_SPIRVMODULEANALYSIS_H
16
18#include "SPIRVGlobalRegistry.h"
19#include "SPIRVUtils.h"
20#include "llvm/ADT/DenseMap.h"
21#include "llvm/ADT/SmallSet.h"
23#include "llvm/ADT/StringMap.h"
24
25namespace llvm {
26class SPIRVSubtarget;
27class MachineFunction;
28class MachineModuleInfo;
29
30namespace SPIRV {
31// The enum contains logical module sections for the instruction collection.
33 // MB_Capabilities, MB_Extensions, MB_ExtInstImports, MB_MemoryModel,
34 MB_EntryPoints, // All OpEntryPoint instructions (if any).
35 // MB_ExecutionModes, MB_DebugSourceAndStrings,
36 MB_DebugNames, // All OpName and OpMemberName intrs.
37 MB_DebugModuleProcessed, // All OpModuleProcessed instructions.
38 MB_Annotations, // OpDecorate, OpMemberDecorate etc.
39 MB_TypeConstVars, // OpTypeXXX, OpConstantXXX, and global OpVariables.
40 MB_ExtFuncDecls, // OpFunction etc. to declare for external funcs.
41 NUM_MODULE_SECTIONS // Total number of sections requiring basic blocks.
42};
43
45 const bool IsSatisfiable;
46 const std::optional<Capability::Capability> Cap;
48 const unsigned MinVer; // 0 if no min version is required.
49 const unsigned MaxVer; // 0 if no max version is required.
50
52 std::optional<Capability::Capability> Cap = {},
53 ExtensionList Exts = {}, unsigned MinVer = 0,
54 unsigned MaxVer = 0)
56 MaxVer(MaxVer) {}
57 Requirements(Capability::Capability Cap) : Requirements(true, {Cap}) {}
58};
59
61private:
62 CapabilityList MinimalCaps;
63
64 // AllCaps and AvailableCaps are related but different. AllCaps is a subset of
65 // AvailableCaps. AvailableCaps is the complete set of capabilities that are
66 // available to the current target. AllCaps is the set of capabilities that
67 // are required by the current module.
69 DenseSet<unsigned> AvailableCaps;
70
72 unsigned MinVersion; // 0 if no min version is defined.
73 unsigned MaxVersion; // 0 if no max version is defined.
74 // Add capabilities to AllCaps, recursing through their implicitly declared
75 // capabilities too.
76 void recursiveAddCapabilities(const CapabilityList &ToPrune);
77
78 void initAvailableCapabilitiesForOpenCL(const SPIRVSubtarget &ST);
79 void initAvailableCapabilitiesForVulkan(const SPIRVSubtarget &ST);
80
81public:
82 RequirementHandler() : MinVersion(0), MaxVersion(0) {}
83 void clear() {
84 MinimalCaps.clear();
85 AllCaps.clear();
86 AvailableCaps.clear();
87 AllExtensions.clear();
88 MinVersion = 0;
89 MaxVersion = 0;
90 }
91 unsigned getMinVersion() const { return MinVersion; }
92 unsigned getMaxVersion() const { return MaxVersion; }
93 const CapabilityList &getMinimalCapabilities() const { return MinimalCaps; }
95 return AllExtensions;
96 }
97 // Add a list of capabilities, ensuring AllCaps captures all the implicitly
98 // declared capabilities, and MinimalCaps has the minimal set of required
99 // capabilities (so all implicitly declared ones are removed).
100 void addCapabilities(const CapabilityList &ToAdd);
101 void addCapability(Capability::Capability ToAdd) { addCapabilities({ToAdd}); }
102 void addExtensions(const ExtensionList &ToAdd) {
103 AllExtensions.insert(ToAdd.begin(), ToAdd.end());
104 }
105 void addExtension(Extension::Extension ToAdd) { AllExtensions.insert(ToAdd); }
106 // Add the given requirements to the lists. If constraints conflict, or these
107 // requirements cannot be satisfied, then abort the compilation.
108 void addRequirements(const Requirements &Req);
109 // Get requirement and add it to the list.
110 void getAndAddRequirements(SPIRV::OperandCategory::OperandCategory Category,
111 uint32_t i, const SPIRVSubtarget &ST);
112 // Check if all the requirements can be satisfied for the given subtarget, and
113 // if not abort compilation.
114 void checkSatisfiable(const SPIRVSubtarget &ST) const;
116 // Add the given capabilities to available and all their implicitly defined
117 // capabilities too.
118 void addAvailableCaps(const CapabilityList &ToAdd);
119 bool isCapabilityAvailable(Capability::Capability Cap) const {
120 return AvailableCaps.contains(Cap);
121 }
122
123 // Remove capability ToRemove, but only if IfPresent is present.
124 void removeCapabilityIf(const Capability::Capability ToRemove,
125 const Capability::Capability IfPresent);
126};
127
129// Maps a local register to the corresponding global alias.
130using LocalToGlobalRegTable = std::map<Register, Register>;
132 std::map<const MachineFunction *, LocalToGlobalRegTable>;
133
134// The struct contains results of the module analysis and methods
135// to access them.
138 MemoryModel::MemoryModel Mem;
139 AddressingModel::AddressingModel Addr;
140 SourceLanguage::SourceLanguage SrcLang;
143 // Maps ExtInstSet to corresponding ID register.
145 // Contains the list of all global OpVariables in the module.
147 // Maps functions to corresponding function ID registers.
149 // The set contains machine instructions which are necessary
150 // for correct MIR but will not be emitted in function bodies.
152 // The table contains global aliases of local registers for each machine
153 // function. The aliases are used to substitute local registers during
154 // code emission.
156 // The counter holds the maximum ID we have in the module.
157 unsigned MaxID;
158 // The array contains lists of MIs for each module section.
160 // The table maps MBB number to SPIR-V unique ID register.
162
164 assert(F && "Function is null");
165 auto FuncPtrRegPair = FuncMap.find(F);
166 return FuncPtrRegPair == FuncMap.end() ? Register(0)
167 : FuncPtrRegPair->second;
168 }
169 Register getExtInstSetReg(unsigned SetNum) { return ExtInstSetMap[SetNum]; }
170 InstrList &getMSInstrs(unsigned MSType) { return MS[MSType]; }
173 return InstrsToDelete.contains(MI);
174 }
176 Register AliasReg) {
177 RegisterAliasTable[MF][Reg] = AliasReg;
178 }
180 auto RI = RegisterAliasTable[MF].find(Reg);
181 if (RI == RegisterAliasTable[MF].end()) {
182 return Register(0);
183 }
184 return RegisterAliasTable[MF][Reg];
185 }
187 return RegisterAliasTable.find(MF) != RegisterAliasTable.end() &&
188 RegisterAliasTable[MF].find(Reg) != RegisterAliasTable[MF].end();
189 }
190 unsigned getNextID() { return MaxID++; }
192 return BBNumToRegMap.contains(MBB.getNumber());
193 }
194 // Convert MBB's number to corresponding ID register.
196 auto f = BBNumToRegMap.find(MBB.getNumber());
197 if (f != BBNumToRegMap.end())
198 return f->second;
200 BBNumToRegMap[MBB.getNumber()] = NewReg;
201 return NewReg;
202 }
203};
204} // namespace SPIRV
205
207 static char ID;
208
209public:
211
212 bool runOnModule(Module &M) override;
213 void getAnalysisUsage(AnalysisUsage &AU) const override;
215
216private:
217 void setBaseInfo(const Module &M);
218 void collectGlobalEntities(
219 const std::vector<SPIRV::DTSortableEntry *> &DepsGraph,
221 std::function<bool(const SPIRV::DTSortableEntry *)> Pred,
222 bool UsePreOrder);
223 void processDefInstrs(const Module &M);
224 void collectFuncNames(MachineInstr &MI, const Function *F);
225 void processOtherInstrs(const Module &M);
226 void numberRegistersGlobally(const Module &M);
227 void collectFuncPtrs();
228 void collectFuncPtrs(MachineInstr *MI);
229
230 const SPIRVSubtarget *ST;
232 const SPIRVInstrInfo *TII;
234};
235} // namespace llvm
236#endif // LLVM_LIB_TARGET_SPIRV_SPIRVMODULEANALYSIS_H
MachineBasicBlock & MBB
This file defines the StringMap class.
ReachingDefAnalysis InstSet & ToRemove
basic Basic Alias true
This file defines the DenseMap class.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
unsigned Reg
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
This file defines the SmallVector class.
Represent the analysis usage information of a pass.
Implements a dense probed hash-table based set.
Definition: DenseSet.h:271
Representation of each machine instruction.
Definition: MachineInstr.h:69
This class contains meta information specific to a module.
ModulePass class - This class is used to implement unstructured interprocedural optimizations and ana...
Definition: Pass.h:251
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
void clear()
Definition: SmallSet.h:218
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:179
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringSet - A wrapper for StringMap that provides set-like functionality.
Definition: StringSet.h:23
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
Definition: DenseSet.h:185
std::map< const MachineFunction *, LocalToGlobalRegTable > RegisterAliasMapTy
std::map< Register, Register > LocalToGlobalRegTable
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static struct SPIRV::ModuleAnalysisInfo MAI
bool runOnModule(Module &M) override
runOnModule - Virtual method overriden by subclasses to process the module being operated on.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Register getRegisterAlias(const MachineFunction *MF, Register Reg)
SmallVector< MachineInstr *, 4 > GlobalVarList
Register getExtInstSetReg(unsigned SetNum)
bool hasMBBRegister(const MachineBasicBlock &MBB)
DenseMap< const Function *, Register > FuncMap
void setRegisterAlias(const MachineFunction *MF, Register Reg, Register AliasReg)
bool hasRegisterAlias(const MachineFunction *MF, Register Reg)
Register getOrCreateMBBRegister(const MachineBasicBlock &MBB)
InstrList & getMSInstrs(unsigned MSType)
bool getSkipEmission(const MachineInstr *MI)
DenseMap< int, Register > BBNumToRegMap
InstrList MS[NUM_MODULE_SECTIONS]
AddressingModel::AddressingModel Addr
void setSkipEmission(MachineInstr *MI)
SourceLanguage::SourceLanguage SrcLang
Register getFuncReg(const Function *F)
DenseSet< MachineInstr * > InstrsToDelete
DenseMap< unsigned, Register > ExtInstSetMap
void checkSatisfiable(const SPIRVSubtarget &ST) const
void getAndAddRequirements(SPIRV::OperandCategory::OperandCategory Category, uint32_t i, const SPIRVSubtarget &ST)
void addRequirements(const Requirements &Req)
bool isCapabilityAvailable(Capability::Capability Cap) const
void removeCapabilityIf(const Capability::Capability ToRemove, const Capability::Capability IfPresent)
void addExtensions(const ExtensionList &ToAdd)
void addAvailableCaps(const CapabilityList &ToAdd)
void addExtension(Extension::Extension ToAdd)
void initAvailableCapabilities(const SPIRVSubtarget &ST)
void addCapability(Capability::Capability ToAdd)
void addCapabilities(const CapabilityList &ToAdd)
const CapabilityList & getMinimalCapabilities() const
const SmallSet< Extension::Extension, 4 > & getExtensions() const
Requirements(bool IsSatisfiable=false, std::optional< Capability::Capability > Cap={}, ExtensionList Exts={}, unsigned MinVer=0, unsigned MaxVer=0)
const std::optional< Capability::Capability > Cap
Requirements(Capability::Capability Cap)