#include "ARM.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMBasicBlockInfo.h"
#include "ARMSubtarget.h"
#include "MVETailPredUtils.h"
#include "Thumb2InstrInfo.h"
#include "llvm/ADT/SetOperations.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineLoopUtils.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/ReachingDefAnalysis.h"
#include "llvm/MC/MCInstrDesc.h"

Include dependency graph for ARMLowOverheadLoops.cpp:

Macros
#define	DEBUG_TYPE "arm-low-overhead-loops"

#define	ARM_LOW_OVERHEAD_LOOPS_NAME "ARM Low Overhead Loops pass"

Functions
static bool	isVectorPredicated (MachineInstr *MI)

static bool	isVectorPredicate (MachineInstr *MI)

static bool	hasVPRUse (MachineInstr &MI)

static bool	isDomainMVE (MachineInstr *MI)

static int	getVecSize (const MachineInstr &MI)

static bool	shouldInspect (MachineInstr &MI)

	INITIALIZE_PASS (ARMLowOverheadLoops, DEBUG_TYPE, ARM_LOW_OVERHEAD_LOOPS_NAME, false, false) static bool TryRemove(MachineInstr *MI

	if (!RDA.isSafeToRemove(MI, Uses, Ignore)) return false

	if (WontCorruptITs(Uses, RDA))

static bool	isRegInClass (const MachineOperand &MO, const TargetRegisterClass *Class)

static bool	retainsPreviousHalfElement (const MachineInstr &MI)

static bool	producesDoubleWidthResult (const MachineInstr &MI)

static bool	isHorizontalReduction (const MachineInstr &MI)

static bool	canGenerateNonZeros (const MachineInstr &MI)

static bool	producesFalseLanesZero (MachineInstr &MI, const TargetRegisterClass *QPRs, const ReachingDefAnalysis &RDA, InstSet &FalseLanesZero)

static bool	ValidateMVEStore (MachineInstr MI, MachineLoop ML)

Variables
static cl::opt< bool >	DisableTailPredication ("arm-loloops-disable-tailpred", cl::Hidden, cl::desc("Disable tail-predication in the ARM LowOverheadLoop pass"), cl::init(false))

static cl::opt< bool >	DisableOmitDLS ("arm-disable-omit-dls", cl::Hidden, cl::desc("Disable omitting 'dls lr, lr' instructions"), cl::init(false))

ReachingDefAnalysis &	RDA

ReachingDefAnalysis InstSet &	ToRemove

ReachingDefAnalysis InstSet InstSet &	Ignore

SmallPtrSet< MachineInstr *, 2 >	Uses

return	false

Detailed Description

Finalize v8.1-m low-overhead loops by converting the associated pseudo instructions into machine operations. The expectation is that the loop contains three pseudo instructions:

t2*LoopStart - placed in the preheader or pre-preheader. The do-loop form should be in the preheader, whereas the while form should be in the preheaders only predecessor.
t2LoopDec - placed within in the loop body.
t2LoopEnd - the loop latch terminator.

In addition to this, we also look for the presence of the VCTP instruction, which determines whether we can generated the tail-predicated low-overhead loop form.

Assumptions and Dependencies: Low-overhead loops are constructed and executed using a setup instruction: DLS, WLS, DLSTP or WLSTP and an instruction that loops back: LE or LETP. WLS(TP) and LE(TP) are branching instructions with a (large) limited range but fixed polarity: WLS can only branch forwards and LE can only branch backwards. These restrictions mean that this pass is dependent upon block layout and block sizes, which is why it's the last pass to run. The same is true for ConstantIslands, but this pass does not increase the size of the basic blocks, nor does it change the CFG. Instructions are mainly removed during the transform and pseudo instructions are replaced by real ones. In some cases, when we have to revert to a 'normal' loop, we have to introduce multiple instructions for a single pseudo (see RevertWhile and RevertLoopEnd). To handle this situation, t2WhileLoopStartLR and t2LoopEnd are defined to be as large as this maximum sequence of replacement instructions.

A note on VPR.P0 (the lane mask): VPT, VCMP, VPNOT and VCTP won't overwrite VPR.P0 when they update it in a "VPT Active" context (which includes low-overhead loops and vpt blocks). They will simply "and" the result of their calculation with the current value of VPR.P0. You can think of it like this:

/// if VPT active:    ; Between a DLSTP/LETP, or for predicated instrs
///   VPR.P0 &= Value
/// else
///   VPR.P0 = Value
///

When we're inside the low-overhead loop (between DLSTP and LETP), we always fall in the "VPT active" case, so we can consider that all VPR writes by one of those instruction is actually a "and".

Definition in file ARMLowOverheadLoops.cpp.

Macro Definition Documentation

◆ ARM_LOW_OVERHEAD_LOOPS_NAME

#define ARM_LOW_OVERHEAD_LOOPS_NAME "ARM Low Overhead Loops pass"

Definition at line 77 of file ARMLowOverheadLoops.cpp.

◆ DEBUG_TYPE

#define DEBUG_TYPE "arm-low-overhead-loops"

Definition at line 76 of file ARMLowOverheadLoops.cpp.

Function Documentation

◆ canGenerateNonZeros()

static bool canGenerateNonZeros ( const MachineInstr & MI )

static

Definition at line 854 of file ARMLowOverheadLoops.cpp.

References MI, and producesDoubleWidthResult().

Referenced by producesFalseLanesZero().

◆ getVecSize()

static int getVecSize ( const MachineInstr & MI )

static

Definition at line 107 of file ARMLowOverheadLoops.cpp.

References MI, llvm::MCInstrDesc::TSFlags, llvm::ARMII::VecSize, and llvm::ARMII::VecSizeShift.

◆ hasVPRUse()

static bool hasVPRUse ( MachineInstr & MI )

static

Definition at line 98 of file ARMLowOverheadLoops.cpp.

References MI.

Referenced by shouldInspect().

◆ if() [1/2]

if ( !RDA. isSafeToRemoveMI, Uses, Ignore )

◆ if() [2/2]

if ( WontCorruptITs(Uses, RDA) )

Definition at line 594 of file ARMLowOverheadLoops.cpp.

References llvm::SmallPtrSetImpl< PtrType >::begin(), llvm::ReachingDefAnalysis::collectKilledOperands(), llvm::dbgs(), llvm::RegState::Dead, llvm::SmallPtrSetImpl< PtrType >::end(), LLVM_DEBUG, MI, RDA, ToRemove, and Uses.

◆ INITIALIZE_PASS()

INITIALIZE_PASS	(	ARMLowOverheadLoops	,
		DEBUG_TYPE	,
		ARM_LOW_OVERHEAD_LOOPS_NAME	,
		false	,
		false
	)

◆ isDomainMVE()

static bool isDomainMVE ( MachineInstr * MI )

static

Definition at line 102 of file ARMLowOverheadLoops.cpp.

References llvm::ARMII::DomainMask, llvm::ARMII::DomainMVE, and MI.

Referenced by shouldInspect().

◆ isHorizontalReduction()

static bool isHorizontalReduction ( const MachineInstr & MI )

static

Definition at line 844 of file ARMLowOverheadLoops.cpp.

References llvm::ARMII::HorizontalReduction, MI, and llvm::MCInstrDesc::TSFlags.

Referenced by producesFalseLanesZero().

◆ isRegInClass()

static bool isRegInClass	(	const MachineOperand &	MO,
		const TargetRegisterClass *	Class
	)

static

Definition at line 821 of file ARMLowOverheadLoops.cpp.

References llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().

Referenced by producesFalseLanesZero().

◆ isVectorPredicate()

static bool isVectorPredicate ( MachineInstr * MI )

static

Definition at line 94 of file ARMLowOverheadLoops.cpp.

References MI.

Referenced by shouldInspect().

◆ isVectorPredicated()

static bool isVectorPredicated ( MachineInstr * MI )

static

Definition at line 89 of file ARMLowOverheadLoops.cpp.

References llvm::findFirstVPTPredOperandIdx(), and MI.

Referenced by producesFalseLanesZero().

◆ producesDoubleWidthResult()

static bool producesDoubleWidthResult ( const MachineInstr & MI )

static

Definition at line 838 of file ARMLowOverheadLoops.cpp.

References llvm::ARMII::DoubleWidthResult, MI, and llvm::MCInstrDesc::TSFlags.

Referenced by canGenerateNonZeros().

◆ producesFalseLanesZero()

static bool producesFalseLanesZero	(	MachineInstr &	MI,
		const TargetRegisterClass *	QPRs,
		const ReachingDefAnalysis &	RDA,
		InstSet &	FalseLanesZero
	)

static

Definition at line 883 of file ARMLowOverheadLoops.cpp.

References canGenerateNonZeros(), llvm::dbgs(), llvm::tgtok::Def, llvm::SmallPtrSetImplBase::empty(), llvm::AArch64::FalseLanesZero, llvm::findFirstVPTPredOperandIdx(), llvm::ReachingDefAnalysis::getGlobalReachingDefs(), llvm::MachineOperand::getReg(), isHorizontalReduction(), llvm::ARM_MC::isPredicated(), llvm::MachineOperand::isReg(), isRegInClass(), llvm::MachineOperand::isUse(), isVectorPredicated(), LLVM_DEBUG, MI, and RDA.

◆ retainsPreviousHalfElement()

static bool retainsPreviousHalfElement ( const MachineInstr & MI )

static

Definition at line 829 of file ARMLowOverheadLoops.cpp.

References MI, llvm::ARMII::RetainsPreviousHalfElement, and llvm::MCInstrDesc::TSFlags.

◆ shouldInspect()

static bool shouldInspect ( MachineInstr & MI )

static

Definition at line 113 of file ARMLowOverheadLoops.cpp.

References hasVPRUse(), isDomainMVE(), isVectorPredicate(), and MI.

◆ ValidateMVEStore()

static bool ValidateMVEStore	(	MachineInstr *	MI,
		MachineLoop *	ML
	)

static

Definition at line 1145 of file ARMLowOverheadLoops.cpp.

References BB, llvm::SmallPtrSetImpl< PtrType >::contains(), llvm::PseudoSourceValue::FixedStack, llvm::X86AS::FS, I, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::is_contained(), llvm::PseudoSourceValue::kind(), MI, and ML.

Variable Documentation

◆ DisableOmitDLS

cl::opt<bool> DisableOmitDLS("arm-disable-omit-dls", cl::Hidden, cl::desc("Disable omitting 'dls lr, lr' instructions"), cl::init(false))

static

◆ DisableTailPredication

cl::opt<bool> DisableTailPredication("arm-loloops-disable-tailpred", cl::Hidden, cl::desc("Disable tail-predication in the ARM LowOverheadLoop pass"), cl::init(false))

static