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ARMLowOverheadLoops.cpp
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1//===-- ARMLowOverheadLoops.cpp - CodeGen Low-overhead Loops ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// Finalize v8.1-m low-overhead loops by converting the associated pseudo
10/// instructions into machine operations.
11/// The expectation is that the loop contains three pseudo instructions:
12/// - t2*LoopStart - placed in the preheader or pre-preheader. The do-loop
13/// form should be in the preheader, whereas the while form should be in the
14/// preheaders only predecessor.
15/// - t2LoopDec - placed within in the loop body.
16/// - t2LoopEnd - the loop latch terminator.
17///
18/// In addition to this, we also look for the presence of the VCTP instruction,
19/// which determines whether we can generated the tail-predicated low-overhead
20/// loop form.
21///
22/// Assumptions and Dependencies:
23/// Low-overhead loops are constructed and executed using a setup instruction:
24/// DLS, WLS, DLSTP or WLSTP and an instruction that loops back: LE or LETP.
25/// WLS(TP) and LE(TP) are branching instructions with a (large) limited range
26/// but fixed polarity: WLS can only branch forwards and LE can only branch
27/// backwards. These restrictions mean that this pass is dependent upon block
28/// layout and block sizes, which is why it's the last pass to run. The same is
29/// true for ConstantIslands, but this pass does not increase the size of the
30/// basic blocks, nor does it change the CFG. Instructions are mainly removed
31/// during the transform and pseudo instructions are replaced by real ones. In
32/// some cases, when we have to revert to a 'normal' loop, we have to introduce
33/// multiple instructions for a single pseudo (see RevertWhile and
34/// RevertLoopEnd). To handle this situation, t2WhileLoopStartLR and t2LoopEnd
35/// are defined to be as large as this maximum sequence of replacement
36/// instructions.
37///
38/// A note on VPR.P0 (the lane mask):
39/// VPT, VCMP, VPNOT and VCTP won't overwrite VPR.P0 when they update it in a
40/// "VPT Active" context (which includes low-overhead loops and vpt blocks).
41/// They will simply "and" the result of their calculation with the current
42/// value of VPR.P0. You can think of it like this:
43/// \verbatim
44/// if VPT active: ; Between a DLSTP/LETP, or for predicated instrs
45/// VPR.P0 &= Value
46/// else
47/// VPR.P0 = Value
48/// \endverbatim
49/// When we're inside the low-overhead loop (between DLSTP and LETP), we always
50/// fall in the "VPT active" case, so we can consider that all VPR writes by
51/// one of those instruction is actually a "and".
52//===----------------------------------------------------------------------===//
53
54#include "ARM.h"
55#include "ARMBaseInstrInfo.h"
56#include "ARMBaseRegisterInfo.h"
57#include "ARMBasicBlockInfo.h"
58#include "ARMSubtarget.h"
59#include "MVETailPredUtils.h"
60#include "Thumb2InstrInfo.h"
62#include "llvm/ADT/SetVector.h"
69#include "llvm/CodeGen/Passes.h"
71#include "llvm/MC/MCInstrDesc.h"
72
73using namespace llvm;
74
75#define DEBUG_TYPE "arm-low-overhead-loops"
76#define ARM_LOW_OVERHEAD_LOOPS_NAME "ARM Low Overhead Loops pass"
77
78static cl::opt<bool>
79DisableTailPredication("arm-loloops-disable-tailpred", cl::Hidden,
80 cl::desc("Disable tail-predication in the ARM LowOverheadLoop pass"),
81 cl::init(false));
82
83static cl::opt<bool>
84 DisableOmitDLS("arm-disable-omit-dls", cl::Hidden,
85 cl::desc("Disable omitting 'dls lr, lr' instructions"),
86 cl::init(false));
87
90 return PIdx != -1 && MI->getOperand(PIdx + 1).getReg() == ARM::VPR;
91}
92
94 return MI->findRegisterDefOperandIdx(ARM::VPR) != -1;
95}
96
97static bool hasVPRUse(MachineInstr &MI) {
98 return MI.findRegisterUseOperandIdx(ARM::VPR) != -1;
99}
100
102 uint64_t Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
103 return Domain == ARMII::DomainMVE;
104}
105
106static int getVecSize(const MachineInstr &MI) {
107 const MCInstrDesc &MCID = MI.getDesc();
108 uint64_t Flags = MCID.TSFlags;
109 return (Flags & ARMII::VecSize) >> ARMII::VecSizeShift;
110}
111
113 if (MI.isDebugInstr())
114 return false;
115 return isDomainMVE(&MI) || isVectorPredicate(&MI) || hasVPRUse(MI);
116}
117
118namespace {
119
120 using InstSet = SmallPtrSetImpl<MachineInstr *>;
121
122 class PostOrderLoopTraversal {
124 MachineLoopInfo &MLI;
127
128 public:
129 PostOrderLoopTraversal(MachineLoop &ML, MachineLoopInfo &MLI)
130 : ML(ML), MLI(MLI) { }
131
132 const SmallVectorImpl<MachineBasicBlock*> &getOrder() const {
133 return Order;
134 }
135
136 // Visit all the blocks within the loop, as well as exit blocks and any
137 // blocks properly dominating the header.
138 void ProcessLoop() {
139 std::function<void(MachineBasicBlock*)> Search = [this, &Search]
140 (MachineBasicBlock *MBB) -> void {
141 if (Visited.count(MBB))
142 return;
143
144 Visited.insert(MBB);
145 for (auto *Succ : MBB->successors()) {
146 if (!ML.contains(Succ))
147 continue;
148 Search(Succ);
149 }
150 Order.push_back(MBB);
151 };
152
153 // Insert exit blocks.
155 ML.getExitBlocks(ExitBlocks);
156 append_range(Order, ExitBlocks);
157
158 // Then add the loop body.
159 Search(ML.getHeader());
160
161 // Then try the preheader and its predecessors.
162 std::function<void(MachineBasicBlock*)> GetPredecessor =
163 [this, &GetPredecessor] (MachineBasicBlock *MBB) -> void {
164 Order.push_back(MBB);
165 if (MBB->pred_size() == 1)
166 GetPredecessor(*MBB->pred_begin());
167 };
168
169 if (auto *Preheader = ML.getLoopPreheader())
170 GetPredecessor(Preheader);
171 else if (auto *Preheader = MLI.findLoopPreheader(&ML, true, true))
172 GetPredecessor(Preheader);
173 }
174 };
175
176 struct PredicatedMI {
177 MachineInstr *MI = nullptr;
178 SetVector<MachineInstr*> Predicates;
179
180 public:
181 PredicatedMI(MachineInstr *I, SetVector<MachineInstr *> &Preds) : MI(I) {
182 assert(I && "Instruction must not be null!");
183 Predicates.insert(Preds.begin(), Preds.end());
184 }
185 };
186
187 // Represent the current state of the VPR and hold all instances which
188 // represent a VPT block, which is a list of instructions that begins with a
189 // VPT/VPST and has a maximum of four proceeding instructions. All
190 // instructions within the block are predicated upon the vpr and we allow
191 // instructions to define the vpr within in the block too.
192 class VPTState {
193 friend struct LowOverheadLoop;
194
196
198 static SetVector<MachineInstr *> CurrentPredicates;
199 static std::map<MachineInstr *,
200 std::unique_ptr<PredicatedMI>> PredicatedInsts;
201
202 static void CreateVPTBlock(MachineInstr *MI) {
203 assert((CurrentPredicates.size() || MI->getParent()->isLiveIn(ARM::VPR))
204 && "Can't begin VPT without predicate");
205 Blocks.emplace_back(MI);
206 // The execution of MI is predicated upon the current set of instructions
207 // that are AND'ed together to form the VPR predicate value. In the case
208 // that MI is a VPT, CurrentPredicates will also just be MI.
209 PredicatedInsts.emplace(
210 MI, std::make_unique<PredicatedMI>(MI, CurrentPredicates));
211 }
212
213 static void reset() {
214 Blocks.clear();
215 PredicatedInsts.clear();
216 CurrentPredicates.clear();
217 }
218
219 static void addInst(MachineInstr *MI) {
220 Blocks.back().insert(MI);
221 PredicatedInsts.emplace(
222 MI, std::make_unique<PredicatedMI>(MI, CurrentPredicates));
223 }
224
225 static void addPredicate(MachineInstr *MI) {
226 LLVM_DEBUG(dbgs() << "ARM Loops: Adding VPT Predicate: " << *MI);
227 CurrentPredicates.insert(MI);
228 }
229
230 static void resetPredicate(MachineInstr *MI) {
231 LLVM_DEBUG(dbgs() << "ARM Loops: Resetting VPT Predicate: " << *MI);
232 CurrentPredicates.clear();
233 CurrentPredicates.insert(MI);
234 }
235
236 public:
237 // Have we found an instruction within the block which defines the vpr? If
238 // so, not all the instructions in the block will have the same predicate.
239 static bool hasUniformPredicate(VPTState &Block) {
240 return getDivergent(Block) == nullptr;
241 }
242
243 // If it exists, return the first internal instruction which modifies the
244 // VPR.
245 static MachineInstr *getDivergent(VPTState &Block) {
246 SmallVectorImpl<MachineInstr *> &Insts = Block.getInsts();
247 for (unsigned i = 1; i < Insts.size(); ++i) {
248 MachineInstr *Next = Insts[i];
249 if (isVectorPredicate(Next))
250 return Next; // Found an instruction altering the vpr.
251 }
252 return nullptr;
253 }
254
255 // Return whether the given instruction is predicated upon a VCTP.
256 static bool isPredicatedOnVCTP(MachineInstr *MI, bool Exclusive = false) {
257 SetVector<MachineInstr *> &Predicates = PredicatedInsts[MI]->Predicates;
258 if (Exclusive && Predicates.size() != 1)
259 return false;
260 return llvm::any_of(Predicates, isVCTP);
261 }
262
263 // Is the VPST, controlling the block entry, predicated upon a VCTP.
264 static bool isEntryPredicatedOnVCTP(VPTState &Block,
265 bool Exclusive = false) {
266 SmallVectorImpl<MachineInstr *> &Insts = Block.getInsts();
267 return isPredicatedOnVCTP(Insts.front(), Exclusive);
268 }
269
270 // If this block begins with a VPT, we can check whether it's using
271 // at least one predicated input(s), as well as possible loop invariant
272 // which would result in it being implicitly predicated.
273 static bool hasImplicitlyValidVPT(VPTState &Block,
275 SmallVectorImpl<MachineInstr *> &Insts = Block.getInsts();
276 MachineInstr *VPT = Insts.front();
277 assert(isVPTOpcode(VPT->getOpcode()) &&
278 "Expected VPT block to begin with VPT/VPST");
279
280 if (VPT->getOpcode() == ARM::MVE_VPST)
281 return false;
282
283 auto IsOperandPredicated = [&](MachineInstr *MI, unsigned Idx) {
284 MachineInstr *Op = RDA.getMIOperand(MI, MI->getOperand(Idx));
285 return Op && PredicatedInsts.count(Op) && isPredicatedOnVCTP(Op);
286 };
287
288 auto IsOperandInvariant = [&](MachineInstr *MI, unsigned Idx) {
289 MachineOperand &MO = MI->getOperand(Idx);
290 if (!MO.isReg() || !MO.getReg())
291 return true;
292
294 RDA.getGlobalReachingDefs(MI, MO.getReg(), Defs);
295 if (Defs.empty())
296 return true;
297
298 for (auto *Def : Defs)
299 if (Def->getParent() == VPT->getParent())
300 return false;
301 return true;
302 };
303
304 // Check that at least one of the operands is directly predicated on a
305 // vctp and allow an invariant value too.
306 return (IsOperandPredicated(VPT, 1) || IsOperandPredicated(VPT, 2)) &&
307 (IsOperandPredicated(VPT, 1) || IsOperandInvariant(VPT, 1)) &&
308 (IsOperandPredicated(VPT, 2) || IsOperandInvariant(VPT, 2));
309 }
310
311 static bool isValid(ReachingDefAnalysis &RDA) {
312 // All predication within the loop should be based on vctp. If the block
313 // isn't predicated on entry, check whether the vctp is within the block
314 // and that all other instructions are then predicated on it.
315 for (auto &Block : Blocks) {
316 if (isEntryPredicatedOnVCTP(Block, false) ||
317 hasImplicitlyValidVPT(Block, RDA))
318 continue;
319
320 SmallVectorImpl<MachineInstr *> &Insts = Block.getInsts();
321 // We don't know how to convert a block with just a VPT;VCTP into
322 // anything valid once we remove the VCTP. For now just bail out.
323 assert(isVPTOpcode(Insts.front()->getOpcode()) &&
324 "Expected VPT block to start with a VPST or VPT!");
325 if (Insts.size() == 2 && Insts.front()->getOpcode() != ARM::MVE_VPST &&
326 isVCTP(Insts.back()))
327 return false;
328
329 for (auto *MI : Insts) {
330 // Check that any internal VCTPs are 'Then' predicated.
332 return false;
333 // Skip other instructions that build up the predicate.
334 if (MI->getOpcode() == ARM::MVE_VPST || isVectorPredicate(MI))
335 continue;
336 // Check that any other instructions are predicated upon a vctp.
337 // TODO: We could infer when VPTs are implicitly predicated on the
338 // vctp (when the operands are predicated).
339 if (!isPredicatedOnVCTP(MI)) {
340 LLVM_DEBUG(dbgs() << "ARM Loops: Can't convert: " << *MI);
341 return false;
342 }
343 }
344 }
345 return true;
346 }
347
348 VPTState(MachineInstr *MI) { Insts.push_back(MI); }
349
350 void insert(MachineInstr *MI) {
351 Insts.push_back(MI);
352 // VPT/VPST + 4 predicated instructions.
353 assert(Insts.size() <= 5 && "Too many instructions in VPT block!");
354 }
355
356 bool containsVCTP() const {
357 return llvm::any_of(Insts, isVCTP);
358 }
359
360 unsigned size() const { return Insts.size(); }
361 SmallVectorImpl<MachineInstr *> &getInsts() { return Insts; }
362 };
363
364 struct LowOverheadLoop {
365
367 MachineBasicBlock *Preheader = nullptr;
368 MachineLoopInfo &MLI;
370 const TargetRegisterInfo &TRI;
371 const ARMBaseInstrInfo &TII;
372 MachineFunction *MF = nullptr;
373 MachineBasicBlock::iterator StartInsertPt;
374 MachineBasicBlock *StartInsertBB = nullptr;
375 MachineInstr *Start = nullptr;
376 MachineInstr *Dec = nullptr;
377 MachineInstr *End = nullptr;
378 MachineOperand TPNumElements;
381 SmallPtrSet<MachineInstr *, 4> BlockMasksToRecompute;
382 SmallPtrSet<MachineInstr *, 4> DoubleWidthResultInstrs;
384 bool Revert = false;
385 bool CannotTailPredicate = false;
386
387 LowOverheadLoop(MachineLoop &ML, MachineLoopInfo &MLI,
389 const ARMBaseInstrInfo &TII)
390 : ML(ML), MLI(MLI), RDA(RDA), TRI(TRI), TII(TII),
391 TPNumElements(MachineOperand::CreateImm(0)) {
392 MF = ML.getHeader()->getParent();
393 if (auto *MBB = ML.getLoopPreheader())
394 Preheader = MBB;
395 else if (auto *MBB = MLI.findLoopPreheader(&ML, true, true))
396 Preheader = MBB;
397 VPTState::reset();
398 }
399
400 // If this is an MVE instruction, check that we know how to use tail
401 // predication with it. Record VPT blocks and return whether the
402 // instruction is valid for tail predication.
403 bool ValidateMVEInst(MachineInstr *MI);
404
405 void AnalyseMVEInst(MachineInstr *MI) {
406 CannotTailPredicate = !ValidateMVEInst(MI);
407 }
408
409 bool IsTailPredicationLegal() const {
410 // For now, let's keep things really simple and only support a single
411 // block for tail predication.
412 return !Revert && FoundAllComponents() && !VCTPs.empty() &&
413 !CannotTailPredicate && ML.getNumBlocks() == 1;
414 }
415
416 // Given that MI is a VCTP, check that is equivalent to any other VCTPs
417 // found.
418 bool AddVCTP(MachineInstr *MI);
419
420 // Check that the predication in the loop will be equivalent once we
421 // perform the conversion. Also ensure that we can provide the number
422 // of elements to the loop start instruction.
423 bool ValidateTailPredicate();
424
425 // Check that any values available outside of the loop will be the same
426 // after tail predication conversion.
427 bool ValidateLiveOuts();
428
429 // Check the branch targets are within range and we satisfy our
430 // restrictions.
431 void Validate(ARMBasicBlockUtils *BBUtils);
432
433 bool FoundAllComponents() const {
434 return Start && Dec && End;
435 }
436
437 SmallVectorImpl<VPTState> &getVPTBlocks() {
438 return VPTState::Blocks;
439 }
440
441 // Return the operand for the loop start instruction. This will be the loop
442 // iteration count, or the number of elements if we're tail predicating.
443 MachineOperand &getLoopStartOperand() {
444 if (IsTailPredicationLegal())
445 return TPNumElements;
446 return Start->getOperand(1);
447 }
448
449 unsigned getStartOpcode() const {
450 bool IsDo = isDoLoopStart(*Start);
451 if (!IsTailPredicationLegal())
452 return IsDo ? ARM::t2DLS : ARM::t2WLS;
453
454 return VCTPOpcodeToLSTP(VCTPs.back()->getOpcode(), IsDo);
455 }
456
457 void dump() const {
458 if (Start) dbgs() << "ARM Loops: Found Loop Start: " << *Start;
459 if (Dec) dbgs() << "ARM Loops: Found Loop Dec: " << *Dec;
460 if (End) dbgs() << "ARM Loops: Found Loop End: " << *End;
461 if (!VCTPs.empty()) {
462 dbgs() << "ARM Loops: Found VCTP(s):\n";
463 for (auto *MI : VCTPs)
464 dbgs() << " - " << *MI;
465 }
466 if (!FoundAllComponents())
467 dbgs() << "ARM Loops: Not a low-overhead loop.\n";
468 else if (!(Start && Dec && End))
469 dbgs() << "ARM Loops: Failed to find all loop components.\n";
470 }
471 };
472
473 class ARMLowOverheadLoops : public MachineFunctionPass {
474 MachineFunction *MF = nullptr;
475 MachineLoopInfo *MLI = nullptr;
476 ReachingDefAnalysis *RDA = nullptr;
477 const ARMBaseInstrInfo *TII = nullptr;
478 MachineRegisterInfo *MRI = nullptr;
479 const TargetRegisterInfo *TRI = nullptr;
480 std::unique_ptr<ARMBasicBlockUtils> BBUtils = nullptr;
481
482 public:
483 static char ID;
484
485 ARMLowOverheadLoops() : MachineFunctionPass(ID) { }
486
487 void getAnalysisUsage(AnalysisUsage &AU) const override {
488 AU.setPreservesCFG();
492 }
493
494 bool runOnMachineFunction(MachineFunction &MF) override;
495
498 MachineFunctionProperties::Property::NoVRegs).set(
499 MachineFunctionProperties::Property::TracksLiveness);
500 }
501
502 StringRef getPassName() const override {
504 }
505
506 private:
507 bool ProcessLoop(MachineLoop *ML);
508
509 bool RevertNonLoops();
510
511 void RevertWhile(MachineInstr *MI) const;
512 void RevertDo(MachineInstr *MI) const;
513
514 bool RevertLoopDec(MachineInstr *MI) const;
515
516 void RevertLoopEnd(MachineInstr *MI, bool SkipCmp = false) const;
517
518 void RevertLoopEndDec(MachineInstr *MI) const;
519
520 void ConvertVPTBlocks(LowOverheadLoop &LoLoop);
521
522 MachineInstr *ExpandLoopStart(LowOverheadLoop &LoLoop);
523
524 void Expand(LowOverheadLoop &LoLoop);
525
526 void IterationCountDCE(LowOverheadLoop &LoLoop);
527 };
528}
529
530char ARMLowOverheadLoops::ID = 0;
531
532SmallVector<VPTState, 4> VPTState::Blocks;
533SetVector<MachineInstr *> VPTState::CurrentPredicates;
534std::map<MachineInstr *,
535 std::unique_ptr<PredicatedMI>> VPTState::PredicatedInsts;
536
538 false, false)
539
540static bool TryRemove(MachineInstr *MI, ReachingDefAnalysis &RDA,
541 InstSet &ToRemove, InstSet &Ignore) {
542
543 // Check that we can remove all of Killed without having to modify any IT
544 // blocks.
545 auto WontCorruptITs = [](InstSet &Killed, ReachingDefAnalysis &RDA) {
546 // Collect the dead code and the MBBs in which they reside.
548 for (auto *Dead : Killed)
549 BasicBlocks.insert(Dead->getParent());
550
551 // Collect IT blocks in all affected basic blocks.
552 std::map<MachineInstr *, SmallPtrSet<MachineInstr *, 2>> ITBlocks;
553 for (auto *MBB : BasicBlocks) {
554 for (auto &IT : *MBB) {
555 if (IT.getOpcode() != ARM::t2IT)
556 continue;
558 ITBlocks[&IT]);
559 }
560 }
561
562 // If we're removing all of the instructions within an IT block, then
563 // also remove the IT instruction.
566 for (auto *Dead : Killed) {
567 if (MachineOperand *MO = Dead->findRegisterUseOperand(ARM::ITSTATE)) {
568 MachineInstr *IT = RDA.getMIOperand(Dead, *MO);
569 RemoveITs.insert(IT);
570 auto &CurrentBlock = ITBlocks[IT];
571 CurrentBlock.erase(Dead);
572 if (CurrentBlock.empty())
573 ModifiedITs.erase(IT);
574 else
575 ModifiedITs.insert(IT);
576 }
577 }
578 if (!ModifiedITs.empty())
579 return false;
580 Killed.insert(RemoveITs.begin(), RemoveITs.end());
581 return true;
582 };
583
586 return false;
587
588 if (WontCorruptITs(Uses, RDA)) {
589 ToRemove.insert(Uses.begin(), Uses.end());
590 LLVM_DEBUG(dbgs() << "ARM Loops: Able to remove: " << *MI
591 << " - can also remove:\n";
592 for (auto *Use : Uses)
593 dbgs() << " - " << *Use);
594
597 if (WontCorruptITs(Killed, RDA)) {
598 ToRemove.insert(Killed.begin(), Killed.end());
599 LLVM_DEBUG(for (auto *Dead : Killed)
600 dbgs() << " - " << *Dead);
601 }
602 return true;
603 }
604 return false;
605}
606
607bool LowOverheadLoop::ValidateTailPredicate() {
608 if (!IsTailPredicationLegal()) {
609 LLVM_DEBUG(if (VCTPs.empty())
610 dbgs() << "ARM Loops: Didn't find a VCTP instruction.\n";
611 dbgs() << "ARM Loops: Tail-predication is not valid.\n");
612 return false;
613 }
614
615 assert(!VCTPs.empty() && "VCTP instruction expected but is not set");
616 assert(ML.getBlocks().size() == 1 &&
617 "Shouldn't be processing a loop with more than one block");
618
620 LLVM_DEBUG(dbgs() << "ARM Loops: tail-predication is disabled\n");
621 return false;
622 }
623
624 if (!VPTState::isValid(RDA)) {
625 LLVM_DEBUG(dbgs() << "ARM Loops: Invalid VPT state.\n");
626 return false;
627 }
628
629 if (!ValidateLiveOuts()) {
630 LLVM_DEBUG(dbgs() << "ARM Loops: Invalid live outs.\n");
631 return false;
632 }
633
634 // For tail predication, we need to provide the number of elements, instead
635 // of the iteration count, to the loop start instruction. The number of
636 // elements is provided to the vctp instruction, so we need to check that
637 // we can use this register at InsertPt.
638 MachineInstr *VCTP = VCTPs.back();
639 if (Start->getOpcode() == ARM::t2DoLoopStartTP ||
640 Start->getOpcode() == ARM::t2WhileLoopStartTP) {
641 TPNumElements = Start->getOperand(2);
642 StartInsertPt = Start;
643 StartInsertBB = Start->getParent();
644 } else {
645 TPNumElements = VCTP->getOperand(1);
646 MCRegister NumElements = TPNumElements.getReg().asMCReg();
647
648 // If the register is defined within loop, then we can't perform TP.
649 // TODO: Check whether this is just a mov of a register that would be
650 // available.
651 if (RDA.hasLocalDefBefore(VCTP, NumElements)) {
652 LLVM_DEBUG(dbgs() << "ARM Loops: VCTP operand is defined in the loop.\n");
653 return false;
654 }
655
656 // The element count register maybe defined after InsertPt, in which case we
657 // need to try to move either InsertPt or the def so that the [w|d]lstp can
658 // use the value.
659
660 if (StartInsertPt != StartInsertBB->end() &&
661 !RDA.isReachingDefLiveOut(&*StartInsertPt, NumElements)) {
662 if (auto *ElemDef =
663 RDA.getLocalLiveOutMIDef(StartInsertBB, NumElements)) {
664 if (RDA.isSafeToMoveForwards(ElemDef, &*StartInsertPt)) {
665 ElemDef->removeFromParent();
666 StartInsertBB->insert(StartInsertPt, ElemDef);
668 << "ARM Loops: Moved element count def: " << *ElemDef);
669 } else if (RDA.isSafeToMoveBackwards(&*StartInsertPt, ElemDef)) {
670 StartInsertPt->removeFromParent();
671 StartInsertBB->insertAfter(MachineBasicBlock::iterator(ElemDef),
672 &*StartInsertPt);
673 LLVM_DEBUG(dbgs() << "ARM Loops: Moved start past: " << *ElemDef);
674 } else {
675 // If we fail to move an instruction and the element count is provided
676 // by a mov, use the mov operand if it will have the same value at the
677 // insertion point
678 MachineOperand Operand = ElemDef->getOperand(1);
679 if (isMovRegOpcode(ElemDef->getOpcode()) &&
680 RDA.getUniqueReachingMIDef(ElemDef, Operand.getReg().asMCReg()) ==
681 RDA.getUniqueReachingMIDef(&*StartInsertPt,
682 Operand.getReg().asMCReg())) {
683 TPNumElements = Operand;
684 NumElements = TPNumElements.getReg();
685 } else {
687 << "ARM Loops: Unable to move element count to loop "
688 << "start instruction.\n");
689 return false;
690 }
691 }
692 }
693 }
694
695 // Especially in the case of while loops, InsertBB may not be the
696 // preheader, so we need to check that the register isn't redefined
697 // before entering the loop.
698 auto CannotProvideElements = [this](MachineBasicBlock *MBB,
699 MCRegister NumElements) {
700 if (MBB->empty())
701 return false;
702 // NumElements is redefined in this block.
703 if (RDA.hasLocalDefBefore(&MBB->back(), NumElements))
704 return true;
705
706 // Don't continue searching up through multiple predecessors.
707 if (MBB->pred_size() > 1)
708 return true;
709
710 return false;
711 };
712
713 // Search backwards for a def, until we get to InsertBB.
714 MachineBasicBlock *MBB = Preheader;
715 while (MBB && MBB != StartInsertBB) {
716 if (CannotProvideElements(MBB, NumElements)) {
717 LLVM_DEBUG(dbgs() << "ARM Loops: Unable to provide element count.\n");
718 return false;
719 }
720 MBB = *MBB->pred_begin();
721 }
722 }
723
724 // Could inserting the [W|D]LSTP cause some unintended affects? In a perfect
725 // world the [w|d]lstp instruction would be last instruction in the preheader
726 // and so it would only affect instructions within the loop body. But due to
727 // scheduling, and/or the logic in this pass (above), the insertion point can
728 // be moved earlier. So if the Loop Start isn't the last instruction in the
729 // preheader, and if the initial element count is smaller than the vector
730 // width, the Loop Start instruction will immediately generate one or more
731 // false lane mask which can, incorrectly, affect the proceeding MVE
732 // instructions in the preheader.
733 if (std::any_of(StartInsertPt, StartInsertBB->end(), shouldInspect)) {
734 LLVM_DEBUG(dbgs() << "ARM Loops: Instruction blocks [W|D]LSTP\n");
735 return false;
736 }
737
738 // For any DoubleWidthResultInstrs we found whilst scanning instructions, they
739 // need to compute an output size that is smaller than the VCTP mask operates
740 // on. The VecSize of the DoubleWidthResult is the larger vector size - the
741 // size it extends into, so any VCTP VecSize <= is valid.
742 unsigned VCTPVecSize = getVecSize(*VCTP);
743 for (MachineInstr *MI : DoubleWidthResultInstrs) {
744 unsigned InstrVecSize = getVecSize(*MI);
745 if (InstrVecSize > VCTPVecSize) {
746 LLVM_DEBUG(dbgs() << "ARM Loops: Double width result larger than VCTP "
747 << "VecSize:\n" << *MI);
748 return false;
749 }
750 }
751
752 // Check that the value change of the element count is what we expect and
753 // that the predication will be equivalent. For this we need:
754 // NumElements = NumElements - VectorWidth. The sub will be a sub immediate
755 // and we can also allow register copies within the chain too.
756 auto IsValidSub = [](MachineInstr *MI, int ExpectedVecWidth) {
757 return -getAddSubImmediate(*MI) == ExpectedVecWidth;
758 };
759
761 // Remove modifications to the element count since they have no purpose in a
762 // tail predicated loop. Explicitly refer to the vctp operand no matter which
763 // register NumElements has been assigned to, since that is what the
764 // modifications will be using
765 if (auto *Def = RDA.getUniqueReachingMIDef(
766 &MBB->back(), VCTP->getOperand(1).getReg().asMCReg())) {
769 unsigned ExpectedVectorWidth = getTailPredVectorWidth(VCTP->getOpcode());
770
771 Ignore.insert(VCTPs.begin(), VCTPs.end());
772
773 if (TryRemove(Def, RDA, ElementChain, Ignore)) {
774 bool FoundSub = false;
775
776 for (auto *MI : ElementChain) {
777 if (isMovRegOpcode(MI->getOpcode()))
778 continue;
779
780 if (isSubImmOpcode(MI->getOpcode())) {
781 if (FoundSub || !IsValidSub(MI, ExpectedVectorWidth)) {
782 LLVM_DEBUG(dbgs() << "ARM Loops: Unexpected instruction in element"
783 " count: " << *MI);
784 return false;
785 }
786 FoundSub = true;
787 } else {
788 LLVM_DEBUG(dbgs() << "ARM Loops: Unexpected instruction in element"
789 " count: " << *MI);
790 return false;
791 }
792 }
793 ToRemove.insert(ElementChain.begin(), ElementChain.end());
794 }
795 }
796
797 // If we converted the LoopStart to a t2DoLoopStartTP/t2WhileLoopStartTP, we
798 // can also remove any extra instructions in the preheader, which often
799 // includes a now unused MOV.
800 if ((Start->getOpcode() == ARM::t2DoLoopStartTP ||
801 Start->getOpcode() == ARM::t2WhileLoopStartTP) &&
802 Preheader && !Preheader->empty() &&
803 !RDA.hasLocalDefBefore(VCTP, VCTP->getOperand(1).getReg())) {
804 if (auto *Def = RDA.getUniqueReachingMIDef(
805 &Preheader->back(), VCTP->getOperand(1).getReg().asMCReg())) {
807 Ignore.insert(VCTPs.begin(), VCTPs.end());
808 TryRemove(Def, RDA, ToRemove, Ignore);
809 }
810 }
811
812 return true;
813}
814
815static bool isRegInClass(const MachineOperand &MO,
816 const TargetRegisterClass *Class) {
817 return MO.isReg() && MO.getReg() && Class->contains(MO.getReg());
818}
819
820// MVE 'narrowing' operate on half a lane, reading from half and writing
821// to half, which are referred to has the top and bottom half. The other
822// half retains its previous value.
824 const MCInstrDesc &MCID = MI.getDesc();
825 uint64_t Flags = MCID.TSFlags;
826 return (Flags & ARMII::RetainsPreviousHalfElement) != 0;
827}
828
829// Some MVE instructions read from the top/bottom halves of their operand(s)
830// and generate a vector result with result elements that are double the
831// width of the input.
833 const MCInstrDesc &MCID = MI.getDesc();
834 uint64_t Flags = MCID.TSFlags;
835 return (Flags & ARMII::DoubleWidthResult) != 0;
836}
837
839 const MCInstrDesc &MCID = MI.getDesc();
840 uint64_t Flags = MCID.TSFlags;
841 return (Flags & ARMII::HorizontalReduction) != 0;
842}
843
844// Can this instruction generate a non-zero result when given only zeroed
845// operands? This allows us to know that, given operands with false bytes
846// zeroed by masked loads, that the result will also contain zeros in those
847// bytes.
849
850 // Check for instructions which can write into a larger element size,
851 // possibly writing into a previous zero'd lane.
853 return true;
854
855 switch (MI.getOpcode()) {
856 default:
857 break;
858 // FIXME: VNEG FP and -0? I think we'll need to handle this once we allow
859 // fp16 -> fp32 vector conversions.
860 // Instructions that perform a NOT will generate 1s from 0s.
861 case ARM::MVE_VMVN:
862 case ARM::MVE_VORN:
863 // Count leading zeros will do just that!
864 case ARM::MVE_VCLZs8:
865 case ARM::MVE_VCLZs16:
866 case ARM::MVE_VCLZs32:
867 return true;
868 }
869 return false;
870}
871
872// Look at its register uses to see if it only can only receive zeros
873// into its false lanes which would then produce zeros. Also check that
874// the output register is also defined by an FalseLanesZero instruction
875// so that if tail-predication happens, the lanes that aren't updated will
876// still be zeros.
878 const TargetRegisterClass *QPRs,
880 InstSet &FalseLanesZero) {
882 return false;
883
884 bool isPredicated = isVectorPredicated(&MI);
885 // Predicated loads will write zeros to the falsely predicated bytes of the
886 // destination register.
887 if (MI.mayLoad())
888 return isPredicated;
889
890 auto IsZeroInit = [](MachineInstr *Def) {
891 return !isVectorPredicated(Def) &&
892 Def->getOpcode() == ARM::MVE_VMOVimmi32 &&
893 Def->getOperand(1).getImm() == 0;
894 };
895
896 bool AllowScalars = isHorizontalReduction(MI);
897 for (auto &MO : MI.operands()) {
898 if (!MO.isReg() || !MO.getReg())
899 continue;
900 if (!isRegInClass(MO, QPRs) && AllowScalars)
901 continue;
902 // Skip the lr predicate reg
904 if (PIdx != -1 && (int)MO.getOperandNo() == PIdx + 2)
905 continue;
906
907 // Check that this instruction will produce zeros in its false lanes:
908 // - If it only consumes false lanes zero or constant 0 (vmov #0)
909 // - If it's predicated, it only matters that it's def register already has
910 // false lane zeros, so we can ignore the uses.
912 RDA.getGlobalReachingDefs(&MI, MO.getReg(), Defs);
913 if (Defs.empty())
914 return false;
915 for (auto *Def : Defs) {
916 if (Def == &MI || FalseLanesZero.count(Def) || IsZeroInit(Def))
917 continue;
918 if (MO.isUse() && isPredicated)
919 continue;
920 return false;
921 }
922 }
923 LLVM_DEBUG(dbgs() << "ARM Loops: Always False Zeros: " << MI);
924 return true;
925}
926
927bool LowOverheadLoop::ValidateLiveOuts() {
928 // We want to find out if the tail-predicated version of this loop will
929 // produce the same values as the loop in its original form. For this to
930 // be true, the newly inserted implicit predication must not change the
931 // the (observable) results.
932 // We're doing this because many instructions in the loop will not be
933 // predicated and so the conversion from VPT predication to tail-predication
934 // can result in different values being produced; due to the tail-predication
935 // preventing many instructions from updating their falsely predicated
936 // lanes. This analysis assumes that all the instructions perform lane-wise
937 // operations and don't perform any exchanges.
938 // A masked load, whether through VPT or tail predication, will write zeros
939 // to any of the falsely predicated bytes. So, from the loads, we know that
940 // the false lanes are zeroed and here we're trying to track that those false
941 // lanes remain zero, or where they change, the differences are masked away
942 // by their user(s).
943 // All MVE stores have to be predicated, so we know that any predicate load
944 // operands, or stored results are equivalent already. Other explicitly
945 // predicated instructions will perform the same operation in the original
946 // loop and the tail-predicated form too. Because of this, we can insert
947 // loads, stores and other predicated instructions into our Predicated
948 // set and build from there.
949 const TargetRegisterClass *QPRs = TRI.getRegClass(ARM::MQPRRegClassID);
950 SetVector<MachineInstr *> FalseLanesUnknown;
953 MachineBasicBlock *Header = ML.getHeader();
954
955 LLVM_DEBUG(dbgs() << "ARM Loops: Validating Live outs\n");
956
957 for (auto &MI : *Header) {
958 if (!shouldInspect(MI))
959 continue;
960
961 if (isVCTP(&MI) || isVPTOpcode(MI.getOpcode()))
962 continue;
963
965 bool retainsOrReduces =
967
968 if (isPredicated)
969 Predicated.insert(&MI);
970 if (producesFalseLanesZero(MI, QPRs, RDA, FalseLanesZero))
971 FalseLanesZero.insert(&MI);
972 else if (MI.getNumDefs() == 0)
973 continue;
974 else if (!isPredicated && retainsOrReduces) {
975 LLVM_DEBUG(dbgs() << " Unpredicated instruction that retainsOrReduces: " << MI);
976 return false;
977 } else if (!isPredicated && MI.getOpcode() != ARM::MQPRCopy)
978 FalseLanesUnknown.insert(&MI);
979 }
980
981 LLVM_DEBUG({
982 dbgs() << " Predicated:\n";
983 for (auto *I : Predicated)
984 dbgs() << " " << *I;
985 dbgs() << " FalseLanesZero:\n";
986 for (auto *I : FalseLanesZero)
987 dbgs() << " " << *I;
988 dbgs() << " FalseLanesUnknown:\n";
989 for (auto *I : FalseLanesUnknown)
990 dbgs() << " " << *I;
991 });
992
993 auto HasPredicatedUsers = [this](MachineInstr *MI, const MachineOperand &MO,
996 RDA.getGlobalUses(MI, MO.getReg().asMCReg(), Uses);
997 for (auto *Use : Uses) {
998 if (Use != MI && !Predicated.count(Use))
999 return false;
1000 }
1001 return true;
1002 };
1003
1004 // Visit the unknowns in reverse so that we can start at the values being
1005 // stored and then we can work towards the leaves, hopefully adding more
1006 // instructions to Predicated. Successfully terminating the loop means that
1007 // all the unknown values have to found to be masked by predicated user(s).
1008 // For any unpredicated values, we store them in NonPredicated so that we
1009 // can later check whether these form a reduction.
1010 SmallPtrSet<MachineInstr*, 2> NonPredicated;
1011 for (auto *MI : reverse(FalseLanesUnknown)) {
1012 for (auto &MO : MI->operands()) {
1013 if (!isRegInClass(MO, QPRs) || !MO.isDef())
1014 continue;
1015 if (!HasPredicatedUsers(MI, MO, Predicated)) {
1016 LLVM_DEBUG(dbgs() << " Found an unknown def of : "
1017 << TRI.getRegAsmName(MO.getReg()) << " at " << *MI);
1018 NonPredicated.insert(MI);
1019 break;
1020 }
1021 }
1022 // Any unknown false lanes have been masked away by the user(s).
1023 if (!NonPredicated.contains(MI))
1024 Predicated.insert(MI);
1025 }
1026
1029 ML.getExitBlocks(ExitBlocks);
1030 assert(ML.getNumBlocks() == 1 && "Expected single block loop!");
1031 assert(ExitBlocks.size() == 1 && "Expected a single exit block");
1032 MachineBasicBlock *ExitBB = ExitBlocks.front();
1033 for (const MachineBasicBlock::RegisterMaskPair &RegMask : ExitBB->liveins()) {
1034 // TODO: Instead of blocking predication, we could move the vctp to the exit
1035 // block and calculate it's operand there in or the preheader.
1036 if (RegMask.PhysReg == ARM::VPR) {
1037 LLVM_DEBUG(dbgs() << " VPR is live in to the exit block.");
1038 return false;
1039 }
1040 // Check Q-regs that are live in the exit blocks. We don't collect scalars
1041 // because they won't be affected by lane predication.
1042 if (QPRs->contains(RegMask.PhysReg))
1043 if (auto *MI = RDA.getLocalLiveOutMIDef(Header, RegMask.PhysReg))
1044 LiveOutMIs.insert(MI);
1045 }
1046
1047 // We've already validated that any VPT predication within the loop will be
1048 // equivalent when we perform the predication transformation; so we know that
1049 // any VPT predicated instruction is predicated upon VCTP. Any live-out
1050 // instruction needs to be predicated, so check this here. The instructions
1051 // in NonPredicated have been found to be a reduction that we can ensure its
1052 // legality. Any MQPRCopy found will need to validate its input as if it was
1053 // live out.
1054 SmallVector<MachineInstr *> Worklist(LiveOutMIs.begin(), LiveOutMIs.end());
1055 while (!Worklist.empty()) {
1056 MachineInstr *MI = Worklist.pop_back_val();
1057 if (MI->getOpcode() == ARM::MQPRCopy) {
1058 VMOVCopies.insert(MI);
1059 MachineInstr *CopySrc =
1060 RDA.getUniqueReachingMIDef(MI, MI->getOperand(1).getReg());
1061 if (CopySrc)
1062 Worklist.push_back(CopySrc);
1063 } else if (NonPredicated.count(MI) && FalseLanesUnknown.contains(MI)) {
1064 LLVM_DEBUG(dbgs() << " Unable to handle live out: " << *MI);
1065 VMOVCopies.clear();
1066 return false;
1067 }
1068 }
1069
1070 return true;
1071}
1072
1073void LowOverheadLoop::Validate(ARMBasicBlockUtils *BBUtils) {
1074 if (Revert)
1075 return;
1076
1077 // Check branch target ranges: WLS[TP] can only branch forwards and LE[TP]
1078 // can only jump back.
1079 auto ValidateRanges = [](MachineInstr *Start, MachineInstr *End,
1080 ARMBasicBlockUtils *BBUtils, MachineLoop &ML) {
1081 MachineBasicBlock *TgtBB = End->getOpcode() == ARM::t2LoopEnd
1082 ? End->getOperand(1).getMBB()
1083 : End->getOperand(2).getMBB();
1084 // TODO Maybe there's cases where the target doesn't have to be the header,
1085 // but for now be safe and revert.
1086 if (TgtBB != ML.getHeader()) {
1087 LLVM_DEBUG(dbgs() << "ARM Loops: LoopEnd is not targeting header.\n");
1088 return false;
1089 }
1090
1091 // The WLS and LE instructions have 12-bits for the label offset. WLS
1092 // requires a positive offset, while LE uses negative.
1093 if (BBUtils->getOffsetOf(End) < BBUtils->getOffsetOf(ML.getHeader()) ||
1094 !BBUtils->isBBInRange(End, ML.getHeader(), 4094)) {
1095 LLVM_DEBUG(dbgs() << "ARM Loops: LE offset is out-of-range\n");
1096 return false;
1097 }
1098
1099 if (isWhileLoopStart(*Start)) {
1100 MachineBasicBlock *TargetBB = getWhileLoopStartTargetBB(*Start);
1101 if (BBUtils->getOffsetOf(Start) > BBUtils->getOffsetOf(TargetBB) ||
1102 !BBUtils->isBBInRange(Start, TargetBB, 4094)) {
1103 LLVM_DEBUG(dbgs() << "ARM Loops: WLS offset is out-of-range!\n");
1104 return false;
1105 }
1106 }
1107 return true;
1108 };
1109
1110 StartInsertPt = MachineBasicBlock::iterator(Start);
1111 StartInsertBB = Start->getParent();
1112 LLVM_DEBUG(dbgs() << "ARM Loops: Will insert LoopStart at "
1113 << *StartInsertPt);
1114
1115 Revert = !ValidateRanges(Start, End, BBUtils, ML);
1116 CannotTailPredicate = !ValidateTailPredicate();
1117}
1118
1119bool LowOverheadLoop::AddVCTP(MachineInstr *MI) {
1120 LLVM_DEBUG(dbgs() << "ARM Loops: Adding VCTP: " << *MI);
1121 if (VCTPs.empty()) {
1122 VCTPs.push_back(MI);
1123 return true;
1124 }
1125
1126 // If we find another VCTP, check whether it uses the same value as the main VCTP.
1127 // If it does, store it in the VCTPs set, else refuse it.
1128 MachineInstr *Prev = VCTPs.back();
1129 if (!Prev->getOperand(1).isIdenticalTo(MI->getOperand(1)) ||
1130 !RDA.hasSameReachingDef(Prev, MI, MI->getOperand(1).getReg().asMCReg())) {
1131 LLVM_DEBUG(dbgs() << "ARM Loops: Found VCTP with a different reaching "
1132 "definition from the main VCTP");
1133 return false;
1134 }
1135 VCTPs.push_back(MI);
1136 return true;
1137}
1138
1140
1141 auto GetFrameIndex = [](MachineMemOperand *Operand) {
1142 const PseudoSourceValue *PseudoValue = Operand->getPseudoValue();
1143 if (PseudoValue && PseudoValue->kind() == PseudoSourceValue::FixedStack) {
1144 if (const auto *FS = dyn_cast<FixedStackPseudoSourceValue>(PseudoValue)) {
1145 return FS->getFrameIndex();
1146 }
1147 }
1148 return -1;
1149 };
1150
1151 auto IsStackOp = [GetFrameIndex](MachineInstr *I) {
1152 switch (I->getOpcode()) {
1153 case ARM::MVE_VSTRWU32:
1154 case ARM::MVE_VLDRWU32: {
1155 return I->getOperand(1).getReg() == ARM::SP &&
1156 I->memoperands().size() == 1 &&
1157 GetFrameIndex(I->memoperands().front()) >= 0;
1158 }
1159 default:
1160 return false;
1161 }
1162 };
1163
1164 // An unpredicated vector register spill is allowed if all of the uses of the
1165 // stack slot are within the loop
1166 if (MI->getOpcode() != ARM::MVE_VSTRWU32 || !IsStackOp(MI))
1167 return false;
1168
1169 // Search all blocks after the loop for accesses to the same stack slot.
1170 // ReachingDefAnalysis doesn't work for sp as it relies on registers being
1171 // live-out (which sp never is) to know what blocks to look in
1172 if (MI->memoperands().size() == 0)
1173 return false;
1174 int FI = GetFrameIndex(MI->memoperands().front());
1175
1176 auto &FrameInfo = MI->getParent()->getParent()->getFrameInfo();
1177 if (FI == -1 || !FrameInfo.isSpillSlotObjectIndex(FI))
1178 return false;
1179
1181 ML->getExitBlocks(Frontier);
1182 SmallPtrSet<MachineBasicBlock *, 4> Visited{MI->getParent()};
1183 unsigned Idx = 0;
1184 while (Idx < Frontier.size()) {
1185 MachineBasicBlock *BB = Frontier[Idx];
1186 bool LookAtSuccessors = true;
1187 for (auto &I : *BB) {
1188 if (!IsStackOp(&I) || I.memoperands().size() == 0)
1189 continue;
1190 if (GetFrameIndex(I.memoperands().front()) != FI)
1191 continue;
1192 // If this block has a store to the stack slot before any loads then we
1193 // can ignore the block
1194 if (I.getOpcode() == ARM::MVE_VSTRWU32) {
1195 LookAtSuccessors = false;
1196 break;
1197 }
1198 // If the store and the load are using the same stack slot then the
1199 // store isn't valid for tail predication
1200 if (I.getOpcode() == ARM::MVE_VLDRWU32)
1201 return false;
1202 }
1203
1204 if (LookAtSuccessors) {
1205 for (auto *Succ : BB->successors()) {
1206 if (!Visited.contains(Succ) && !is_contained(Frontier, Succ))
1207 Frontier.push_back(Succ);
1208 }
1209 }
1210 Visited.insert(BB);
1211 Idx++;
1212 }
1213
1214 return true;
1215}
1216
1217bool LowOverheadLoop::ValidateMVEInst(MachineInstr *MI) {
1218 if (CannotTailPredicate)
1219 return false;
1220
1221 if (!shouldInspect(*MI))
1222 return true;
1223
1224 if (MI->getOpcode() == ARM::MVE_VPSEL ||
1225 MI->getOpcode() == ARM::MVE_VPNOT) {
1226 // TODO: Allow VPSEL and VPNOT, we currently cannot because:
1227 // 1) It will use the VPR as a predicate operand, but doesn't have to be
1228 // instead a VPT block, which means we can assert while building up
1229 // the VPT block because we don't find another VPT or VPST to being a new
1230 // one.
1231 // 2) VPSEL still requires a VPR operand even after tail predicating,
1232 // which means we can't remove it unless there is another
1233 // instruction, such as vcmp, that can provide the VPR def.
1234 return false;
1235 }
1236
1237 // Record all VCTPs and check that they're equivalent to one another.
1238 if (isVCTP(MI) && !AddVCTP(MI))
1239 return false;
1240
1241 // Inspect uses first so that any instructions that alter the VPR don't
1242 // alter the predicate upon themselves.
1243 const MCInstrDesc &MCID = MI->getDesc();
1244 bool IsUse = false;
1245 unsigned LastOpIdx = MI->getNumOperands() - 1;
1246 for (const auto &Op : enumerate(reverse(MCID.operands()))) {
1247 const MachineOperand &MO = MI->getOperand(LastOpIdx - Op.index());
1248 if (!MO.isReg() || !MO.isUse() || MO.getReg() != ARM::VPR)
1249 continue;
1250
1251 if (ARM::isVpred(Op.value().OperandType)) {
1252 VPTState::addInst(MI);
1253 IsUse = true;
1254 } else if (MI->getOpcode() != ARM::MVE_VPST) {
1255 LLVM_DEBUG(dbgs() << "ARM Loops: Found instruction using vpr: " << *MI);
1256 return false;
1257 }
1258 }
1259
1260 // If we find an instruction that has been marked as not valid for tail
1261 // predication, only allow the instruction if it's contained within a valid
1262 // VPT block.
1263 bool RequiresExplicitPredication =
1265 if (isDomainMVE(MI) && RequiresExplicitPredication) {
1266 if (MI->getOpcode() == ARM::MQPRCopy)
1267 return true;
1268 if (!IsUse && producesDoubleWidthResult(*MI)) {
1269 DoubleWidthResultInstrs.insert(MI);
1270 return true;
1271 }
1272
1273 LLVM_DEBUG(if (!IsUse) dbgs()
1274 << "ARM Loops: Can't tail predicate: " << *MI);
1275 return IsUse;
1276 }
1277
1278 // If the instruction is already explicitly predicated, then the conversion
1279 // will be fine, but ensure that all store operations are predicated.
1280 if (MI->mayStore() && !ValidateMVEStore(MI, &ML))
1281 return IsUse;
1282
1283 // If this instruction defines the VPR, update the predicate for the
1284 // proceeding instructions.
1285 if (isVectorPredicate(MI)) {
1286 // Clear the existing predicate when we're not in VPT Active state,
1287 // otherwise we add to it.
1288 if (!isVectorPredicated(MI))
1289 VPTState::resetPredicate(MI);
1290 else
1291 VPTState::addPredicate(MI);
1292 }
1293
1294 // Finally once the predicate has been modified, we can start a new VPT
1295 // block if necessary.
1296 if (isVPTOpcode(MI->getOpcode()))
1297 VPTState::CreateVPTBlock(MI);
1298
1299 return true;
1300}
1301
1302bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &mf) {
1304 if (!ST.hasLOB())
1305 return false;
1306
1307 MF = &mf;
1308 LLVM_DEBUG(dbgs() << "ARM Loops on " << MF->getName() << " ------------- \n");
1309
1310 MLI = &getAnalysis<MachineLoopInfo>();
1311 RDA = &getAnalysis<ReachingDefAnalysis>();
1312 MF->getProperties().set(MachineFunctionProperties::Property::TracksLiveness);
1313 MRI = &MF->getRegInfo();
1314 TII = static_cast<const ARMBaseInstrInfo*>(ST.getInstrInfo());
1315 TRI = ST.getRegisterInfo();
1316 BBUtils = std::unique_ptr<ARMBasicBlockUtils>(new ARMBasicBlockUtils(*MF));
1317 BBUtils->computeAllBlockSizes();
1318 BBUtils->adjustBBOffsetsAfter(&MF->front());
1319
1320 bool Changed = false;
1321 for (auto *ML : *MLI) {
1322 if (ML->isOutermost())
1323 Changed |= ProcessLoop(ML);
1324 }
1325 Changed |= RevertNonLoops();
1326 return Changed;
1327}
1328
1329bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
1330
1331 bool Changed = false;
1332
1333 // Process inner loops first.
1334 for (MachineLoop *L : *ML)
1335 Changed |= ProcessLoop(L);
1336
1337 LLVM_DEBUG({
1338 dbgs() << "ARM Loops: Processing loop containing:\n";
1339 if (auto *Preheader = ML->getLoopPreheader())
1340 dbgs() << " - Preheader: " << printMBBReference(*Preheader) << "\n";
1341 else if (auto *Preheader = MLI->findLoopPreheader(ML, true, true))
1342 dbgs() << " - Preheader: " << printMBBReference(*Preheader) << "\n";
1343 for (auto *MBB : ML->getBlocks())
1344 dbgs() << " - Block: " << printMBBReference(*MBB) << "\n";
1345 });
1346
1347 // Search the given block for a loop start instruction. If one isn't found,
1348 // and there's only one predecessor block, search that one too.
1349 std::function<MachineInstr*(MachineBasicBlock*)> SearchForStart =
1350 [&SearchForStart](MachineBasicBlock *MBB) -> MachineInstr* {
1351 for (auto &MI : *MBB) {
1352 if (isLoopStart(MI))
1353 return &MI;
1354 }
1355 if (MBB->pred_size() == 1)
1356 return SearchForStart(*MBB->pred_begin());
1357 return nullptr;
1358 };
1359
1360 LowOverheadLoop LoLoop(*ML, *MLI, *RDA, *TRI, *TII);
1361 // Search the preheader for the start intrinsic.
1362 // FIXME: I don't see why we shouldn't be supporting multiple predecessors
1363 // with potentially multiple set.loop.iterations, so we need to enable this.
1364 if (LoLoop.Preheader)
1365 LoLoop.Start = SearchForStart(LoLoop.Preheader);
1366 else
1367 return Changed;
1368
1369 // Find the low-overhead loop components and decide whether or not to fall
1370 // back to a normal loop. Also look for a vctp instructions and decide
1371 // whether we can convert that predicate using tail predication.
1372 for (auto *MBB : reverse(ML->getBlocks())) {
1373 for (auto &MI : *MBB) {
1374 if (MI.isDebugValue())
1375 continue;
1376 else if (MI.getOpcode() == ARM::t2LoopDec)
1377 LoLoop.Dec = &MI;
1378 else if (MI.getOpcode() == ARM::t2LoopEnd)
1379 LoLoop.End = &MI;
1380 else if (MI.getOpcode() == ARM::t2LoopEndDec)
1381 LoLoop.End = LoLoop.Dec = &MI;
1382 else if (isLoopStart(MI))
1383 LoLoop.Start = &MI;
1384 else if (MI.getDesc().isCall()) {
1385 // TODO: Though the call will require LE to execute again, does this
1386 // mean we should revert? Always executing LE hopefully should be
1387 // faster than performing a sub,cmp,br or even subs,br.
1388 LoLoop.Revert = true;
1389 LLVM_DEBUG(dbgs() << "ARM Loops: Found call.\n");
1390 } else {
1391 // Record VPR defs and build up their corresponding vpt blocks.
1392 // Check we know how to tail predicate any mve instructions.
1393 LoLoop.AnalyseMVEInst(&MI);
1394 }
1395 }
1396 }
1397
1398 LLVM_DEBUG(LoLoop.dump());
1399 if (!LoLoop.FoundAllComponents()) {
1400 LLVM_DEBUG(dbgs() << "ARM Loops: Didn't find loop start, update, end\n");
1401 return Changed;
1402 }
1403
1404 assert(LoLoop.Start->getOpcode() != ARM::t2WhileLoopStart &&
1405 "Expected t2WhileLoopStart to be removed before regalloc!");
1406
1407 // Check that the only instruction using LoopDec is LoopEnd. This can only
1408 // happen when the Dec and End are separate, not a single t2LoopEndDec.
1409 // TODO: Check for copy chains that really have no effect.
1410 if (LoLoop.Dec != LoLoop.End) {
1412 RDA->getReachingLocalUses(LoLoop.Dec, MCRegister::from(ARM::LR), Uses);
1413 if (Uses.size() > 1 || !Uses.count(LoLoop.End)) {
1414 LLVM_DEBUG(dbgs() << "ARM Loops: Unable to remove LoopDec.\n");
1415 LoLoop.Revert = true;
1416 }
1417 }
1418 LoLoop.Validate(BBUtils.get());
1419 Expand(LoLoop);
1420 return true;
1421}
1422
1423// WhileLoopStart holds the exit block, so produce a cmp lr, 0 and then a
1424// beq that branches to the exit branch.
1425// TODO: We could also try to generate a cbz if the value in LR is also in
1426// another low register.
1427void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const {
1428 LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp: " << *MI);
1430 unsigned BrOpc = BBUtils->isBBInRange(MI, DestBB, 254) ?
1431 ARM::tBcc : ARM::t2Bcc;
1432
1433 RevertWhileLoopStartLR(MI, TII, BrOpc);
1434}
1435
1436void ARMLowOverheadLoops::RevertDo(MachineInstr *MI) const {
1437 LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to mov: " << *MI);
1439}
1440
1441bool ARMLowOverheadLoops::RevertLoopDec(MachineInstr *MI) const {
1442 LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to sub: " << *MI);
1443 MachineBasicBlock *MBB = MI->getParent();
1445 for (auto I = MachineBasicBlock::iterator(MI), E = MBB->end(); I != E; ++I) {
1446 if (I->getOpcode() == ARM::t2LoopEnd) {
1447 Ignore.insert(&*I);
1448 break;
1449 }
1450 }
1451
1452 // If nothing defines CPSR between LoopDec and LoopEnd, use a t2SUBS.
1453 bool SetFlags =
1455
1456 llvm::RevertLoopDec(MI, TII, SetFlags);
1457 return SetFlags;
1458}
1459
1460// Generate a subs, or sub and cmp, and a branch instead of an LE.
1461void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI, bool SkipCmp) const {
1462 LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp, br: " << *MI);
1463
1464 MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
1465 unsigned BrOpc = BBUtils->isBBInRange(MI, DestBB, 254) ?
1466 ARM::tBcc : ARM::t2Bcc;
1467
1468 llvm::RevertLoopEnd(MI, TII, BrOpc, SkipCmp);
1469}
1470
1471// Generate a subs, or sub and cmp, and a branch instead of an LE.
1472void ARMLowOverheadLoops::RevertLoopEndDec(MachineInstr *MI) const {
1473 LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to subs, br: " << *MI);
1474 assert(MI->getOpcode() == ARM::t2LoopEndDec && "Expected a t2LoopEndDec!");
1475 MachineBasicBlock *MBB = MI->getParent();
1476
1478 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2SUBri));
1479 MIB.addDef(ARM::LR);
1480 MIB.add(MI->getOperand(1));
1481 MIB.addImm(1);
1482 MIB.addImm(ARMCC::AL);
1483 MIB.addReg(ARM::NoRegister);
1484 MIB.addReg(ARM::CPSR);
1485 MIB->getOperand(5).setIsDef(true);
1486
1487 MachineBasicBlock *DestBB = MI->getOperand(2).getMBB();
1488 unsigned BrOpc =
1489 BBUtils->isBBInRange(MI, DestBB, 254) ? ARM::tBcc : ARM::t2Bcc;
1490
1491 // Create bne
1492 MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
1493 MIB.add(MI->getOperand(2)); // branch target
1494 MIB.addImm(ARMCC::NE); // condition code
1495 MIB.addReg(ARM::CPSR);
1496
1497 MI->eraseFromParent();
1498}
1499
1500// Perform dead code elimation on the loop iteration count setup expression.
1501// If we are tail-predicating, the number of elements to be processed is the
1502// operand of the VCTP instruction in the vector body, see getCount(), which is
1503// register $r3 in this example:
1504//
1505// $lr = big-itercount-expression
1506// ..
1507// $lr = t2DoLoopStart renamable $lr
1508// vector.body:
1509// ..
1510// $vpr = MVE_VCTP32 renamable $r3
1511// renamable $lr = t2LoopDec killed renamable $lr, 1
1512// t2LoopEnd renamable $lr, %vector.body
1513// tB %end
1514//
1515// What we would like achieve here is to replace the do-loop start pseudo
1516// instruction t2DoLoopStart with:
1517//
1518// $lr = MVE_DLSTP_32 killed renamable $r3
1519//
1520// Thus, $r3 which defines the number of elements, is written to $lr,
1521// and then we want to delete the whole chain that used to define $lr,
1522// see the comment below how this chain could look like.
1523//
1524void ARMLowOverheadLoops::IterationCountDCE(LowOverheadLoop &LoLoop) {
1525 if (!LoLoop.IsTailPredicationLegal())
1526 return;
1527
1528 LLVM_DEBUG(dbgs() << "ARM Loops: Trying DCE on loop iteration count.\n");
1529
1530 MachineInstr *Def = RDA->getMIOperand(LoLoop.Start, 1);
1531 if (!Def) {
1532 LLVM_DEBUG(dbgs() << "ARM Loops: Couldn't find iteration count.\n");
1533 return;
1534 }
1535
1536 // Collect and remove the users of iteration count.
1537 SmallPtrSet<MachineInstr*, 4> Killed = { LoLoop.Start, LoLoop.Dec,
1538 LoLoop.End };
1539 if (!TryRemove(Def, *RDA, LoLoop.ToRemove, Killed))
1540 LLVM_DEBUG(dbgs() << "ARM Loops: Unsafe to remove loop iteration count.\n");
1541}
1542
1543MachineInstr* ARMLowOverheadLoops::ExpandLoopStart(LowOverheadLoop &LoLoop) {
1544 LLVM_DEBUG(dbgs() << "ARM Loops: Expanding LoopStart.\n");
1545 // When using tail-predication, try to delete the dead code that was used to
1546 // calculate the number of loop iterations.
1547 IterationCountDCE(LoLoop);
1548
1549 MachineBasicBlock::iterator InsertPt = LoLoop.StartInsertPt;
1550 MachineInstr *Start = LoLoop.Start;
1551 MachineBasicBlock *MBB = LoLoop.StartInsertBB;
1552 unsigned Opc = LoLoop.getStartOpcode();
1553 MachineOperand &Count = LoLoop.getLoopStartOperand();
1554
1555 // A DLS lr, lr we needn't emit
1556 MachineInstr* NewStart;
1557 if (!DisableOmitDLS && Opc == ARM::t2DLS && Count.isReg() &&
1558 Count.getReg() == ARM::LR) {
1559 LLVM_DEBUG(dbgs() << "ARM Loops: Didn't insert start: DLS lr, lr");
1560 NewStart = nullptr;
1561 } else {
1563 BuildMI(*MBB, InsertPt, Start->getDebugLoc(), TII->get(Opc));
1564
1565 MIB.addDef(ARM::LR);
1566 MIB.add(Count);
1567 if (isWhileLoopStart(*Start))
1568 MIB.addMBB(getWhileLoopStartTargetBB(*Start));
1569
1570 LLVM_DEBUG(dbgs() << "ARM Loops: Inserted start: " << *MIB);
1571 NewStart = &*MIB;
1572 }
1573
1574 LoLoop.ToRemove.insert(Start);
1575 return NewStart;
1576}
1577
1578void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) {
1579 auto RemovePredicate = [](MachineInstr *MI) {
1580 if (MI->isDebugInstr())
1581 return;
1582 LLVM_DEBUG(dbgs() << "ARM Loops: Removing predicate from: " << *MI);
1584 assert(PIdx >= 1 && "Trying to unpredicate a non-predicated instruction");
1585 assert(MI->getOperand(PIdx).getImm() == ARMVCC::Then &&
1586 "Expected Then predicate!");
1587 MI->getOperand(PIdx).setImm(ARMVCC::None);
1588 MI->getOperand(PIdx + 1).setReg(0);
1589 };
1590
1591 for (auto &Block : LoLoop.getVPTBlocks()) {
1592 SmallVectorImpl<MachineInstr *> &Insts = Block.getInsts();
1593
1594 auto ReplaceVCMPWithVPT = [&](MachineInstr *&TheVCMP, MachineInstr *At) {
1595 assert(TheVCMP && "Replacing a removed or non-existent VCMP");
1596 // Replace the VCMP with a VPT
1598 BuildMI(*At->getParent(), At, At->getDebugLoc(),
1599 TII->get(VCMPOpcodeToVPT(TheVCMP->getOpcode())));
1600 MIB.addImm(ARMVCC::Then);
1601 // Register one
1602 MIB.add(TheVCMP->getOperand(1));
1603 // Register two
1604 MIB.add(TheVCMP->getOperand(2));
1605 // The comparison code, e.g. ge, eq, lt
1606 MIB.add(TheVCMP->getOperand(3));
1607 LLVM_DEBUG(dbgs() << "ARM Loops: Combining with VCMP to VPT: " << *MIB);
1608 LoLoop.BlockMasksToRecompute.insert(MIB.getInstr());
1609 LoLoop.ToRemove.insert(TheVCMP);
1610 TheVCMP = nullptr;
1611 };
1612
1613 if (VPTState::isEntryPredicatedOnVCTP(Block, /*exclusive*/ true)) {
1614 MachineInstr *VPST = Insts.front();
1615 if (VPTState::hasUniformPredicate(Block)) {
1616 // A vpt block starting with VPST, is only predicated upon vctp and has no
1617 // internal vpr defs:
1618 // - Remove vpst.
1619 // - Unpredicate the remaining instructions.
1620 LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *VPST);
1621 for (unsigned i = 1; i < Insts.size(); ++i)
1622 RemovePredicate(Insts[i]);
1623 } else {
1624 // The VPT block has a non-uniform predicate but it uses a vpst and its
1625 // entry is guarded only by a vctp, which means we:
1626 // - Need to remove the original vpst.
1627 // - Then need to unpredicate any following instructions, until
1628 // we come across the divergent vpr def.
1629 // - Insert a new vpst to predicate the instruction(s) that following
1630 // the divergent vpr def.
1631 MachineInstr *Divergent = VPTState::getDivergent(Block);
1632 MachineBasicBlock *MBB = Divergent->getParent();
1633 auto DivergentNext = ++MachineBasicBlock::iterator(Divergent);
1634 while (DivergentNext != MBB->end() && DivergentNext->isDebugInstr())
1635 ++DivergentNext;
1636
1637 bool DivergentNextIsPredicated =
1638 DivergentNext != MBB->end() &&
1639 getVPTInstrPredicate(*DivergentNext) != ARMVCC::None;
1640
1641 for (auto I = ++MachineBasicBlock::iterator(VPST), E = DivergentNext;
1642 I != E; ++I)
1643 RemovePredicate(&*I);
1644
1645 // Check if the instruction defining vpr is a vcmp so it can be combined
1646 // with the VPST This should be the divergent instruction
1648 VCMPOpcodeToVPT(Divergent->getOpcode()) != 0 ? Divergent : nullptr;
1649
1650 if (DivergentNextIsPredicated) {
1651 // Insert a VPST at the divergent only if the next instruction
1652 // would actually use it. A VCMP following a VPST can be
1653 // merged into a VPT so do that instead if the VCMP exists.
1654 if (!VCMP) {
1655 // Create a VPST (with a null mask for now, we'll recompute it
1656 // later)
1658 BuildMI(*Divergent->getParent(), Divergent,
1659 Divergent->getDebugLoc(), TII->get(ARM::MVE_VPST));
1660 MIB.addImm(0);
1661 LLVM_DEBUG(dbgs() << "ARM Loops: Created VPST: " << *MIB);
1662 LoLoop.BlockMasksToRecompute.insert(MIB.getInstr());
1663 } else {
1664 // No RDA checks are necessary here since the VPST would have been
1665 // directly after the VCMP
1666 ReplaceVCMPWithVPT(VCMP, VCMP);
1667 }
1668 }
1669 }
1670 LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *VPST);
1671 LoLoop.ToRemove.insert(VPST);
1672 } else if (Block.containsVCTP()) {
1673 // The vctp will be removed, so either the entire block will be dead or
1674 // the block mask of the vp(s)t will need to be recomputed.
1675 MachineInstr *VPST = Insts.front();
1676 if (Block.size() == 2) {
1677 assert(VPST->getOpcode() == ARM::MVE_VPST &&
1678 "Found a VPST in an otherwise empty vpt block");
1679 LoLoop.ToRemove.insert(VPST);
1680 } else
1681 LoLoop.BlockMasksToRecompute.insert(VPST);
1682 } else if (Insts.front()->getOpcode() == ARM::MVE_VPST) {
1683 // If this block starts with a VPST then attempt to merge it with the
1684 // preceeding un-merged VCMP into a VPT. This VCMP comes from a VPT
1685 // block that no longer exists
1686 MachineInstr *VPST = Insts.front();
1687 auto Next = ++MachineBasicBlock::iterator(VPST);
1689 "The instruction after a VPST must be predicated");
1690 (void)Next;
1691 MachineInstr *VprDef = RDA->getUniqueReachingMIDef(VPST, ARM::VPR);
1692 if (VprDef && VCMPOpcodeToVPT(VprDef->getOpcode()) &&
1693 !LoLoop.ToRemove.contains(VprDef)) {
1694 MachineInstr *VCMP = VprDef;
1695 // The VCMP and VPST can only be merged if the VCMP's operands will have
1696 // the same values at the VPST.
1697 // If any of the instructions between the VCMP and VPST are predicated
1698 // then a different code path is expected to have merged the VCMP and
1699 // VPST already.
1700 if (std::none_of(++MachineBasicBlock::iterator(VCMP),
1702 RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(1).getReg()) &&
1703 RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(2).getReg())) {
1704 ReplaceVCMPWithVPT(VCMP, VPST);
1705 LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *VPST);
1706 LoLoop.ToRemove.insert(VPST);
1707 }
1708 }
1709 }
1710 }
1711
1712 LoLoop.ToRemove.insert(LoLoop.VCTPs.begin(), LoLoop.VCTPs.end());
1713}
1714
1715void ARMLowOverheadLoops::Expand(LowOverheadLoop &LoLoop) {
1716
1717 // Combine the LoopDec and LoopEnd instructions into LE(TP).
1718 auto ExpandLoopEnd = [this](LowOverheadLoop &LoLoop) {
1719 MachineInstr *End = LoLoop.End;
1720 MachineBasicBlock *MBB = End->getParent();
1721 unsigned Opc = LoLoop.IsTailPredicationLegal() ?
1722 ARM::MVE_LETP : ARM::t2LEUpdate;
1723 MachineInstrBuilder MIB = BuildMI(*MBB, End, End->getDebugLoc(),
1724 TII->get(Opc));
1725 MIB.addDef(ARM::LR);
1726 unsigned Off = LoLoop.Dec == LoLoop.End ? 1 : 0;
1727 MIB.add(End->getOperand(Off + 0));
1728 MIB.add(End->getOperand(Off + 1));
1729 LLVM_DEBUG(dbgs() << "ARM Loops: Inserted LE: " << *MIB);
1730 LoLoop.ToRemove.insert(LoLoop.Dec);
1731 LoLoop.ToRemove.insert(End);
1732 return &*MIB;
1733 };
1734
1735 // TODO: We should be able to automatically remove these branches before we
1736 // get here - probably by teaching analyzeBranch about the pseudo
1737 // instructions.
1738 // If there is an unconditional branch, after I, that just branches to the
1739 // next block, remove it.
1740 auto RemoveDeadBranch = [](MachineInstr *I) {
1741 MachineBasicBlock *BB = I->getParent();
1743 if (Terminator->isUnconditionalBranch() && I != Terminator) {
1744 MachineBasicBlock *Succ = Terminator->getOperand(0).getMBB();
1745 if (BB->isLayoutSuccessor(Succ)) {
1746 LLVM_DEBUG(dbgs() << "ARM Loops: Removing branch: " << *Terminator);
1747 Terminator->eraseFromParent();
1748 }
1749 }
1750 };
1751
1752 // And VMOVCopies need to become 2xVMOVD for tail predication to be valid.
1753 // Anything other MQPRCopy can be converted to MVE_VORR later on.
1754 auto ExpandVMOVCopies = [this](SmallPtrSet<MachineInstr *, 4> &VMOVCopies) {
1755 for (auto *MI : VMOVCopies) {
1756 LLVM_DEBUG(dbgs() << "Converting copy to VMOVD: " << *MI);
1757 assert(MI->getOpcode() == ARM::MQPRCopy && "Only expected MQPRCOPY!");
1758 MachineBasicBlock *MBB = MI->getParent();
1759 Register Dst = MI->getOperand(0).getReg();
1760 Register Src = MI->getOperand(1).getReg();
1761 auto MIB1 = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::VMOVD),
1762 ARM::D0 + (Dst - ARM::Q0) * 2)
1763 .addReg(ARM::D0 + (Src - ARM::Q0) * 2)
1765 (void)MIB1;
1766 LLVM_DEBUG(dbgs() << " into " << *MIB1);
1767 auto MIB2 = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::VMOVD),
1768 ARM::D0 + (Dst - ARM::Q0) * 2 + 1)
1769 .addReg(ARM::D0 + (Src - ARM::Q0) * 2 + 1)
1771 LLVM_DEBUG(dbgs() << " and " << *MIB2);
1772 (void)MIB2;
1773 MI->eraseFromParent();
1774 }
1775 };
1776
1777 if (LoLoop.Revert) {
1778 if (isWhileLoopStart(*LoLoop.Start))
1779 RevertWhile(LoLoop.Start);
1780 else
1781 RevertDo(LoLoop.Start);
1782 if (LoLoop.Dec == LoLoop.End)
1783 RevertLoopEndDec(LoLoop.End);
1784 else
1785 RevertLoopEnd(LoLoop.End, RevertLoopDec(LoLoop.Dec));
1786 } else {
1787 ExpandVMOVCopies(LoLoop.VMOVCopies);
1788 LoLoop.Start = ExpandLoopStart(LoLoop);
1789 if (LoLoop.Start)
1790 RemoveDeadBranch(LoLoop.Start);
1791 LoLoop.End = ExpandLoopEnd(LoLoop);
1792 RemoveDeadBranch(LoLoop.End);
1793 if (LoLoop.IsTailPredicationLegal())
1794 ConvertVPTBlocks(LoLoop);
1795 for (auto *I : LoLoop.ToRemove) {
1796 LLVM_DEBUG(dbgs() << "ARM Loops: Erasing " << *I);
1797 I->eraseFromParent();
1798 }
1799 for (auto *I : LoLoop.BlockMasksToRecompute) {
1800 LLVM_DEBUG(dbgs() << "ARM Loops: Recomputing VPT/VPST Block Mask: " << *I);
1802 LLVM_DEBUG(dbgs() << " ... done: " << *I);
1803 }
1804 }
1805
1806 PostOrderLoopTraversal DFS(LoLoop.ML, *MLI);
1807 DFS.ProcessLoop();
1808 const SmallVectorImpl<MachineBasicBlock*> &PostOrder = DFS.getOrder();
1809 bool anyChange = false;
1810 do {
1811 anyChange = false;
1812 for (auto *MBB : PostOrder) {
1813 anyChange = recomputeLiveIns(*MBB) || anyChange;
1814 }
1815 } while (anyChange);
1816
1817 for (auto *MBB : reverse(PostOrder))
1819
1820 // We've moved, removed and inserted new instructions, so update RDA.
1821 RDA->reset();
1822}
1823
1824bool ARMLowOverheadLoops::RevertNonLoops() {
1825 LLVM_DEBUG(dbgs() << "ARM Loops: Reverting any remaining pseudos...\n");
1826 bool Changed = false;
1827
1828 for (auto &MBB : *MF) {
1834
1835 for (auto &I : MBB) {
1836 if (isLoopStart(I))
1837 Starts.push_back(&I);
1838 else if (I.getOpcode() == ARM::t2LoopDec)
1839 Decs.push_back(&I);
1840 else if (I.getOpcode() == ARM::t2LoopEnd)
1841 Ends.push_back(&I);
1842 else if (I.getOpcode() == ARM::t2LoopEndDec)
1843 EndDecs.push_back(&I);
1844 else if (I.getOpcode() == ARM::MQPRCopy)
1845 MQPRCopies.push_back(&I);
1846 }
1847
1848 if (Starts.empty() && Decs.empty() && Ends.empty() && EndDecs.empty() &&
1849 MQPRCopies.empty())
1850 continue;
1851
1852 Changed = true;
1853
1854 for (auto *Start : Starts) {
1855 if (isWhileLoopStart(*Start))
1856 RevertWhile(Start);
1857 else
1858 RevertDo(Start);
1859 }
1860 for (auto *Dec : Decs)
1861 RevertLoopDec(Dec);
1862
1863 for (auto *End : Ends)
1865 for (auto *End : EndDecs)
1866 RevertLoopEndDec(End);
1867 for (auto *MI : MQPRCopies) {
1868 LLVM_DEBUG(dbgs() << "Converting copy to VORR: " << *MI);
1869 assert(MI->getOpcode() == ARM::MQPRCopy && "Only expected MQPRCOPY!");
1870 MachineBasicBlock *MBB = MI->getParent();
1871 auto MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::MVE_VORR),
1872 MI->getOperand(0).getReg())
1873 .add(MI->getOperand(1))
1874 .add(MI->getOperand(1));
1875 addUnpredicatedMveVpredROp(MIB, MI->getOperand(0).getReg());
1876 MI->eraseFromParent();
1877 }
1878 }
1879 return Changed;
1880}
1881
1883 return new ARMLowOverheadLoops();
1884}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
static bool isDomainMVE(MachineInstr *MI)
SmallPtrSet< MachineInstr *, 2 > Uses
static bool isVectorPredicated(MachineInstr *MI)
ReachingDefAnalysis & RDA
static bool canGenerateNonZeros(const MachineInstr &MI)
static bool isHorizontalReduction(const MachineInstr &MI)
ReachingDefAnalysis InstSet & ToRemove
static bool producesDoubleWidthResult(const MachineInstr &MI)
static bool hasVPRUse(MachineInstr &MI)
static bool isRegInClass(const MachineOperand &MO, const TargetRegisterClass *Class)
static bool ValidateMVEStore(MachineInstr *MI, MachineLoop *ML)
static bool isVectorPredicate(MachineInstr *MI)
static bool retainsPreviousHalfElement(const MachineInstr &MI)
static bool shouldInspect(MachineInstr &MI)
static cl::opt< bool > DisableTailPredication("arm-loloops-disable-tailpred", cl::Hidden, cl::desc("Disable tail-predication in the ARM LowOverheadLoop pass"), cl::init(false))
static bool producesFalseLanesZero(MachineInstr &MI, const TargetRegisterClass *QPRs, const ReachingDefAnalysis &RDA, InstSet &FalseLanesZero)
#define DEBUG_TYPE
static int getVecSize(const MachineInstr &MI)
#define ARM_LOW_OVERHEAD_LOOPS_NAME
static cl::opt< bool > DisableOmitDLS("arm-disable-omit-dls", cl::Hidden, cl::desc("Disable omitting 'dls lr, lr' instructions"), cl::init(false))
ReachingDefAnalysis InstSet InstSet & Ignore
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate any type of IT block"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow complex IT blocks")))
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define LLVM_DEBUG(X)
Definition: Debug.h:101
bool End
Definition: ELF_riscv.cpp:480
DenseMap< Block *, BlockRelaxAux > Blocks
Definition: ELF_riscv.cpp:507
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
#define I(x, y, z)
Definition: MD5.cpp:58
static ARM::PredBlockMask CreateVPTBlock(MachineBasicBlock::instr_iterator &Iter, MachineBasicBlock::instr_iterator EndIter, SmallVectorImpl< MachineInstr * > &DeadInstructions)
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines generic set operations that may be used on set's of different types,...
This file implements a set that has insertion order iteration characteristics.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:269
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
static MCRegister from(unsigned Val)
Check the provided unsigned value is a valid MCRegister.
Definition: MCRegister.h:74
unsigned pred_size() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
iterator_range< livein_iterator > liveins() const
MachineInstr & instr_back()
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
iterator_range< succ_iterator > successors()
iterator insertAfter(iterator I, MachineInstr *MI)
Insert MI into the instruction list after I.
MachineInstrBundleIterator< MachineInstr > iterator
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:544
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:327
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:473
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:554
MachineBasicBlock * findLoopPreheader(MachineLoop *L, bool SpeculativePreheader=false, bool FindMultiLoopPreheader=false) const
Find the block that either is the loop preheader, or could speculatively be used as the preheader.
A description of a memory reference used in the backend.
MachineOperand class - Representation of each machine instruction operand.
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Register getReg() const
getReg - Returns the register number.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Special value supplied for machine level alias analysis.
This class provides the reaching def analysis.
bool isSafeToMoveForwards(MachineInstr *From, MachineInstr *To) const
Return whether From can be moved forwards to just before To.
bool isSafeToDefRegAt(MachineInstr *MI, MCRegister PhysReg) const
Return whether a MachineInstr could be inserted at MI and safely define the given register without af...
bool isSafeToRemove(MachineInstr *MI, InstSet &ToRemove) const
Return whether removing this instruction will have no effect on the program, returning the redundant ...
MachineInstr * getLocalLiveOutMIDef(MachineBasicBlock *MBB, MCRegister PhysReg) const
Return the local MI that produces the live out value for PhysReg, or nullptr for a non-live out or no...
MachineInstr * getMIOperand(MachineInstr *MI, unsigned Idx) const
If a single MachineInstr creates the reaching definition, for MIs operand at Idx, then return it.
void getReachingLocalUses(MachineInstr *MI, MCRegister PhysReg, InstSet &Uses) const
Provides the uses, in the same block as MI, of register that MI defines.
void reset()
Re-run the analysis.
bool hasLocalDefBefore(MachineInstr *MI, MCRegister PhysReg) const
Provide whether the register has been defined in the same basic block as, and before,...
bool hasSameReachingDef(MachineInstr *A, MachineInstr *B, MCRegister PhysReg) const
Return whether A and B use the same def of PhysReg.
void getGlobalUses(MachineInstr *MI, MCRegister PhysReg, InstSet &Uses) const
Collect the users of the value stored in PhysReg, which is defined by MI.
void collectKilledOperands(MachineInstr *MI, InstSet &Dead) const
Assuming MI is dead, recursively search the incoming operands which are killed by MI and collect thos...
bool isSafeToMoveBackwards(MachineInstr *From, MachineInstr *To) const
Return whether From can be moved backwards to just after To.
void getGlobalReachingDefs(MachineInstr *MI, MCRegister PhysReg, InstSet &Defs) const
Collect all possible definitions of the value stored in PhysReg, which is used by MI.
MachineInstr * getUniqueReachingMIDef(MachineInstr *MI, MCRegister PhysReg) const
If a single MachineInstr creates the reaching definition, then return it.
bool isReachingDefLiveOut(MachineInstr *MI, MCRegister PhysReg) const
Return whether the reaching def for MI also is live out of its parent block.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
Definition: Register.h:110
A vector that has set insertion semantics.
Definition: SetVector.h:57
size_type size() const
Determine the number of elements in the SetVector.
Definition: SetVector.h:98
iterator end()
Get an iterator to the end of the SetVector.
Definition: SetVector.h:113
void clear()
Completely clear the SetVector.
Definition: SetVector.h:273
iterator begin()
Get an iterator to the beginning of the SetVector.
Definition: SetVector.h:103
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:162
bool contains(const key_type &key) const
Check if the SetVector contains the given key.
Definition: SetVector.h:254
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:321
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
Definition: SmallPtrSet.h:356
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:360
iterator end() const
Definition: SmallPtrSet.h:385
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:342
iterator begin() const
Definition: SmallPtrSet.h:380
bool contains(ConstPtrType Ptr) const
Definition: SmallPtrSet.h:366
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:427
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
@ ValidForTailPredication
Definition: ARMBaseInfo.h:418
@ HorizontalReduction
Definition: ARMBaseInfo.h:425
@ RetainsPreviousHalfElement
Definition: ARMBaseInfo.h:422
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)
bool isVpred(OperandType op)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
NodeAddr< DefNode * > Def
Definition: RDFGraph.h:384
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static bool isDoLoopStart(const MachineInstr &MI)
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
int findFirstVPTPredOperandIdx(const MachineInstr &MI)
ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, Register &PredReg)
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1689
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static bool isVCTP(const MachineInstr *MI)
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
Definition: STLExtras.h:2386
static bool isVPTOpcode(int Opc)
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
Definition: STLExtras.h:2053
static unsigned getTailPredVectorWidth(unsigned Opcode)
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
FunctionPass * createARMLowOverheadLoopsPass()
static bool isMovRegOpcode(int Opc)
static bool isSubImmOpcode(int Opc)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1738
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:428
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
static bool isLoopStart(const MachineInstr &MI)
void RevertWhileLoopStartLR(MachineInstr *MI, const TargetInstrInfo *TII, unsigned BrOpc=ARM::t2Bcc, bool UseCmp=false)
void recomputeLivenessFlags(MachineBasicBlock &MBB)
Recomputes dead and kill flags in MBB.
static unsigned VCTPOpcodeToLSTP(unsigned Opcode, bool IsDoLoop)
void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg)
void RevertLoopEnd(MachineInstr *MI, const TargetInstrInfo *TII, unsigned BrOpc=ARM::t2Bcc, bool SkipCmp=false)
void RevertLoopDec(MachineInstr *MI, const TargetInstrInfo *TII, bool SetFlags=false)
MachineBasicBlock * getWhileLoopStartTargetBB(const MachineInstr &MI)
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1888
static bool isWhileLoopStart(const MachineInstr &MI)
static unsigned VCMPOpcodeToVPT(unsigned Opcode)
void RevertDoLoopStart(MachineInstr *MI, const TargetInstrInfo *TII)
int getAddSubImmediate(MachineInstr &MI)
void recomputeVPTBlockMask(MachineInstr &Instr)
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
static bool recomputeLiveIns(MachineBasicBlock &MBB)
Convenience function for recomputing live-in's for a MBB.
Definition: LivePhysRegs.h:198
Pair of physical register and lane mask.