36#define DEBUG_TYPE "riscv-opt-w-instrs"
37#define RISCV_OPT_W_INSTRS_NAME "RISC-V Optimize W Instructions"
39STATISTIC(NumRemovedSExtW,
"Number of removed sign-extensions");
41 "Number of instructions transformed to W-ops");
44 cl::desc(
"Disable removal of sext.w"),
76char RISCVOptWInstrs::ID = 0;
81 return new RISCVOptWInstrs();
102 auto NumDemandedBits =
104 return NumDemandedBits && Bits >= *NumDemandedBits;
117 Worklist.
push_back(std::make_pair(&OrigMI, OrigBits));
119 while (!Worklist.
empty()) {
122 unsigned Bits =
P.second;
128 if (
MI->getNumExplicitDefs() != 1)
131 for (
auto &UserOp :
MRI.use_operands(
MI->getOperand(0).getReg())) {
133 unsigned OpIdx = UserOp.getOperandNo();
163 case RISCV::FCVT_H_W:
164 case RISCV::FCVT_H_WU:
165 case RISCV::FCVT_S_W:
166 case RISCV::FCVT_S_WU:
167 case RISCV::FCVT_D_W:
168 case RISCV::FCVT_D_WU:
179 case RISCV::ZEXT_H_RV32:
180 case RISCV::ZEXT_H_RV64:
187 if (Bits >= (ST.getXLen() / 2))
197 Worklist.
push_back(std::make_pair(UserMI, Bits - ShAmt));
208 Worklist.
push_back(std::make_pair(UserMI, Bits));
214 Worklist.
push_back(std::make_pair(UserMI, Bits));
219 if (Bits >= (
unsigned)llvm::bit_width<uint64_t>(~Imm))
221 Worklist.
push_back(std::make_pair(UserMI, Bits));
231 if (Bits >=
Log2_32(ST.getXLen()))
235 Worklist.
push_back(std::make_pair(UserMI, Bits));
243 if (OpIdx == 2 && Bits >=
Log2_32(ST.getXLen()))
248 case RISCV::SH1ADD_UW:
249 case RISCV::SH2ADD_UW:
250 case RISCV::SH3ADD_UW:
252 if (OpIdx == 1 && Bits >= 32)
254 Worklist.
push_back(std::make_pair(UserMI, Bits));
264 if (OpIdx == 0 && Bits >= 8)
269 if (OpIdx == 0 && Bits >= 16)
274 if (OpIdx == 0 && Bits >= 32)
304 Worklist.
push_back(std::make_pair(UserMI, Bits));
307 case RISCV::PseudoCCMOVGPR:
311 if (OpIdx != 4 && OpIdx != 5)
313 Worklist.
push_back(std::make_pair(UserMI, Bits));
316 case RISCV::CZERO_EQZ:
317 case RISCV::CZERO_NEZ:
318 case RISCV::VT_MASKC:
319 case RISCV::VT_MASKCN:
322 Worklist.
push_back(std::make_pair(UserMI, Bits));
347 switch (
MI.getOpcode()) {
350 return MI.getOperand(2).getImm() >= 32;
352 return MI.getOperand(2).getImm() > 32;
355 return MI.getOperand(1).isReg() &&
MI.getOperand(1).getReg() == RISCV::X0;
358 return isUInt<11>(
MI.getOperand(2).getImm());
361 return !isUInt<11>(
MI.getOperand(2).getImm());
364 return MI.getOperand(2).getImm() < 31 &&
365 MI.getOperand(1).getReg() == RISCV::X0;
368 return MI.getOperand(1).getReg() == RISCV::X0;
369 case RISCV::PseudoAtomicLoadNand32:
383 auto AddRegDefToWorkList = [&](
Register SrcReg) {
399 if (!AddRegDefToWorkList(SrcReg))
402 while (!Worklist.
empty()) {
414 switch (
MI->getOpcode()) {
425 if (
MI->getParent() == &MF->
front()) {
431 Register CopySrcReg =
MI->getOperand(1).getReg();
432 if (CopySrcReg == RISCV::X10) {
442 auto II =
MI->getIterator();
444 (--II)->
getOpcode() != RISCV::ADJCALLSTACKUP)
456 auto *IntTy = dyn_cast<IntegerType>(CalleeFn->getReturnType());
460 const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
461 unsigned BitWidth = IntTy->getBitWidth();
462 if ((
BitWidth <= 32 && Attrs.hasAttribute(Attribute::SExt)) ||
463 (
BitWidth < 32 && Attrs.hasAttribute(Attribute::ZExt)))
467 if (!AddRegDefToWorkList(CopySrcReg))
477 if (
MI->getOperand(2).getImm() >= 31)
487 if (!AddRegDefToWorkList(
MI->getOperand(1).getReg()))
491 case RISCV::PseudoCCADDW:
492 case RISCV::PseudoCCADDIW:
493 case RISCV::PseudoCCSUBW:
494 case RISCV::PseudoCCSLLW:
495 case RISCV::PseudoCCSRLW:
496 case RISCV::PseudoCCSRAW:
497 case RISCV::PseudoCCSLLIW:
498 case RISCV::PseudoCCSRLIW:
499 case RISCV::PseudoCCSRAIW:
502 if (!AddRegDefToWorkList(
MI->getOperand(4).getReg()))
516 case RISCV::PseudoCCMOVGPR:
517 case RISCV::PseudoCCAND:
518 case RISCV::PseudoCCOR:
519 case RISCV::PseudoCCXOR:
528 unsigned B = 1,
E = 3,
D = 1;
529 switch (
MI->getOpcode()) {
531 E =
MI->getNumOperands();
534 case RISCV::PseudoCCMOVGPR:
538 case RISCV::PseudoCCAND:
539 case RISCV::PseudoCCOR:
540 case RISCV::PseudoCCXOR:
546 for (
unsigned I =
B;
I !=
E;
I +=
D) {
547 if (!
MI->getOperand(
I).isReg())
550 if (!AddRegDefToWorkList(
MI->getOperand(
I).getReg()))
557 case RISCV::CZERO_EQZ:
558 case RISCV::CZERO_NEZ:
559 case RISCV::VT_MASKC:
560 case RISCV::VT_MASKCN:
563 if (!AddRegDefToWorkList(
MI->getOperand(1).getReg()))
571 if (
MI->getOperand(2).getImm() >= 32)
620 bool MadeChange =
false;
639 if (!
MRI.constrainRegClass(SrcReg,
MRI.getRegClass(DstReg)))
645 Fixable->setDesc(
TII.get(
getWOp(Fixable->getOpcode())));
646 Fixable->clearFlag(MachineInstr::MIFlag::NoSWrap);
647 Fixable->clearFlag(MachineInstr::MIFlag::NoUWrap);
648 Fixable->clearFlag(MachineInstr::MIFlag::IsExact);
650 ++NumTransformedToWInstrs;
654 MRI.replaceRegWith(DstReg, SrcReg);
655 MRI.clearKillFlags(SrcReg);
656 MI.eraseFromParent();
672 bool MadeChange =
false;
676 switch (
MI.getOpcode()) {
679 case RISCV::ADDW: Opc = RISCV::ADD;
break;
680 case RISCV::ADDIW: Opc = RISCV::ADDI;
break;
681 case RISCV::MULW: Opc = RISCV::MUL;
break;
682 case RISCV::SLLIW: Opc = RISCV::SLLI;
break;
686 MI.setDesc(
TII.get(Opc));
706 bool MadeChange =
false;
707 MadeChange |= removeSExtWInstrs(MF,
TII, ST,
MRI);
708 MadeChange |= stripWSuffixes(MF,
TII, ST,
MRI);
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const HexagonInstrInfo * TII
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static bool isSignExtendingOpW(const MachineInstr &MI, const MachineRegisterInfo &MRI)
static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI, SmallPtrSetImpl< MachineInstr * > &FixableDef)
static bool hasAllWUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI)
static cl::opt< bool > DisableStripWSuffix("riscv-disable-strip-w-suffix", cl::desc("Disable strip W suffix"), cl::init(false), cl::Hidden)
static bool hasAllNBitUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI, unsigned OrigBits)
#define RISCV_OPT_W_INSTRS_NAME
static bool vectorPseudoHasAllNBitUsers(const MachineOperand &UserOp, unsigned Bits)
static cl::opt< bool > DisableSExtWRemoval("riscv-disable-sextw-removal", cl::desc("Disable removal of sext.w"), cl::init(false), cl::Hidden)
static unsigned getWOp(unsigned Opcode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
static constexpr uint32_t Opcode
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
Describe properties that are true of each instruction in the target description file.
instr_iterator instr_begin()
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
bool isCall(QueryType Type=AnyInBundle) const
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool isLiveIn(Register Reg) const
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
bool isSExt32Register(Register Reg) const
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool hasVLOp(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
std::optional< unsigned > getVectorLowDemandedScalarBits(uint16_t Opcode, unsigned Log2SEW)
unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode)
bool isSEXT_W(const MachineInstr &MI)
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
FunctionPass * createRISCVOptWInstrsPass()
void initializeRISCVOptWInstrsPass(PassRegistry &)
constexpr unsigned BitWidth