31#define DEBUG_TYPE "riscv-opt-w-instrs"
32#define RISCV_OPT_W_INSTRS_NAME "RISC-V Optimize W Instructions"
34STATISTIC(NumRemovedSExtW,
"Number of removed sign-extensions");
36 "Number of instructions transformed to W-ops");
39 cl::desc(
"Disable removal of sext.w"),
71char RISCVOptWInstrs::ID = 0;
76 return new RISCVOptWInstrs();
89 Worklist.
push_back(std::make_pair(&OrigMI, OrigBits));
91 while (!Worklist.
empty()) {
94 unsigned Bits =
P.second;
100 if (
MI->getNumExplicitDefs() != 1)
103 for (
auto &UserOp :
MRI.use_operands(
MI->getOperand(0).getReg())) {
105 unsigned OpIdx = UserOp.getOperandNo();
133 case RISCV::FCVT_H_W:
134 case RISCV::FCVT_H_WU:
135 case RISCV::FCVT_S_W:
136 case RISCV::FCVT_S_WU:
137 case RISCV::FCVT_D_W:
138 case RISCV::FCVT_D_WU:
149 case RISCV::ZEXT_H_RV32:
150 case RISCV::ZEXT_H_RV64:
157 if (Bits >= (ST.getXLen() / 2))
167 Worklist.
push_back(std::make_pair(UserMI, Bits - ShAmt));
178 Worklist.
push_back(std::make_pair(UserMI, Bits));
184 Worklist.
push_back(std::make_pair(UserMI, Bits));
189 if (Bits >= (
unsigned)llvm::bit_width<uint64_t>(~Imm))
191 Worklist.
push_back(std::make_pair(UserMI, Bits));
201 if (Bits >=
Log2_32(ST.getXLen()))
205 Worklist.
push_back(std::make_pair(UserMI, Bits));
213 if (OpIdx == 2 && Bits >=
Log2_32(ST.getXLen()))
218 case RISCV::SH1ADD_UW:
219 case RISCV::SH2ADD_UW:
220 case RISCV::SH3ADD_UW:
222 if (OpIdx == 1 && Bits >= 32)
224 Worklist.
push_back(std::make_pair(UserMI, Bits));
234 if (OpIdx == 0 && Bits >= 8)
239 if (OpIdx == 0 && Bits >= 16)
244 if (OpIdx == 0 && Bits >= 32)
274 Worklist.
push_back(std::make_pair(UserMI, Bits));
277 case RISCV::PseudoCCMOVGPR:
281 if (OpIdx != 4 && OpIdx != 5)
283 Worklist.
push_back(std::make_pair(UserMI, Bits));
286 case RISCV::VT_MASKC:
287 case RISCV::VT_MASKCN:
290 Worklist.
push_back(std::make_pair(UserMI, Bits));
315 switch (
MI.getOpcode()) {
318 return MI.getOperand(2).getImm() >= 32;
320 return MI.getOperand(2).getImm() > 32;
323 return MI.getOperand(1).isReg() &&
MI.getOperand(1).getReg() == RISCV::X0;
326 return isUInt<11>(
MI.getOperand(2).getImm());
329 return !isUInt<11>(
MI.getOperand(2).getImm());
332 return MI.getOperand(1).getReg() == RISCV::X0;
345 auto AddRegDefToWorkList = [&](
Register SrcReg) {
356 if (!AddRegDefToWorkList(SrcReg))
359 while (!Worklist.
empty()) {
371 switch (
MI->getOpcode()) {
382 if (
MI->getParent() == &MF->
front()) {
388 Register CopySrcReg =
MI->getOperand(1).getReg();
389 if (CopySrcReg == RISCV::X10) {
399 auto II =
MI->getIterator();
401 (--II)->
getOpcode() != RISCV::ADJCALLSTACKUP)
413 auto *IntTy = dyn_cast<IntegerType>(CalleeFn->getReturnType());
417 const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
418 unsigned BitWidth = IntTy->getBitWidth();
419 if ((
BitWidth <= 32 && Attrs.hasAttribute(Attribute::SExt)) ||
420 (
BitWidth < 32 && Attrs.hasAttribute(Attribute::ZExt)))
424 if (!AddRegDefToWorkList(CopySrcReg))
434 if (
MI->getOperand(2).getImm() >= 31)
444 if (!AddRegDefToWorkList(
MI->getOperand(1).getReg()))
448 case RISCV::PseudoCCADDW:
449 case RISCV::PseudoCCSUBW:
452 if (!AddRegDefToWorkList(
MI->getOperand(4).getReg()))
466 case RISCV::PseudoCCMOVGPR:
467 case RISCV::PseudoCCAND:
468 case RISCV::PseudoCCOR:
469 case RISCV::PseudoCCXOR:
478 unsigned B = 1,
E = 3,
D = 1;
479 switch (
MI->getOpcode()) {
481 E =
MI->getNumOperands();
484 case RISCV::PseudoCCMOVGPR:
488 case RISCV::PseudoCCAND:
489 case RISCV::PseudoCCOR:
490 case RISCV::PseudoCCXOR:
496 for (
unsigned I =
B;
I !=
E;
I +=
D) {
497 if (!
MI->getOperand(
I).isReg())
500 if (!AddRegDefToWorkList(
MI->getOperand(
I).getReg()))
507 case RISCV::VT_MASKC:
508 case RISCV::VT_MASKCN:
511 if (!AddRegDefToWorkList(
MI->getOperand(1).getReg()))
519 if (
MI->getOperand(2).getImm() >= 32)
568 bool MadeChange =
false;
589 if (!
MRI.constrainRegClass(SrcReg,
MRI.getRegClass(DstReg)))
595 Fixable->setDesc(
TII.get(
getWOp(Fixable->getOpcode())));
596 Fixable->clearFlag(MachineInstr::MIFlag::NoSWrap);
597 Fixable->clearFlag(MachineInstr::MIFlag::NoUWrap);
598 Fixable->clearFlag(MachineInstr::MIFlag::IsExact);
600 ++NumTransformedToWInstrs;
604 MRI.replaceRegWith(DstReg, SrcReg);
605 MRI.clearKillFlags(SrcReg);
606 MI->eraseFromParent();
622 bool MadeChange =
false;
628 switch (
MI.getOpcode()) {
631 case RISCV::ADDW: Opc = RISCV::ADD;
break;
632 case RISCV::MULW: Opc = RISCV::MUL;
break;
633 case RISCV::SLLIW: Opc = RISCV::SLLI;
break;
637 MI.setDesc(
TII.get(Opc));
657 bool MadeChange =
false;
658 MadeChange |= removeSExtWInstrs(MF,
TII, ST,
MRI);
659 MadeChange |= stripWSuffixes(MF,
TII, ST,
MRI);
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const HexagonInstrInfo * TII
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static bool isSignExtendingOpW(const MachineInstr &MI, const MachineRegisterInfo &MRI)
static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI, SmallPtrSetImpl< MachineInstr * > &FixableDef)
static bool hasAllWUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI)
static cl::opt< bool > DisableStripWSuffix("riscv-disable-strip-w-suffix", cl::desc("Disable strip W suffix"), cl::init(false), cl::Hidden)
static bool hasAllNBitUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI, unsigned OrigBits)
#define RISCV_OPT_W_INSTRS_NAME
static cl::opt< bool > DisableSExtWRemoval("riscv-disable-sextw-removal", cl::desc("Disable removal of sext.w"), cl::init(false), cl::Hidden)
static unsigned getWOp(unsigned Opcode)
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
instr_iterator instr_begin()
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
bool isCall(QueryType Type=AnyInBundle) const
const MachineOperand & getOperand(unsigned i) const
const GlobalValue * getGlobal() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool isLiveIn(Register Reg) const
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
bool isSExt32Register(Register Reg) const
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isSEXT_W(const MachineInstr &MI)
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
FunctionPass * createRISCVOptWInstrsPass()
void initializeRISCVOptWInstrsPass(PassRegistry &)
constexpr unsigned BitWidth