LLVM 18.0.0git
RISCVOptWInstrs.cpp
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1//===- RISCVOptWInstrs.cpp - MI W instruction optimizations ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===---------------------------------------------------------------------===//
8//
9// This pass does some optimizations for *W instructions at the MI level.
10//
11// First it removes unneeded sext.w instructions. Either because the sign
12// extended bits aren't consumed or because the input was already sign extended
13// by an earlier instruction.
14//
15// Then it removes the -w suffix from opw instructions whenever all users are
16// dependent only on the lower word of the result of the instruction.
17// The cases handled are:
18// * addw because c.add has a larger register encoding than c.addw.
19// * addiw because it helps reduce test differences between RV32 and RV64
20// w/o being a pessimization.
21// * mulw because c.mulw doesn't exist but c.mul does (w/ zcb)
22// * slliw because c.slliw doesn't exist and c.slli does
23//
24//===---------------------------------------------------------------------===//
25
26#include "RISCV.h"
28#include "RISCVSubtarget.h"
29#include "llvm/ADT/SmallSet.h"
30#include "llvm/ADT/Statistic.h"
33
34using namespace llvm;
35
36#define DEBUG_TYPE "riscv-opt-w-instrs"
37#define RISCV_OPT_W_INSTRS_NAME "RISC-V Optimize W Instructions"
38
39STATISTIC(NumRemovedSExtW, "Number of removed sign-extensions");
40STATISTIC(NumTransformedToWInstrs,
41 "Number of instructions transformed to W-ops");
42
43static cl::opt<bool> DisableSExtWRemoval("riscv-disable-sextw-removal",
44 cl::desc("Disable removal of sext.w"),
45 cl::init(false), cl::Hidden);
46static cl::opt<bool> DisableStripWSuffix("riscv-disable-strip-w-suffix",
47 cl::desc("Disable strip W suffix"),
48 cl::init(false), cl::Hidden);
49
50namespace {
51
52class RISCVOptWInstrs : public MachineFunctionPass {
53public:
54 static char ID;
55
56 RISCVOptWInstrs() : MachineFunctionPass(ID) {
58 }
59
60 bool runOnMachineFunction(MachineFunction &MF) override;
61 bool removeSExtWInstrs(MachineFunction &MF, const RISCVInstrInfo &TII,
63 bool stripWSuffixes(MachineFunction &MF, const RISCVInstrInfo &TII,
65
66 void getAnalysisUsage(AnalysisUsage &AU) const override {
67 AU.setPreservesCFG();
69 }
70
71 StringRef getPassName() const override { return RISCV_OPT_W_INSTRS_NAME; }
72};
73
74} // end anonymous namespace
75
76char RISCVOptWInstrs::ID = 0;
78 false)
79
81 return new RISCVOptWInstrs();
82}
83
85 unsigned Bits) {
86 const MachineInstr &MI = *UserOp.getParent();
87 unsigned MCOpcode = RISCV::getRVVMCOpcode(MI.getOpcode());
88
89 if (!MCOpcode)
90 return false;
91
92 const MCInstrDesc &MCID = MI.getDesc();
93 const uint64_t TSFlags = MCID.TSFlags;
95 return false;
97 const unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MCID)).getImm();
98
99 if (UserOp.getOperandNo() == RISCVII::getVLOpNum(MCID))
100 return false;
101
102 auto NumDemandedBits =
104 return NumDemandedBits && Bits >= *NumDemandedBits;
105}
106
107// Checks if all users only demand the lower \p OrigBits of the original
108// instruction's result.
109// TODO: handle multiple interdependent transformations
110static bool hasAllNBitUsers(const MachineInstr &OrigMI,
111 const RISCVSubtarget &ST,
112 const MachineRegisterInfo &MRI, unsigned OrigBits) {
113
116
117 Worklist.push_back(std::make_pair(&OrigMI, OrigBits));
118
119 while (!Worklist.empty()) {
120 auto P = Worklist.pop_back_val();
121 const MachineInstr *MI = P.first;
122 unsigned Bits = P.second;
123
124 if (!Visited.insert(P).second)
125 continue;
126
127 // Only handle instructions with one def.
128 if (MI->getNumExplicitDefs() != 1)
129 return false;
130
131 for (auto &UserOp : MRI.use_operands(MI->getOperand(0).getReg())) {
132 const MachineInstr *UserMI = UserOp.getParent();
133 unsigned OpIdx = UserOp.getOperandNo();
134
135 switch (UserMI->getOpcode()) {
136 default:
137 if (vectorPseudoHasAllNBitUsers(UserOp, Bits))
138 break;
139 return false;
140
141 case RISCV::ADDIW:
142 case RISCV::ADDW:
143 case RISCV::DIVUW:
144 case RISCV::DIVW:
145 case RISCV::MULW:
146 case RISCV::REMUW:
147 case RISCV::REMW:
148 case RISCV::SLLIW:
149 case RISCV::SLLW:
150 case RISCV::SRAIW:
151 case RISCV::SRAW:
152 case RISCV::SRLIW:
153 case RISCV::SRLW:
154 case RISCV::SUBW:
155 case RISCV::ROLW:
156 case RISCV::RORW:
157 case RISCV::RORIW:
158 case RISCV::CLZW:
159 case RISCV::CTZW:
160 case RISCV::CPOPW:
161 case RISCV::SLLI_UW:
162 case RISCV::FMV_W_X:
163 case RISCV::FCVT_H_W:
164 case RISCV::FCVT_H_WU:
165 case RISCV::FCVT_S_W:
166 case RISCV::FCVT_S_WU:
167 case RISCV::FCVT_D_W:
168 case RISCV::FCVT_D_WU:
169 if (Bits >= 32)
170 break;
171 return false;
172 case RISCV::SEXT_B:
173 case RISCV::PACKH:
174 if (Bits >= 8)
175 break;
176 return false;
177 case RISCV::SEXT_H:
178 case RISCV::FMV_H_X:
179 case RISCV::ZEXT_H_RV32:
180 case RISCV::ZEXT_H_RV64:
181 case RISCV::PACKW:
182 if (Bits >= 16)
183 break;
184 return false;
185
186 case RISCV::PACK:
187 if (Bits >= (ST.getXLen() / 2))
188 break;
189 return false;
190
191 case RISCV::SRLI: {
192 // If we are shifting right by less than Bits, and users don't demand
193 // any bits that were shifted into [Bits-1:0], then we can consider this
194 // as an N-Bit user.
195 unsigned ShAmt = UserMI->getOperand(2).getImm();
196 if (Bits > ShAmt) {
197 Worklist.push_back(std::make_pair(UserMI, Bits - ShAmt));
198 break;
199 }
200 return false;
201 }
202
203 // these overwrite higher input bits, otherwise the lower word of output
204 // depends only on the lower word of input. So check their uses read W.
205 case RISCV::SLLI:
206 if (Bits >= (ST.getXLen() - UserMI->getOperand(2).getImm()))
207 break;
208 Worklist.push_back(std::make_pair(UserMI, Bits));
209 break;
210 case RISCV::ANDI: {
211 uint64_t Imm = UserMI->getOperand(2).getImm();
212 if (Bits >= (unsigned)llvm::bit_width(Imm))
213 break;
214 Worklist.push_back(std::make_pair(UserMI, Bits));
215 break;
216 }
217 case RISCV::ORI: {
218 uint64_t Imm = UserMI->getOperand(2).getImm();
219 if (Bits >= (unsigned)llvm::bit_width<uint64_t>(~Imm))
220 break;
221 Worklist.push_back(std::make_pair(UserMI, Bits));
222 break;
223 }
224
225 case RISCV::SLL:
226 case RISCV::BSET:
227 case RISCV::BCLR:
228 case RISCV::BINV:
229 // Operand 2 is the shift amount which uses log2(xlen) bits.
230 if (OpIdx == 2) {
231 if (Bits >= Log2_32(ST.getXLen()))
232 break;
233 return false;
234 }
235 Worklist.push_back(std::make_pair(UserMI, Bits));
236 break;
237
238 case RISCV::SRA:
239 case RISCV::SRL:
240 case RISCV::ROL:
241 case RISCV::ROR:
242 // Operand 2 is the shift amount which uses 6 bits.
243 if (OpIdx == 2 && Bits >= Log2_32(ST.getXLen()))
244 break;
245 return false;
246
247 case RISCV::ADD_UW:
248 case RISCV::SH1ADD_UW:
249 case RISCV::SH2ADD_UW:
250 case RISCV::SH3ADD_UW:
251 // Operand 1 is implicitly zero extended.
252 if (OpIdx == 1 && Bits >= 32)
253 break;
254 Worklist.push_back(std::make_pair(UserMI, Bits));
255 break;
256
257 case RISCV::BEXTI:
258 if (UserMI->getOperand(2).getImm() >= Bits)
259 return false;
260 break;
261
262 case RISCV::SB:
263 // The first argument is the value to store.
264 if (OpIdx == 0 && Bits >= 8)
265 break;
266 return false;
267 case RISCV::SH:
268 // The first argument is the value to store.
269 if (OpIdx == 0 && Bits >= 16)
270 break;
271 return false;
272 case RISCV::SW:
273 // The first argument is the value to store.
274 if (OpIdx == 0 && Bits >= 32)
275 break;
276 return false;
277
278 // For these, lower word of output in these operations, depends only on
279 // the lower word of input. So, we check all uses only read lower word.
280 case RISCV::COPY:
281 case RISCV::PHI:
282
283 case RISCV::ADD:
284 case RISCV::ADDI:
285 case RISCV::AND:
286 case RISCV::MUL:
287 case RISCV::OR:
288 case RISCV::SUB:
289 case RISCV::XOR:
290 case RISCV::XORI:
291
292 case RISCV::ANDN:
293 case RISCV::BREV8:
294 case RISCV::CLMUL:
295 case RISCV::ORC_B:
296 case RISCV::ORN:
297 case RISCV::SH1ADD:
298 case RISCV::SH2ADD:
299 case RISCV::SH3ADD:
300 case RISCV::XNOR:
301 case RISCV::BSETI:
302 case RISCV::BCLRI:
303 case RISCV::BINVI:
304 Worklist.push_back(std::make_pair(UserMI, Bits));
305 break;
306
307 case RISCV::PseudoCCMOVGPR:
308 // Either operand 4 or operand 5 is returned by this instruction. If
309 // only the lower word of the result is used, then only the lower word
310 // of operand 4 and 5 is used.
311 if (OpIdx != 4 && OpIdx != 5)
312 return false;
313 Worklist.push_back(std::make_pair(UserMI, Bits));
314 break;
315
316 case RISCV::CZERO_EQZ:
317 case RISCV::CZERO_NEZ:
318 case RISCV::VT_MASKC:
319 case RISCV::VT_MASKCN:
320 if (OpIdx != 1)
321 return false;
322 Worklist.push_back(std::make_pair(UserMI, Bits));
323 break;
324 }
325 }
326 }
327
328 return true;
329}
330
331static bool hasAllWUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST,
332 const MachineRegisterInfo &MRI) {
333 return hasAllNBitUsers(OrigMI, ST, MRI, 32);
334}
335
336// This function returns true if the machine instruction always outputs a value
337// where bits 63:32 match bit 31.
339 const MachineRegisterInfo &MRI) {
340 uint64_t TSFlags = MI.getDesc().TSFlags;
341
342 // Instructions that can be determined from opcode are marked in tablegen.
344 return true;
345
346 // Special cases that require checking operands.
347 switch (MI.getOpcode()) {
348 // shifting right sufficiently makes the value 32-bit sign-extended
349 case RISCV::SRAI:
350 return MI.getOperand(2).getImm() >= 32;
351 case RISCV::SRLI:
352 return MI.getOperand(2).getImm() > 32;
353 // The LI pattern ADDI rd, X0, imm is sign extended.
354 case RISCV::ADDI:
355 return MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0;
356 // An ANDI with an 11 bit immediate will zero bits 63:11.
357 case RISCV::ANDI:
358 return isUInt<11>(MI.getOperand(2).getImm());
359 // An ORI with an >11 bit immediate (negative 12-bit) will set bits 63:11.
360 case RISCV::ORI:
361 return !isUInt<11>(MI.getOperand(2).getImm());
362 // A bseti with X0 is sign extended if the immediate is less than 31.
363 case RISCV::BSETI:
364 return MI.getOperand(2).getImm() < 31 &&
365 MI.getOperand(1).getReg() == RISCV::X0;
366 // Copying from X0 produces zero.
367 case RISCV::COPY:
368 return MI.getOperand(1).getReg() == RISCV::X0;
369 case RISCV::PseudoAtomicLoadNand32:
370 return true;
371 }
372
373 return false;
374}
375
376static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
379
382
383 auto AddRegDefToWorkList = [&](Register SrcReg) {
384 if (!SrcReg.isVirtual())
385 return false;
386 MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
387 if (!SrcMI)
388 return false;
389 // Code assumes the register is operand 0.
390 // TODO: Maybe the worklist should store register?
391 if (!SrcMI->getOperand(0).isReg() ||
392 SrcMI->getOperand(0).getReg() != SrcReg)
393 return false;
394 // Add SrcMI to the worklist.
395 Worklist.push_back(SrcMI);
396 return true;
397 };
398
399 if (!AddRegDefToWorkList(SrcReg))
400 return false;
401
402 while (!Worklist.empty()) {
403 MachineInstr *MI = Worklist.pop_back_val();
404
405 // If we already visited this instruction, we don't need to check it again.
406 if (!Visited.insert(MI).second)
407 continue;
408
409 // If this is a sign extending operation we don't need to look any further.
411 continue;
412
413 // Is this an instruction that propagates sign extend?
414 switch (MI->getOpcode()) {
415 default:
416 // Unknown opcode, give up.
417 return false;
418 case RISCV::COPY: {
419 const MachineFunction *MF = MI->getMF();
420 const RISCVMachineFunctionInfo *RVFI =
422
423 // If this is the entry block and the register is livein, see if we know
424 // it is sign extended.
425 if (MI->getParent() == &MF->front()) {
426 Register VReg = MI->getOperand(0).getReg();
427 if (MF->getRegInfo().isLiveIn(VReg) && RVFI->isSExt32Register(VReg))
428 continue;
429 }
430
431 Register CopySrcReg = MI->getOperand(1).getReg();
432 if (CopySrcReg == RISCV::X10) {
433 // For a method return value, we check the ZExt/SExt flags in attribute.
434 // We assume the following code sequence for method call.
435 // PseudoCALL @bar, ...
436 // ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
437 // %0:gpr = COPY $x10
438 //
439 // We use the PseudoCall to look up the IR function being called to find
440 // its return attributes.
441 const MachineBasicBlock *MBB = MI->getParent();
442 auto II = MI->getIterator();
443 if (II == MBB->instr_begin() ||
444 (--II)->getOpcode() != RISCV::ADJCALLSTACKUP)
445 return false;
446
447 const MachineInstr &CallMI = *(--II);
448 if (!CallMI.isCall() || !CallMI.getOperand(0).isGlobal())
449 return false;
450
451 auto *CalleeFn =
452 dyn_cast_if_present<Function>(CallMI.getOperand(0).getGlobal());
453 if (!CalleeFn)
454 return false;
455
456 auto *IntTy = dyn_cast<IntegerType>(CalleeFn->getReturnType());
457 if (!IntTy)
458 return false;
459
460 const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
461 unsigned BitWidth = IntTy->getBitWidth();
462 if ((BitWidth <= 32 && Attrs.hasAttribute(Attribute::SExt)) ||
463 (BitWidth < 32 && Attrs.hasAttribute(Attribute::ZExt)))
464 continue;
465 }
466
467 if (!AddRegDefToWorkList(CopySrcReg))
468 return false;
469
470 break;
471 }
472
473 // For these, we just need to check if the 1st operand is sign extended.
474 case RISCV::BCLRI:
475 case RISCV::BINVI:
476 case RISCV::BSETI:
477 if (MI->getOperand(2).getImm() >= 31)
478 return false;
479 [[fallthrough]];
480 case RISCV::REM:
481 case RISCV::ANDI:
482 case RISCV::ORI:
483 case RISCV::XORI:
484 // |Remainder| is always <= |Dividend|. If D is 32-bit, then so is R.
485 // DIV doesn't work because of the edge case 0xf..f 8000 0000 / (long)-1
486 // Logical operations use a sign extended 12-bit immediate.
487 if (!AddRegDefToWorkList(MI->getOperand(1).getReg()))
488 return false;
489
490 break;
491 case RISCV::PseudoCCADDW:
492 case RISCV::PseudoCCADDIW:
493 case RISCV::PseudoCCSUBW:
494 case RISCV::PseudoCCSLLW:
495 case RISCV::PseudoCCSRLW:
496 case RISCV::PseudoCCSRAW:
497 case RISCV::PseudoCCSLLIW:
498 case RISCV::PseudoCCSRLIW:
499 case RISCV::PseudoCCSRAIW:
500 // Returns operand 4 or an ADDW/SUBW/etc. of operands 5 and 6. We only
501 // need to check if operand 4 is sign extended.
502 if (!AddRegDefToWorkList(MI->getOperand(4).getReg()))
503 return false;
504 break;
505 case RISCV::REMU:
506 case RISCV::AND:
507 case RISCV::OR:
508 case RISCV::XOR:
509 case RISCV::ANDN:
510 case RISCV::ORN:
511 case RISCV::XNOR:
512 case RISCV::MAX:
513 case RISCV::MAXU:
514 case RISCV::MIN:
515 case RISCV::MINU:
516 case RISCV::PseudoCCMOVGPR:
517 case RISCV::PseudoCCAND:
518 case RISCV::PseudoCCOR:
519 case RISCV::PseudoCCXOR:
520 case RISCV::PHI: {
521 // If all incoming values are sign-extended, the output of AND, OR, XOR,
522 // MIN, MAX, or PHI is also sign-extended.
523
524 // The input registers for PHI are operand 1, 3, ...
525 // The input registers for PseudoCCMOVGPR are 4 and 5.
526 // The input registers for PseudoCCAND/OR/XOR are 4, 5, and 6.
527 // The input registers for others are operand 1 and 2.
528 unsigned B = 1, E = 3, D = 1;
529 switch (MI->getOpcode()) {
530 case RISCV::PHI:
531 E = MI->getNumOperands();
532 D = 2;
533 break;
534 case RISCV::PseudoCCMOVGPR:
535 B = 4;
536 E = 6;
537 break;
538 case RISCV::PseudoCCAND:
539 case RISCV::PseudoCCOR:
540 case RISCV::PseudoCCXOR:
541 B = 4;
542 E = 7;
543 break;
544 }
545
546 for (unsigned I = B; I != E; I += D) {
547 if (!MI->getOperand(I).isReg())
548 return false;
549
550 if (!AddRegDefToWorkList(MI->getOperand(I).getReg()))
551 return false;
552 }
553
554 break;
555 }
556
557 case RISCV::CZERO_EQZ:
558 case RISCV::CZERO_NEZ:
559 case RISCV::VT_MASKC:
560 case RISCV::VT_MASKCN:
561 // Instructions return zero or operand 1. Result is sign extended if
562 // operand 1 is sign extended.
563 if (!AddRegDefToWorkList(MI->getOperand(1).getReg()))
564 return false;
565 break;
566
567 // With these opcode, we can "fix" them with the W-version
568 // if we know all users of the result only rely on bits 31:0
569 case RISCV::SLLI:
570 // SLLIW reads the lowest 5 bits, while SLLI reads lowest 6 bits
571 if (MI->getOperand(2).getImm() >= 32)
572 return false;
573 [[fallthrough]];
574 case RISCV::ADDI:
575 case RISCV::ADD:
576 case RISCV::LD:
577 case RISCV::LWU:
578 case RISCV::MUL:
579 case RISCV::SUB:
580 if (hasAllWUsers(*MI, ST, MRI)) {
581 FixableDef.insert(MI);
582 break;
583 }
584 return false;
585 }
586 }
587
588 // If we get here, then every node we visited produces a sign extended value
589 // or propagated sign extended values. So the result must be sign extended.
590 return true;
591}
592
593static unsigned getWOp(unsigned Opcode) {
594 switch (Opcode) {
595 case RISCV::ADDI:
596 return RISCV::ADDIW;
597 case RISCV::ADD:
598 return RISCV::ADDW;
599 case RISCV::LD:
600 case RISCV::LWU:
601 return RISCV::LW;
602 case RISCV::MUL:
603 return RISCV::MULW;
604 case RISCV::SLLI:
605 return RISCV::SLLIW;
606 case RISCV::SUB:
607 return RISCV::SUBW;
608 default:
609 llvm_unreachable("Unexpected opcode for replacement with W variant");
610 }
611}
612
613bool RISCVOptWInstrs::removeSExtWInstrs(MachineFunction &MF,
614 const RISCVInstrInfo &TII,
615 const RISCVSubtarget &ST,
618 return false;
619
620 bool MadeChange = false;
621 for (MachineBasicBlock &MBB : MF) {
623 // We're looking for the sext.w pattern ADDIW rd, rs1, 0.
624 if (!RISCV::isSEXT_W(MI))
625 continue;
626
627 Register SrcReg = MI.getOperand(1).getReg();
628
630
631 // If all users only use the lower bits, this sext.w is redundant.
632 // Or if all definitions reaching MI sign-extend their output,
633 // then sext.w is redundant.
634 if (!hasAllWUsers(MI, ST, MRI) &&
635 !isSignExtendedW(SrcReg, ST, MRI, FixableDefs))
636 continue;
637
638 Register DstReg = MI.getOperand(0).getReg();
639 if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
640 continue;
641
642 // Convert Fixable instructions to their W versions.
643 for (MachineInstr *Fixable : FixableDefs) {
644 LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
645 Fixable->setDesc(TII.get(getWOp(Fixable->getOpcode())));
646 Fixable->clearFlag(MachineInstr::MIFlag::NoSWrap);
647 Fixable->clearFlag(MachineInstr::MIFlag::NoUWrap);
648 Fixable->clearFlag(MachineInstr::MIFlag::IsExact);
649 LLVM_DEBUG(dbgs() << " with " << *Fixable);
650 ++NumTransformedToWInstrs;
651 }
652
653 LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
654 MRI.replaceRegWith(DstReg, SrcReg);
655 MRI.clearKillFlags(SrcReg);
656 MI.eraseFromParent();
657 ++NumRemovedSExtW;
658 MadeChange = true;
659 }
660 }
661
662 return MadeChange;
663}
664
665bool RISCVOptWInstrs::stripWSuffixes(MachineFunction &MF,
666 const RISCVInstrInfo &TII,
667 const RISCVSubtarget &ST,
670 return false;
671
672 bool MadeChange = false;
673 for (MachineBasicBlock &MBB : MF) {
674 for (MachineInstr &MI : MBB) {
675 unsigned Opc;
676 switch (MI.getOpcode()) {
677 default:
678 continue;
679 case RISCV::ADDW: Opc = RISCV::ADD; break;
680 case RISCV::ADDIW: Opc = RISCV::ADDI; break;
681 case RISCV::MULW: Opc = RISCV::MUL; break;
682 case RISCV::SLLIW: Opc = RISCV::SLLI; break;
683 }
684
685 if (hasAllWUsers(MI, ST, MRI)) {
686 MI.setDesc(TII.get(Opc));
687 MadeChange = true;
688 }
689 }
690 }
691
692 return MadeChange;
693}
694
695bool RISCVOptWInstrs::runOnMachineFunction(MachineFunction &MF) {
696 if (skipFunction(MF.getFunction()))
697 return false;
698
701 const RISCVInstrInfo &TII = *ST.getInstrInfo();
702
703 if (!ST.is64Bit())
704 return false;
705
706 bool MadeChange = false;
707 MadeChange |= removeSExtWInstrs(MF, TII, ST, MRI);
708 MadeChange |= stripWSuffixes(MF, TII, ST, MRI);
709
710 return MadeChange;
711}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DEBUG(X)
Definition: Debug.h:101
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
#define P(N)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
unsigned Log2SEW
uint64_t TSFlags
static bool isSignExtendingOpW(const MachineInstr &MI, const MachineRegisterInfo &MRI)
static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI, SmallPtrSetImpl< MachineInstr * > &FixableDef)
static bool hasAllWUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI)
static cl::opt< bool > DisableStripWSuffix("riscv-disable-strip-w-suffix", cl::desc("Disable strip W suffix"), cl::init(false), cl::Hidden)
static bool hasAllNBitUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI, unsigned OrigBits)
#define RISCV_OPT_W_INSTRS_NAME
static bool vectorPseudoHasAllNBitUsers(const MachineOperand &UserOp, unsigned Bits)
static cl::opt< bool > DisableSExtWRemoval("riscv-disable-sextw-removal", cl::desc("Disable removal of sext.w"), cl::init(false), cl::Hidden)
#define DEBUG_TYPE
static unsigned getWOp(unsigned Opcode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
Definition: VPlanSLP.cpp:191
static constexpr uint32_t Opcode
Definition: aarch32.h:200
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:269
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
instr_iterator instr_begin()
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:543
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:326
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:915
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:553
MachineOperand class - Representation of each machine instruction operand.
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
const GlobalValue * getGlobal() const
int64_t getImm() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool isLiveIn(Register Reg) const
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
bool isSExt32Register(Register Reg) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:345
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:366
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:451
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:179
bool empty() const
Definition: SmallVector.h:94
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool hasVLOp(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
std::optional< unsigned > getVectorLowDemandedScalarBits(uint16_t Opcode, unsigned Log2SEW)
unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode)
bool isSEXT_W(const MachineInstr &MI)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
Definition: bit.h:316
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:665
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:313
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
FunctionPass * createRISCVOptWInstrsPass()
void initializeRISCVOptWInstrsPass(PassRegistry &)
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:191