LLVM  9.0.0svn
AArch64RegisterInfo.cpp
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1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64RegisterInfo.h"
15 #include "AArch64FrameLowering.h"
16 #include "AArch64InstrInfo.h"
18 #include "AArch64Subtarget.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/Triple.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/DiagnosticInfo.h"
31 
32 using namespace llvm;
33 
34 #define GET_REGINFO_TARGET_DESC
35 #include "AArch64GenRegisterInfo.inc"
36 
38  : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
40 }
41 
42 const MCPhysReg *
44  assert(MF && "Invalid MachineFunction pointer.");
46  return CSR_Win_AArch64_AAPCS_SaveList;
48  // GHC set of callee saved regs is empty as all those regs are
49  // used for passing STG regs around
50  return CSR_AArch64_NoRegs_SaveList;
52  return CSR_AArch64_AllRegs_SaveList;
54  return CSR_AArch64_AAVPCS_SaveList;
56  return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
57  CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
58  CSR_AArch64_CXX_TLS_Darwin_SaveList;
60  ->supportSwiftError() &&
62  Attribute::SwiftError))
63  return CSR_AArch64_AAPCS_SwiftError_SaveList;
65  return CSR_AArch64_RT_MostRegs_SaveList;
66  else
67  return CSR_AArch64_AAPCS_SaveList;
68 }
69 
71  const MachineFunction *MF) const {
72  assert(MF && "Invalid MachineFunction pointer.");
74  MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
75  return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
76  return nullptr;
77 }
78 
80  MachineFunction &MF) const {
81  const MCPhysReg *CSRs = getCalleeSavedRegs(&MF);
82  SmallVector<MCPhysReg, 32> UpdatedCSRs;
83  for (const MCPhysReg *I = CSRs; *I; ++I)
84  UpdatedCSRs.push_back(*I);
85 
86  for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
88  UpdatedCSRs.push_back(AArch64::GPR64commonRegClass.getRegister(i));
89  }
90  }
91  // Register lists are zero-terminated.
92  UpdatedCSRs.push_back(0);
93  MF.getRegInfo().setCalleeSavedRegs(UpdatedCSRs);
94 }
95 
96 const TargetRegisterClass *
98  unsigned Idx) const {
99  // edge case for GPR/FPR register classes
100  if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub)
101  return &AArch64::FPR32RegClass;
102  else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub)
103  return &AArch64::FPR64RegClass;
104 
105  // Forward to TableGen's default version.
106  return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
107 }
108 
109 const uint32_t *
111  CallingConv::ID CC) const {
112  bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
113  if (CC == CallingConv::GHC)
114  // This is academic because all GHC calls are (supposed to be) tail calls
115  return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask;
116  if (CC == CallingConv::AnyReg)
117  return SCS ? CSR_AArch64_AllRegs_SCS_RegMask : CSR_AArch64_AllRegs_RegMask;
118  if (CC == CallingConv::CXX_FAST_TLS)
119  return SCS ? CSR_AArch64_CXX_TLS_Darwin_SCS_RegMask
120  : CSR_AArch64_CXX_TLS_Darwin_RegMask;
122  return SCS ? CSR_AArch64_AAVPCS_SCS_RegMask : CSR_AArch64_AAVPCS_RegMask;
124  ->supportSwiftError() &&
125  MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
126  return SCS ? CSR_AArch64_AAPCS_SwiftError_SCS_RegMask
127  : CSR_AArch64_AAPCS_SwiftError_RegMask;
128  if (CC == CallingConv::PreserveMost)
129  return SCS ? CSR_AArch64_RT_MostRegs_SCS_RegMask
130  : CSR_AArch64_RT_MostRegs_RegMask;
131  else
132  return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
133 }
134 
136  if (TT.isOSDarwin())
137  return CSR_AArch64_TLS_Darwin_RegMask;
138 
139  assert(TT.isOSBinFormatELF() && "Invalid target");
140  return CSR_AArch64_TLS_ELF_RegMask;
141 }
142 
144  const uint32_t **Mask) const {
145  uint32_t *UpdatedMask = MF.allocateRegMask();
146  unsigned RegMaskSize = MachineOperand::getRegMaskSize(getNumRegs());
147  memcpy(UpdatedMask, *Mask, sizeof(UpdatedMask[0]) * RegMaskSize);
148 
149  for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
151  for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i),
152  this, true);
153  SubReg.isValid(); ++SubReg) {
154  // See TargetRegisterInfo::getCallPreservedMask for how to interpret the
155  // register mask.
156  UpdatedMask[*SubReg / 32] |= 1u << (*SubReg % 32);
157  }
158  }
159  }
160  *Mask = UpdatedMask;
161 }
162 
164  return CSR_AArch64_NoRegs_RegMask;
165 }
166 
167 const uint32_t *
169  CallingConv::ID CC) const {
170  // This should return a register mask that is the same as that returned by
171  // getCallPreservedMask but that additionally preserves the register used for
172  // the first i64 argument (which must also be the register used to return a
173  // single i64 return value)
174  //
175  // In case that the calling convention does not use the same register for
176  // both, the function should return NULL (does not currently apply)
177  assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
178  return CSR_AArch64_AAPCS_ThisReturn_RegMask;
179 }
180 
182  return CSR_AArch64_StackProbe_Windows_RegMask;
183 }
184 
185 BitVector
187  const AArch64FrameLowering *TFI = getFrameLowering(MF);
188 
189  // FIXME: avoid re-calculating this every time.
190  BitVector Reserved(getNumRegs());
191  markSuperRegs(Reserved, AArch64::WSP);
192  markSuperRegs(Reserved, AArch64::WZR);
193 
194  if (TFI->hasFP(MF) || TT.isOSDarwin())
195  markSuperRegs(Reserved, AArch64::W29);
196 
197  for (size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) {
199  markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(i));
200  }
201 
202  if (hasBasePointer(MF))
203  markSuperRegs(Reserved, AArch64::W19);
204 
205  // SLH uses register W16/X16 as the taint register.
206  if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening))
207  markSuperRegs(Reserved, AArch64::W16);
208 
209  assert(checkAllSuperRegsMarked(Reserved));
210  return Reserved;
211 }
212 
214  unsigned Reg) const {
215  return getReservedRegs(MF)[Reg];
216 }
217 
219  return std::any_of(std::begin(*AArch64::GPR64argRegClass.MC),
220  std::end(*AArch64::GPR64argRegClass.MC),
221  [this, &MF](MCPhysReg r){return isReservedReg(MF, r);});
222 }
223 
225  const MachineFunction &MF) const {
226  const Function &F = MF.getFunction();
227  F.getContext().diagnose(DiagnosticInfoUnsupported{F, "AArch64 doesn't support"
228  " function calls if any of the argument registers is reserved."});
229 }
230 
232  unsigned PhysReg) const {
233  return !isReservedReg(MF, PhysReg);
234 }
235 
236 bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
237  return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
238 }
239 
240 const TargetRegisterClass *
242  unsigned Kind) const {
243  return &AArch64::GPR64spRegClass;
244 }
245 
246 const TargetRegisterClass *
248  if (RC == &AArch64::CCRRegClass)
249  return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
250  return RC;
251 }
252 
253 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
254 
256  const MachineFrameInfo &MFI = MF.getFrameInfo();
257 
258  // In the presence of variable sized objects or funclets, if the fixed stack
259  // size is large enough that referencing from the FP won't result in things
260  // being in range relatively often, we can use a base pointer to allow access
261  // from the other direction like the SP normally works.
262  //
263  // Furthermore, if both variable sized objects are present, and the
264  // stack needs to be dynamically re-aligned, the base pointer is the only
265  // reliable way to reference the locals.
266  if (MFI.hasVarSizedObjects() || MF.hasEHFunclets()) {
267  if (needsStackRealignment(MF))
268  return true;
269  // Conservatively estimate whether the negative offset from the frame
270  // pointer will be sufficient to reach. If a function has a smallish
271  // frame, it's less likely to have lots of spills and callee saved
272  // space, so it's all more likely to be within range of the frame pointer.
273  // If it's wrong, we'll materialize the constant and still get to the
274  // object; it's just suboptimal. Negative offsets use the unscaled
275  // load/store instructions, which have a 9-bit signed immediate.
276  return MFI.getLocalFrameSize() >= 256;
277  }
278 
279  return false;
280 }
281 
282 unsigned
284  const AArch64FrameLowering *TFI = getFrameLowering(MF);
285  return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
286 }
287 
289  const MachineFunction &MF) const {
290  return true;
291 }
292 
294  const MachineFunction &MF) const {
295  return true;
296 }
297 
298 bool
300  // This function indicates whether the emergency spillslot should be placed
301  // close to the beginning of the stackframe (closer to FP) or the end
302  // (closer to SP).
303  //
304  // The beginning works most reliably if we have a frame pointer.
305  const AArch64FrameLowering &TFI = *getFrameLowering(MF);
306  return TFI.hasFP(MF);
307 }
308 
310  const MachineFunction &MF) const {
311  return true;
312 }
313 
314 bool
316  const MachineFrameInfo &MFI = MF.getFrameInfo();
318  return true;
319  return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
320 }
321 
322 /// needsFrameBaseReg - Returns true if the instruction's frame index
323 /// reference would be better served by a base register other than FP
324 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
325 /// references it should create new base registers for.
327  int64_t Offset) const {
328  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
329  assert(i < MI->getNumOperands() &&
330  "Instr doesn't have FrameIndex operand!");
331 
332  // It's the load/store FI references that cause issues, as it can be difficult
333  // to materialize the offset if it won't fit in the literal field. Estimate
334  // based on the size of the local frame and some conservative assumptions
335  // about the rest of the stack frame (note, this is pre-regalloc, so
336  // we don't know everything for certain yet) whether this offset is likely
337  // to be out of range of the immediate. Return true if so.
338 
339  // We only generate virtual base registers for loads and stores, so
340  // return false for everything else.
341  if (!MI->mayLoad() && !MI->mayStore())
342  return false;
343 
344  // Without a virtual base register, if the function has variable sized
345  // objects, all fixed-size local references will be via the frame pointer,
346  // Approximate the offset and see if it's legal for the instruction.
347  // Note that the incoming offset is based on the SP value at function entry,
348  // so it'll be negative.
349  MachineFunction &MF = *MI->getParent()->getParent();
350  const AArch64FrameLowering *TFI = getFrameLowering(MF);
351  MachineFrameInfo &MFI = MF.getFrameInfo();
352 
353  // Estimate an offset from the frame pointer.
354  // Conservatively assume all GPR callee-saved registers get pushed.
355  // FP, LR, X19-X28, D8-D15. 64-bits each.
356  int64_t FPOffset = Offset - 16 * 20;
357  // Estimate an offset from the stack pointer.
358  // The incoming offset is relating to the SP at the start of the function,
359  // but when we access the local it'll be relative to the SP after local
360  // allocation, so adjust our SP-relative offset by that allocation size.
361  Offset += MFI.getLocalFrameSize();
362  // Assume that we'll have at least some spill slots allocated.
363  // FIXME: This is a total SWAG number. We should run some statistics
364  // and pick a real one.
365  Offset += 128; // 128 bytes of spill slots
366 
367  // If there is a frame pointer, try using it.
368  // The FP is only available if there is no dynamic realignment. We
369  // don't know for sure yet whether we'll need that, so we guess based
370  // on whether there are any local variables that would trigger it.
371  if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
372  return false;
373 
374  // If we can reference via the stack pointer or base pointer, try that.
375  // FIXME: This (and the code that resolves the references) can be improved
376  // to only disallow SP relative references in the live range of
377  // the VLA(s). In practice, it's unclear how much difference that
378  // would make, but it may be worth doing.
379  if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
380  return false;
381 
382  // The offset likely isn't legal; we want to allocate a virtual base register.
383  return true;
384 }
385 
387  unsigned BaseReg,
388  int64_t Offset) const {
389  assert(Offset <= INT_MAX && "Offset too big to fit in int.");
390  assert(MI && "Unable to get the legal offset for nil instruction.");
391  int SaveOffset = Offset;
392  return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
393 }
394 
395 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
396 /// at the beginning of the basic block.
398  unsigned BaseReg,
399  int FrameIdx,
400  int64_t Offset) const {
402  DebugLoc DL; // Defaults to "unknown"
403  if (Ins != MBB->end())
404  DL = Ins->getDebugLoc();
405  const MachineFunction &MF = *MBB->getParent();
406  const AArch64InstrInfo *TII =
407  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
408  const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
410  MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
411  unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
412 
413  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
414  .addFrameIndex(FrameIdx)
415  .addImm(Offset)
416  .addImm(Shifter);
417 }
418 
420  int64_t Offset) const {
421  int Off = Offset; // ARM doesn't need the general 64-bit offsets
422  unsigned i = 0;
423 
424  while (!MI.getOperand(i).isFI()) {
425  ++i;
426  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
427  }
428  const MachineFunction *MF = MI.getParent()->getParent();
429  const AArch64InstrInfo *TII =
430  MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
431  bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
432  assert(Done && "Unable to resolve frame index!");
433  (void)Done;
434 }
435 
437  int SPAdj, unsigned FIOperandNum,
438  RegScavenger *RS) const {
439  assert(SPAdj == 0 && "Unexpected");
440 
441  MachineInstr &MI = *II;
442  MachineBasicBlock &MBB = *MI.getParent();
443  MachineFunction &MF = *MBB.getParent();
444  const AArch64InstrInfo *TII =
445  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
446  const AArch64FrameLowering *TFI = getFrameLowering(MF);
447 
448  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
449  unsigned FrameReg;
450  int Offset;
451 
452  // Special handling of dbg_value, stackmap and patchpoint instructions.
453  if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
454  MI.getOpcode() == TargetOpcode::PATCHPOINT) {
455  Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
456  /*PreferFP=*/true);
457  Offset += MI.getOperand(FIOperandNum + 1).getImm();
458  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
459  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
460  return;
461  }
462 
463  if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) {
464  MachineOperand &FI = MI.getOperand(FIOperandNum);
465  Offset = TFI->getNonLocalFrameIndexReference(MF, FrameIndex);
466  FI.ChangeToImmediate(Offset);
467  return;
468  }
469 
470  // Modify MI as necessary to handle as much of 'Offset' as possible
471  Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg);
472 
473  if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
474  return;
475 
476  assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
477  "Emergency spill slot is out of reach");
478 
479  // If we get here, the immediate doesn't fit into the instruction. We folded
480  // as much as possible above. Handle the rest, providing a register that is
481  // SP+LargeImm.
482  unsigned ScratchReg =
483  MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
484  emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
485  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
486 }
487 
489  MachineFunction &MF) const {
490  const AArch64FrameLowering *TFI = getFrameLowering(MF);
491 
492  switch (RC->getID()) {
493  default:
494  return 0;
495  case AArch64::GPR32RegClassID:
496  case AArch64::GPR32spRegClassID:
497  case AArch64::GPR32allRegClassID:
498  case AArch64::GPR64spRegClassID:
499  case AArch64::GPR64allRegClassID:
500  case AArch64::GPR64RegClassID:
501  case AArch64::GPR32commonRegClassID:
502  case AArch64::GPR64commonRegClassID:
503  return 32 - 1 // XZR/SP
504  - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
506  - hasBasePointer(MF); // X19
507  case AArch64::FPR8RegClassID:
508  case AArch64::FPR16RegClassID:
509  case AArch64::FPR32RegClassID:
510  case AArch64::FPR64RegClassID:
511  case AArch64::FPR128RegClassID:
512  return 32;
513 
514  case AArch64::DDRegClassID:
515  case AArch64::DDDRegClassID:
516  case AArch64::DDDDRegClassID:
517  case AArch64::QQRegClassID:
518  case AArch64::QQQRegClassID:
519  case AArch64::QQQQRegClassID:
520  return 32;
521 
522  case AArch64::FPR128_loRegClassID:
523  return 16;
524  }
525 }
526 
528  const MachineFunction &MF) const {
529  const auto &MFI = MF.getFrameInfo();
530  if (!MF.hasEHFunclets() && !MFI.hasVarSizedObjects())
531  return AArch64::SP;
532  else if (needsStackRealignment(MF))
533  return getBaseRegister();
534  return getFrameRegister(MF);
535 }
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:480
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Diagnostic information for unsupported feature in backend.
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:618
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
bool cannotEliminateFrame(const MachineFunction &MF) const
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
int64_t getLocalFrameSize() const
Get the size of the local object blob.
unsigned Reg
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
A debug info location.
Definition: DebugLoc.h:33
F(f)
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool isAnyArgRegReserved(const MachineFunction &MF) const
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
unsigned SubReg
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - Provide a base+offset reference to an FI slot for debug info.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
unsigned getID() const
Return the register class ID number.
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
const uint32_t * getNoPreservedMask() const override
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
AArch64RegisterInfo(const Triple &TT)
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
bool isXRegisterReserved(size_t i) const
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
int getNonLocalFrameIndexReference(const MachineFunction &MF, int FI) const override
getNonLocalFrameIndexReference - This method returns the offset used to reference a frame index locat...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const AArch64TargetLowering * getTargetLowering() const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:821
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool hasEHFunclets() const
int resolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP=false) const
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1199
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that &#39;returned&#39; is on...
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
MCSubRegIterator enumerates all sub-registers of Reg.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
bool isDebugValue() const
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
uint32_t * allocateRegMask()
Allocate and initialize a register mask with NumRegister bits.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
unsigned getNumXRegisterReserved() const
void UpdateCustomCallPreservedMask(MachineFunction &MF, const uint32_t **Mask) const
const uint32_t * getWindowsStackProbePreservedMask() const
Stack probing calls preserve different CSRs to the normal CC.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
BitVector getReservedRegs(const MachineFunction &MF) const override
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
void emitReservedArgRegCallError(const MachineFunction &MF) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getLocalAddressRegister(const MachineFunction &MF) const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetOptions Options
#define I(x, y, z)
Definition: MD5.cpp:58
bool useFPForScavengingIndex(const MachineFunction &MF) const override
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
const uint32_t * getTLSCallPreservedMask() const
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:808
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isConstantPhysReg(unsigned PhysReg) const override
bool hasBasePointer(const MachineFunction &MF) const
bool isXRegCustomCalleeSaved(size_t i) const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction&#39;s frame index reference would be better served by...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
bool isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) const override
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...