LLVM 18.0.0git
AArch64RegisterInfo.cpp
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1//===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AArch64 implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AArch64RegisterInfo.h"
16#include "AArch64InstrInfo.h"
18#include "AArch64Subtarget.h"
21#include "llvm/ADT/BitVector.h"
30#include "llvm/IR/Function.h"
34
35using namespace llvm;
36
37#define GET_CC_REGISTER_LISTS
38#include "AArch64GenCallingConv.inc"
39#define GET_REGINFO_TARGET_DESC
40#include "AArch64GenRegisterInfo.inc"
41
43 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
45}
46
47/// Return whether the register needs a CFI entry. Not all unwinders may know
48/// about SVE registers, so we assume the lowest common denominator, i.e. the
49/// callee-saves required by the base ABI. For the SVE registers z8-z15 only the
50/// lower 64-bits (d8-d15) need to be saved. The lower 64-bits subreg is
51/// returned in \p RegToUseForCFI.
53 unsigned &RegToUseForCFI) const {
54 if (AArch64::PPRRegClass.contains(Reg))
55 return false;
56
57 if (AArch64::ZPRRegClass.contains(Reg)) {
58 RegToUseForCFI = getSubReg(Reg, AArch64::dsub);
59 for (int I = 0; CSR_AArch64_AAPCS_SaveList[I]; ++I) {
60 if (CSR_AArch64_AAPCS_SaveList[I] == RegToUseForCFI)
61 return true;
62 }
63 return false;
64 }
65
66 RegToUseForCFI = Reg;
67 return true;
68}
69
70const MCPhysReg *
72 assert(MF && "Invalid MachineFunction pointer.");
73
75 // GHC set of callee saved regs is empty as all those regs are
76 // used for passing STG regs around
77 return CSR_AArch64_NoRegs_SaveList;
79 return CSR_AArch64_AllRegs_SaveList;
80
81 // Darwin has its own CSR_AArch64_AAPCS_SaveList, which means most CSR save
82 // lists depending on that will need to have their Darwin variant as well.
84 return getDarwinCalleeSavedRegs(MF);
85
87 return CSR_Win_AArch64_CFGuard_Check_SaveList;
92 Attribute::SwiftError))
93 return CSR_Win_AArch64_AAPCS_SwiftError_SaveList;
95 return CSR_Win_AArch64_AAPCS_SwiftTail_SaveList;
96 return CSR_Win_AArch64_AAPCS_SaveList;
97 }
99 return CSR_AArch64_AAVPCS_SaveList;
101 return CSR_AArch64_SVE_AAPCS_SaveList;
102 if (MF->getFunction().getCallingConv() ==
105 "Calling convention AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0 is "
106 "only supported to improve calls to SME ACLE save/restore/disable-za "
107 "functions, and is not intended to be used beyond that scope.");
108 if (MF->getFunction().getCallingConv() ==
111 "Calling convention AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2 is "
112 "only supported to improve calls to SME ACLE __arm_sme_state "
113 "and is not intended to be used beyond that scope.");
115 ->supportSwiftError() &&
117 Attribute::SwiftError))
118 return CSR_AArch64_AAPCS_SwiftError_SaveList;
120 return CSR_AArch64_AAPCS_SwiftTail_SaveList;
122 return CSR_AArch64_RT_MostRegs_SaveList;
124 return CSR_AArch64_RT_AllRegs_SaveList;
126 // This is for OSes other than Windows; Windows is a separate case further
127 // above.
128 return CSR_AArch64_AAPCS_X18_SaveList;
129 if (MF->getInfo<AArch64FunctionInfo>()->isSVECC())
130 return CSR_AArch64_SVE_AAPCS_SaveList;
131 return CSR_AArch64_AAPCS_SaveList;
132}
133
134const MCPhysReg *
136 assert(MF && "Invalid MachineFunction pointer.");
138 "Invalid subtarget for getDarwinCalleeSavedRegs");
139
142 "Calling convention CFGuard_Check is unsupported on Darwin.");
144 return CSR_Darwin_AArch64_AAVPCS_SaveList;
147 "Calling convention SVE_VectorCall is unsupported on Darwin.");
148 if (MF->getFunction().getCallingConv() ==
151 "Calling convention AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0 is "
152 "only supported to improve calls to SME ACLE save/restore/disable-za "
153 "functions, and is not intended to be used beyond that scope.");
154 if (MF->getFunction().getCallingConv() ==
157 "Calling convention AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2 is "
158 "only supported to improve calls to SME ACLE __arm_sme_state "
159 "and is not intended to be used beyond that scope.");
161 return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR()
162 ? CSR_Darwin_AArch64_CXX_TLS_PE_SaveList
163 : CSR_Darwin_AArch64_CXX_TLS_SaveList;
165 ->supportSwiftError() &&
167 Attribute::SwiftError))
168 return CSR_Darwin_AArch64_AAPCS_SwiftError_SaveList;
170 return CSR_Darwin_AArch64_AAPCS_SwiftTail_SaveList;
172 return CSR_Darwin_AArch64_RT_MostRegs_SaveList;
174 return CSR_Darwin_AArch64_RT_AllRegs_SaveList;
176 return CSR_Darwin_AArch64_AAPCS_Win64_SaveList;
177 return CSR_Darwin_AArch64_AAPCS_SaveList;
178}
179
181 const MachineFunction *MF) const {
182 assert(MF && "Invalid MachineFunction pointer.");
185 return CSR_Darwin_AArch64_CXX_TLS_ViaCopy_SaveList;
186 return nullptr;
187}
188
190 MachineFunction &MF) const {
191 const MCPhysReg *CSRs = getCalleeSavedRegs(&MF);
192 SmallVector<MCPhysReg, 32> UpdatedCSRs;
193 for (const MCPhysReg *I = CSRs; *I; ++I)
194 UpdatedCSRs.push_back(*I);
195
196 for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
198 UpdatedCSRs.push_back(AArch64::GPR64commonRegClass.getRegister(i));
199 }
200 }
201 // Register lists are zero-terminated.
202 UpdatedCSRs.push_back(0);
203 MF.getRegInfo().setCalleeSavedRegs(UpdatedCSRs);
204}
205
208 unsigned Idx) const {
209 // edge case for GPR/FPR register classes
210 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub)
211 return &AArch64::FPR32RegClass;
212 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub)
213 return &AArch64::FPR64RegClass;
214
215 // Forward to TableGen's default version.
216 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
217}
218
219const uint32_t *
221 CallingConv::ID CC) const {
223 "Invalid subtarget for getDarwinCallPreservedMask");
224
226 return CSR_Darwin_AArch64_CXX_TLS_RegMask;
228 return CSR_Darwin_AArch64_AAVPCS_RegMask;
231 "Calling convention SVE_VectorCall is unsupported on Darwin.");
234 "Calling convention AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0 is "
235 "unsupported on Darwin.");
238 "Calling convention AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2 is "
239 "unsupported on Darwin.");
242 "Calling convention CFGuard_Check is unsupported on Darwin.");
245 ->supportSwiftError() &&
246 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
247 return CSR_Darwin_AArch64_AAPCS_SwiftError_RegMask;
249 return CSR_Darwin_AArch64_AAPCS_SwiftTail_RegMask;
251 return CSR_Darwin_AArch64_RT_MostRegs_RegMask;
253 return CSR_Darwin_AArch64_RT_AllRegs_RegMask;
254 return CSR_Darwin_AArch64_AAPCS_RegMask;
255}
256
257const uint32_t *
259 CallingConv::ID CC) const {
260 bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
261 if (CC == CallingConv::GHC)
262 // This is academic because all GHC calls are (supposed to be) tail calls
263 return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask;
264 if (CC == CallingConv::AnyReg)
265 return SCS ? CSR_AArch64_AllRegs_SCS_RegMask : CSR_AArch64_AllRegs_RegMask;
266
267 // All the following calling conventions are handled differently on Darwin.
269 if (SCS)
270 report_fatal_error("ShadowCallStack attribute not supported on Darwin.");
271 return getDarwinCallPreservedMask(MF, CC);
272 }
273
275 return SCS ? CSR_AArch64_AAVPCS_SCS_RegMask : CSR_AArch64_AAVPCS_RegMask;
277 return SCS ? CSR_AArch64_SVE_AAPCS_SCS_RegMask
278 : CSR_AArch64_SVE_AAPCS_RegMask;
280 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0_RegMask;
282 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2_RegMask;
284 return CSR_Win_AArch64_CFGuard_Check_RegMask;
286 ->supportSwiftError() &&
287 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
288 return SCS ? CSR_AArch64_AAPCS_SwiftError_SCS_RegMask
289 : CSR_AArch64_AAPCS_SwiftError_RegMask;
290 if (CC == CallingConv::SwiftTail) {
291 if (SCS)
292 report_fatal_error("ShadowCallStack attribute not supported with swifttail");
293 return CSR_AArch64_AAPCS_SwiftTail_RegMask;
294 }
296 return SCS ? CSR_AArch64_RT_MostRegs_SCS_RegMask
297 : CSR_AArch64_RT_MostRegs_RegMask;
298 else if (CC == CallingConv::PreserveAll)
299 return SCS ? CSR_AArch64_RT_AllRegs_SCS_RegMask
300 : CSR_AArch64_RT_AllRegs_RegMask;
301
302 else
303 return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
304}
305
307 const MachineFunction &MF) const {
309 return CSR_AArch64_AAPCS_RegMask;
310
311 return nullptr;
312}
313
315 if (TT.isOSDarwin())
316 return CSR_Darwin_AArch64_TLS_RegMask;
317
318 assert(TT.isOSBinFormatELF() && "Invalid target");
319 return CSR_AArch64_TLS_ELF_RegMask;
320}
321
323 const uint32_t **Mask) const {
324 uint32_t *UpdatedMask = MF.allocateRegMask();
325 unsigned RegMaskSize = MachineOperand::getRegMaskSize(getNumRegs());
326 memcpy(UpdatedMask, *Mask, sizeof(UpdatedMask[0]) * RegMaskSize);
327
328 for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
330 for (MCPhysReg SubReg :
331 subregs_inclusive(AArch64::GPR64commonRegClass.getRegister(i))) {
332 // See TargetRegisterInfo::getCallPreservedMask for how to interpret the
333 // register mask.
334 UpdatedMask[SubReg / 32] |= 1u << (SubReg % 32);
335 }
336 }
337 }
338 *Mask = UpdatedMask;
339}
340
342 return CSR_AArch64_SMStartStop_RegMask;
343}
344
345const uint32_t *
347 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0_RegMask;
348}
349
351 return CSR_AArch64_NoRegs_RegMask;
352}
353
354const uint32_t *
356 CallingConv::ID CC) const {
357 // This should return a register mask that is the same as that returned by
358 // getCallPreservedMask but that additionally preserves the register used for
359 // the first i64 argument (which must also be the register used to return a
360 // single i64 return value)
361 //
362 // In case that the calling convention does not use the same register for
363 // both, the function should return NULL (does not currently apply)
364 assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
366 return CSR_Darwin_AArch64_AAPCS_ThisReturn_RegMask;
367 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
368}
369
371 return CSR_AArch64_StackProbe_Windows_RegMask;
372}
373
374std::optional<std::string>
376 MCRegister PhysReg) const {
377 if (hasBasePointer(MF) && MCRegisterInfo::regsOverlap(PhysReg, AArch64::X19))
378 return std::string("X19 is used as the frame base pointer register.");
379
381 bool warn = false;
382 if (MCRegisterInfo::regsOverlap(PhysReg, AArch64::X13) ||
383 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X14) ||
384 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X23) ||
385 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X24) ||
386 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X28))
387 warn = true;
388
389 for (unsigned i = AArch64::B16; i <= AArch64::B31; ++i)
390 if (MCRegisterInfo::regsOverlap(PhysReg, i))
391 warn = true;
392
393 if (warn)
394 return std::string(AArch64InstPrinter::getRegisterName(PhysReg)) +
395 " is clobbered by asynchronous signals when using Arm64EC.";
396 }
397
398 return {};
399}
400
403 const AArch64FrameLowering *TFI = getFrameLowering(MF);
404
405 // FIXME: avoid re-calculating this every time.
406 BitVector Reserved(getNumRegs());
407 markSuperRegs(Reserved, AArch64::WSP);
408 markSuperRegs(Reserved, AArch64::WZR);
409
410 if (TFI->hasFP(MF) || TT.isOSDarwin())
411 markSuperRegs(Reserved, AArch64::W29);
412
414 // x13, x14, x23, x24, x28, and v16-v31 are clobbered by asynchronous
415 // signals, so we can't ever use them.
416 markSuperRegs(Reserved, AArch64::W13);
417 markSuperRegs(Reserved, AArch64::W14);
418 markSuperRegs(Reserved, AArch64::W23);
419 markSuperRegs(Reserved, AArch64::W24);
420 markSuperRegs(Reserved, AArch64::W28);
421 for (unsigned i = AArch64::B16; i <= AArch64::B31; ++i)
422 markSuperRegs(Reserved, i);
423 }
424
425 for (size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) {
427 markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(i));
428 }
429
430 if (hasBasePointer(MF))
431 markSuperRegs(Reserved, AArch64::W19);
432
433 // SLH uses register W16/X16 as the taint register.
434 if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening))
435 markSuperRegs(Reserved, AArch64::W16);
436
437 // SME tiles are not allocatable.
438 if (MF.getSubtarget<AArch64Subtarget>().hasSME()) {
439 for (MCPhysReg SubReg : subregs_inclusive(AArch64::ZA))
440 Reserved.set(SubReg);
441 }
442
443 markSuperRegs(Reserved, AArch64::FPCR);
444
445 assert(checkAllSuperRegsMarked(Reserved));
446 return Reserved;
447}
448
452
453 for (size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) {
455 markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(i));
456 }
457
458 assert(checkAllSuperRegsMarked(Reserved));
459 return Reserved;
460}
461
463 MCRegister Reg) const {
464 return getReservedRegs(MF)[Reg];
465}
466
468 MCRegister Reg) const {
469 return getStrictlyReservedRegs(MF)[Reg];
470}
471
473 return llvm::any_of(*AArch64::GPR64argRegClass.MC, [this, &MF](MCPhysReg r) {
474 return isStrictlyReservedReg(MF, r);
475 });
476}
477
479 const MachineFunction &MF) const {
480 const Function &F = MF.getFunction();
481 F.getContext().diagnose(DiagnosticInfoUnsupported{F, ("AArch64 doesn't support"
482 " function calls if any of the argument registers is reserved.")});
483}
484
486 MCRegister PhysReg) const {
487 // SLH uses register X16 as the taint register but it will fallback to a different
488 // method if the user clobbers it. So X16 is not reserved for inline asm but is
489 // for normal codegen.
490 if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening) &&
491 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X16))
492 return true;
493
494 return !isReservedReg(MF, PhysReg);
495}
496
499 unsigned Kind) const {
500 return &AArch64::GPR64spRegClass;
501}
502
505 if (RC == &AArch64::CCRRegClass)
506 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
507 return RC;
508}
509
510unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
511
513 const MachineFrameInfo &MFI = MF.getFrameInfo();
514
515 // In the presence of variable sized objects or funclets, if the fixed stack
516 // size is large enough that referencing from the FP won't result in things
517 // being in range relatively often, we can use a base pointer to allow access
518 // from the other direction like the SP normally works.
519 //
520 // Furthermore, if both variable sized objects are present, and the
521 // stack needs to be dynamically re-aligned, the base pointer is the only
522 // reliable way to reference the locals.
523 if (MFI.hasVarSizedObjects() || MF.hasEHFunclets()) {
524 if (hasStackRealignment(MF))
525 return true;
526
527 if (MF.getSubtarget<AArch64Subtarget>().hasSVE()) {
529 // Frames that have variable sized objects and scalable SVE objects,
530 // should always use a basepointer.
531 if (!AFI->hasCalculatedStackSizeSVE() || AFI->getStackSizeSVE())
532 return true;
533 }
534
535 // Conservatively estimate whether the negative offset from the frame
536 // pointer will be sufficient to reach. If a function has a smallish
537 // frame, it's less likely to have lots of spills and callee saved
538 // space, so it's all more likely to be within range of the frame pointer.
539 // If it's wrong, we'll materialize the constant and still get to the
540 // object; it's just suboptimal. Negative offsets use the unscaled
541 // load/store instructions, which have a 9-bit signed immediate.
542 return MFI.getLocalFrameSize() >= 256;
543 }
544
545 return false;
546}
547
549 MCRegister Reg) const {
552 bool IsVarArg = STI.isCallingConvWin64(MF.getFunction().getCallingConv());
553
554 auto HasReg = [](ArrayRef<MCRegister> RegList, MCRegister Reg) {
555 return llvm::is_contained(RegList, Reg);
556 };
557
558 switch (CC) {
559 default:
560 report_fatal_error("Unsupported calling convention.");
562 return HasReg(CC_AArch64_WebKit_JS_ArgRegs, Reg);
563 case CallingConv::GHC:
564 return HasReg(CC_AArch64_GHC_ArgRegs, Reg);
565 case CallingConv::C:
573 if (STI.isTargetWindows() && IsVarArg)
574 return HasReg(CC_AArch64_Win64_VarArg_ArgRegs, Reg);
575 if (!STI.isTargetDarwin()) {
576 switch (CC) {
577 default:
578 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg);
581 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg) ||
582 HasReg(CC_AArch64_AAPCS_Swift_ArgRegs, Reg);
583 }
584 }
585 if (!IsVarArg) {
586 switch (CC) {
587 default:
588 return HasReg(CC_AArch64_DarwinPCS_ArgRegs, Reg);
591 return HasReg(CC_AArch64_DarwinPCS_ArgRegs, Reg) ||
592 HasReg(CC_AArch64_DarwinPCS_Swift_ArgRegs, Reg);
593 }
594 }
595 if (STI.isTargetILP32())
596 return HasReg(CC_AArch64_DarwinPCS_ILP32_VarArg_ArgRegs, Reg);
597 return HasReg(CC_AArch64_DarwinPCS_VarArg_ArgRegs, Reg);
599 if (IsVarArg)
600 HasReg(CC_AArch64_Win64_VarArg_ArgRegs, Reg);
601 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg);
603 return HasReg(CC_AArch64_Win64_CFGuard_Check_ArgRegs, Reg);
608 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg);
609 }
610}
611
614 const AArch64FrameLowering *TFI = getFrameLowering(MF);
615 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
616}
617
619 const MachineFunction &MF) const {
620 return true;
621}
622
624 const MachineFunction &MF) const {
625 return true;
626}
627
628bool
630 // This function indicates whether the emergency spillslot should be placed
631 // close to the beginning of the stackframe (closer to FP) or the end
632 // (closer to SP).
633 //
634 // The beginning works most reliably if we have a frame pointer.
635 // In the presence of any non-constant space between FP and locals,
636 // (e.g. in case of stack realignment or a scalable SVE area), it is
637 // better to use SP or BP.
638 const AArch64FrameLowering &TFI = *getFrameLowering(MF);
640 assert((!MF.getSubtarget<AArch64Subtarget>().hasSVE() ||
642 "Expected SVE area to be calculated by this point");
643 return TFI.hasFP(MF) && !hasStackRealignment(MF) && !AFI->getStackSizeSVE();
644}
645
647 const MachineFunction &MF) const {
648 return true;
649}
650
651bool
653 const MachineFrameInfo &MFI = MF.getFrameInfo();
655 return true;
656 return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
657}
658
659/// needsFrameBaseReg - Returns true if the instruction's frame index
660/// reference would be better served by a base register other than FP
661/// or SP. Used by LocalStackFrameAllocation to determine which frame index
662/// references it should create new base registers for.
664 int64_t Offset) const {
665 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
666 assert(i < MI->getNumOperands() &&
667 "Instr doesn't have FrameIndex operand!");
668
669 // It's the load/store FI references that cause issues, as it can be difficult
670 // to materialize the offset if it won't fit in the literal field. Estimate
671 // based on the size of the local frame and some conservative assumptions
672 // about the rest of the stack frame (note, this is pre-regalloc, so
673 // we don't know everything for certain yet) whether this offset is likely
674 // to be out of range of the immediate. Return true if so.
675
676 // We only generate virtual base registers for loads and stores, so
677 // return false for everything else.
678 if (!MI->mayLoad() && !MI->mayStore())
679 return false;
680
681 // Without a virtual base register, if the function has variable sized
682 // objects, all fixed-size local references will be via the frame pointer,
683 // Approximate the offset and see if it's legal for the instruction.
684 // Note that the incoming offset is based on the SP value at function entry,
685 // so it'll be negative.
686 MachineFunction &MF = *MI->getParent()->getParent();
687 const AArch64FrameLowering *TFI = getFrameLowering(MF);
688 MachineFrameInfo &MFI = MF.getFrameInfo();
689
690 // Estimate an offset from the frame pointer.
691 // Conservatively assume all GPR callee-saved registers get pushed.
692 // FP, LR, X19-X28, D8-D15. 64-bits each.
693 int64_t FPOffset = Offset - 16 * 20;
694 // Estimate an offset from the stack pointer.
695 // The incoming offset is relating to the SP at the start of the function,
696 // but when we access the local it'll be relative to the SP after local
697 // allocation, so adjust our SP-relative offset by that allocation size.
698 Offset += MFI.getLocalFrameSize();
699 // Assume that we'll have at least some spill slots allocated.
700 // FIXME: This is a total SWAG number. We should run some statistics
701 // and pick a real one.
702 Offset += 128; // 128 bytes of spill slots
703
704 // If there is a frame pointer, try using it.
705 // The FP is only available if there is no dynamic realignment. We
706 // don't know for sure yet whether we'll need that, so we guess based
707 // on whether there are any local variables that would trigger it.
708 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
709 return false;
710
711 // If we can reference via the stack pointer or base pointer, try that.
712 // FIXME: This (and the code that resolves the references) can be improved
713 // to only disallow SP relative references in the live range of
714 // the VLA(s). In practice, it's unclear how much difference that
715 // would make, but it may be worth doing.
716 if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
717 return false;
718
719 // If even offset 0 is illegal, we don't want a virtual base register.
720 if (!isFrameOffsetLegal(MI, AArch64::SP, 0))
721 return false;
722
723 // The offset likely isn't legal; we want to allocate a virtual base register.
724 return true;
725}
726
728 Register BaseReg,
729 int64_t Offset) const {
730 assert(MI && "Unable to get the legal offset for nil instruction.");
733}
734
735/// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
736/// at the beginning of the basic block.
739 int FrameIdx,
740 int64_t Offset) const {
742 DebugLoc DL; // Defaults to "unknown"
743 if (Ins != MBB->end())
744 DL = Ins->getDebugLoc();
745 const MachineFunction &MF = *MBB->getParent();
746 const AArch64InstrInfo *TII =
747 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
748 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
750 Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
751 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
752 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
753
754 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
755 .addFrameIndex(FrameIdx)
756 .addImm(Offset)
757 .addImm(Shifter);
758
759 return BaseReg;
760}
761
763 int64_t Offset) const {
764 // ARM doesn't need the general 64-bit offsets
766
767 unsigned i = 0;
768 while (!MI.getOperand(i).isFI()) {
769 ++i;
770 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
771 }
772
773 const MachineFunction *MF = MI.getParent()->getParent();
774 const AArch64InstrInfo *TII =
775 MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
776 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
777 assert(Done && "Unable to resolve frame index!");
778 (void)Done;
779}
780
781// Create a scratch register for the frame index elimination in an instruction.
782// This function has special handling of stack tagging loop pseudos, in which
783// case it can also change the instruction opcode.
784static Register
786 const AArch64InstrInfo *TII) {
787 // ST*Gloop have a reserved scratch register in operand 1. Use it, and also
788 // replace the instruction with the writeback variant because it will now
789 // satisfy the operand constraints for it.
790 Register ScratchReg;
791 if (MI.getOpcode() == AArch64::STGloop ||
792 MI.getOpcode() == AArch64::STZGloop) {
793 assert(FIOperandNum == 3 &&
794 "Wrong frame index operand for STGloop/STZGloop");
795 unsigned Op = MI.getOpcode() == AArch64::STGloop ? AArch64::STGloop_wback
796 : AArch64::STZGloop_wback;
797 ScratchReg = MI.getOperand(1).getReg();
798 MI.getOperand(3).ChangeToRegister(ScratchReg, false, false, true);
799 MI.setDesc(TII->get(Op));
800 MI.tieOperands(1, 3);
801 } else {
802 ScratchReg =
803 MI.getMF()->getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
804 MI.getOperand(FIOperandNum)
805 .ChangeToRegister(ScratchReg, false, false, true);
806 }
807 return ScratchReg;
808}
809
811 const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
812 // The smallest scalable element supported by scaled SVE addressing
813 // modes are predicates, which are 2 scalable bytes in size. So the scalable
814 // byte offset must always be a multiple of 2.
815 assert(Offset.getScalable() % 2 == 0 && "Invalid frame offset");
816
817 // Add fixed-sized offset using existing DIExpression interface.
818 DIExpression::appendOffset(Ops, Offset.getFixed());
819
820 unsigned VG = getDwarfRegNum(AArch64::VG, true);
821 int64_t VGSized = Offset.getScalable() / 2;
822 if (VGSized > 0) {
823 Ops.push_back(dwarf::DW_OP_constu);
824 Ops.push_back(VGSized);
825 Ops.append({dwarf::DW_OP_bregx, VG, 0ULL});
826 Ops.push_back(dwarf::DW_OP_mul);
827 Ops.push_back(dwarf::DW_OP_plus);
828 } else if (VGSized < 0) {
829 Ops.push_back(dwarf::DW_OP_constu);
830 Ops.push_back(-VGSized);
831 Ops.append({dwarf::DW_OP_bregx, VG, 0ULL});
832 Ops.push_back(dwarf::DW_OP_mul);
833 Ops.push_back(dwarf::DW_OP_minus);
834 }
835}
836
838 int SPAdj, unsigned FIOperandNum,
839 RegScavenger *RS) const {
840 assert(SPAdj == 0 && "Unexpected");
841
842 MachineInstr &MI = *II;
843 MachineBasicBlock &MBB = *MI.getParent();
845 const MachineFrameInfo &MFI = MF.getFrameInfo();
846 const AArch64InstrInfo *TII =
847 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
848 const AArch64FrameLowering *TFI = getFrameLowering(MF);
849 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
850 bool Tagged =
851 MI.getOperand(FIOperandNum).getTargetFlags() & AArch64II::MO_TAGGED;
852 Register FrameReg;
853
854 // Special handling of dbg_value, stackmap patchpoint statepoint instructions.
855 if (MI.getOpcode() == TargetOpcode::STACKMAP ||
856 MI.getOpcode() == TargetOpcode::PATCHPOINT ||
857 MI.getOpcode() == TargetOpcode::STATEPOINT) {
859 TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
860 /*PreferFP=*/true,
861 /*ForSimm=*/false);
862 Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
863 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
864 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
865 return false;
866 }
867
868 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) {
869 MachineOperand &FI = MI.getOperand(FIOperandNum);
871 assert(!Offset.getScalable() &&
872 "Frame offsets with a scalable component are not supported");
873 FI.ChangeToImmediate(Offset.getFixed());
874 return false;
875 }
876
878 if (MI.getOpcode() == AArch64::TAGPstack) {
879 // TAGPstack must use the virtual frame register in its 3rd operand.
881 FrameReg = MI.getOperand(3).getReg();
884 } else if (Tagged) {
886 MFI.getObjectOffset(FrameIndex) + (int64_t)MFI.getStackSize());
887 if (MFI.hasVarSizedObjects() ||
888 isAArch64FrameOffsetLegal(MI, SPOffset, nullptr, nullptr, nullptr) !=
890 // Can't update to SP + offset in place. Precalculate the tagged pointer
891 // in a scratch register.
893 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true);
894 Register ScratchReg =
895 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
896 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset,
897 TII);
898 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AArch64::LDG), ScratchReg)
899 .addReg(ScratchReg)
900 .addReg(ScratchReg)
901 .addImm(0);
902 MI.getOperand(FIOperandNum)
903 .ChangeToRegister(ScratchReg, false, false, true);
904 return false;
905 }
906 FrameReg = AArch64::SP;
908 (int64_t)MFI.getStackSize());
909 } else {
911 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true);
912 }
913
914 // Modify MI as necessary to handle as much of 'Offset' as possible
915 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
916 return true;
917
918 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
919 "Emergency spill slot is out of reach");
920
921 // If we get here, the immediate doesn't fit into the instruction. We folded
922 // as much as possible above. Handle the rest, providing a register that is
923 // SP+LargeImm.
924 Register ScratchReg =
926 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
927 return false;
928}
929
931 MachineFunction &MF) const {
932 const AArch64FrameLowering *TFI = getFrameLowering(MF);
933
934 switch (RC->getID()) {
935 default:
936 return 0;
937 case AArch64::GPR32RegClassID:
938 case AArch64::GPR32spRegClassID:
939 case AArch64::GPR32allRegClassID:
940 case AArch64::GPR64spRegClassID:
941 case AArch64::GPR64allRegClassID:
942 case AArch64::GPR64RegClassID:
943 case AArch64::GPR32commonRegClassID:
944 case AArch64::GPR64commonRegClassID:
945 return 32 - 1 // XZR/SP
946 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
948 - hasBasePointer(MF); // X19
949 case AArch64::FPR8RegClassID:
950 case AArch64::FPR16RegClassID:
951 case AArch64::FPR32RegClassID:
952 case AArch64::FPR64RegClassID:
953 case AArch64::FPR128RegClassID:
954 return 32;
955
956 case AArch64::MatrixIndexGPR32_8_11RegClassID:
957 case AArch64::MatrixIndexGPR32_12_15RegClassID:
958 return 4;
959
960 case AArch64::DDRegClassID:
961 case AArch64::DDDRegClassID:
962 case AArch64::DDDDRegClassID:
963 case AArch64::QQRegClassID:
964 case AArch64::QQQRegClassID:
965 case AArch64::QQQQRegClassID:
966 return 32;
967
968 case AArch64::FPR128_loRegClassID:
969 case AArch64::FPR64_loRegClassID:
970 case AArch64::FPR16_loRegClassID:
971 return 16;
972 }
973}
974
976 const MachineFunction &MF) const {
977 const auto &MFI = MF.getFrameInfo();
978 if (!MF.hasEHFunclets() && !MFI.hasVarSizedObjects())
979 return AArch64::SP;
980 else if (hasStackRealignment(MF))
981 return getBaseRegister();
982 return getFrameRegister(MF);
983}
984
985/// SrcRC and DstRC will be morphed into NewRC if this returns true
987 MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg,
988 const TargetRegisterClass *DstRC, unsigned DstSubReg,
989 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
990 if (MI->isCopy() &&
991 ((DstRC->getID() == AArch64::GPR64RegClassID) ||
992 (DstRC->getID() == AArch64::GPR64commonRegClassID)) &&
993 MI->getOperand(0).getSubReg() && MI->getOperand(1).getSubReg())
994 // Do not coalesce in the case of a 32-bit subregister copy
995 // which implements a 32 to 64 bit zero extension
996 // which relies on the upper 32 bits being zeroed.
997 return false;
998 return true;
999}
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
static Register createScratchRegisterForInstruction(MachineInstr &MI, unsigned FIOperandNum, const AArch64InstrInfo *TII)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements the BitVector class.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
Definition: StackMaps.cpp:195
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:470
StackOffset getNonLocalFrameIndexReference(const MachineFunction &MF, int FI) const override
getNonLocalFrameIndexReference - This method returns the offset used to reference a frame index locat...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
StackOffset resolveFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg, bool PreferFP, bool ForSimm) const
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=AArch64::NoRegAltName)
BitVector getStrictlyReservedRegs(const MachineFunction &MF) const
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
BitVector getReservedRegs(const MachineFunction &MF) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
bool requiresRegisterScavenging(const MachineFunction &MF) const override
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
const uint32_t * getWindowsStackProbePreservedMask() const
Stack probing calls preserve different CSRs to the normal CC.
AArch64RegisterInfo(const Triple &TT)
bool isAnyArgRegReserved(const MachineFunction &MF) const
void emitReservedArgRegCallError(const MachineFunction &MF) const
bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const
Return whether the register needs a CFI entry.
bool isStrictlyReservedReg(const MachineFunction &MF, MCRegister Reg) const
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const uint32_t * getTLSCallPreservedMask() const
const uint32_t * getNoPreservedMask() const override
Register getFrameRegister(const MachineFunction &MF) const override
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
const MCPhysReg * getDarwinCalleeSavedRegs(const MachineFunction *MF) const
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
const uint32_t * SMEABISupportRoutinesCallPreservedMaskFromX0() const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const override
unsigned getLocalAddressRegister(const MachineFunction &MF) const
bool hasBasePointer(const MachineFunction &MF) const
const uint32_t * getDarwinCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
const uint32_t * getSMStartStopCallPreservedMask() const
bool useFPForScavengingIndex(const MachineFunction &MF) const override
bool cannotEliminateFrame(const MachineFunction &MF) const
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const override
void UpdateCustomCallPreservedMask(MachineFunction &MF, const uint32_t **Mask) const
std::optional< std::string > explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool isXRegisterReservedForRA(size_t i) const
unsigned getNumXRegisterReserved() const
const AArch64TargetLowering * getTargetLowering() const override
bool isCallingConvWin64(CallingConv::ID CC) const
bool isXRegCustomCalleeSaved(size_t i) const
bool isXRegisterReserved(size_t i) const
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value.
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Diagnostic information for unsupported feature in backend.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:315
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:645
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
int64_t getLocalFrameSize() const
Get the size of the local object blob.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
uint32_t * allocateRegMask()
Allocate and initialize a register mask with NumRegister bits.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:687
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:36
int64_t getFixed() const
Returns the fixed component of the stack.
Definition: TypeSize.h:52
TargetOptions Options
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
unsigned getID() const
Return the register class ID number.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
Definition: Triple.h:518
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:675
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
@ AArch64_VectorCall
Used between AArch64 Advanced SIMD functions.
Definition: CallingConv.h:218
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
@ AArch64_SVE_VectorCall
Used between AArch64 SVE functions.
Definition: CallingConv.h:221
@ CFGuard_Check
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
Definition: CallingConv.h:82
@ PreserveMost
Used for runtime calls that preserves most registers.
Definition: CallingConv.h:63
@ AnyReg
Used for dynamic register based calls (e.g.
Definition: CallingConv.h:60
@ AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2
Preserve X2-X15, X19-X29, SP, Z0-Z31, P0-P15.
Definition: CallingConv.h:238
@ CXX_FAST_TLS
Used for access functions.
Definition: CallingConv.h:72
@ AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0
Preserve X0-X13, X19-X29, SP, Z0-Z31, P0-P15.
Definition: CallingConv.h:235
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
Definition: CallingConv.h:50
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
Definition: CallingConv.h:66
@ WebKit_JS
Used for stack based JavaScript calls.
Definition: CallingConv.h:56
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Definition: CallingConv.h:76
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:156
@ SwiftTail
This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...
Definition: CallingConv.h:87
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
@ Done
Definition: Threading.h:61
@ AArch64FrameOffsetIsLegal
Offset is legal.
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1734
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1884