LLVM 19.0.0git
AArch64RegisterInfo.cpp
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1//===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AArch64 implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AArch64RegisterInfo.h"
16#include "AArch64InstrInfo.h"
18#include "AArch64Subtarget.h"
21#include "llvm/ADT/BitVector.h"
30#include "llvm/IR/Function.h"
34
35using namespace llvm;
36
37#define GET_CC_REGISTER_LISTS
38#include "AArch64GenCallingConv.inc"
39#define GET_REGINFO_TARGET_DESC
40#include "AArch64GenRegisterInfo.inc"
41
43 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
45}
46
47/// Return whether the register needs a CFI entry. Not all unwinders may know
48/// about SVE registers, so we assume the lowest common denominator, i.e. the
49/// callee-saves required by the base ABI. For the SVE registers z8-z15 only the
50/// lower 64-bits (d8-d15) need to be saved. The lower 64-bits subreg is
51/// returned in \p RegToUseForCFI.
53 unsigned &RegToUseForCFI) const {
54 if (AArch64::PPRRegClass.contains(Reg))
55 return false;
56
57 if (AArch64::ZPRRegClass.contains(Reg)) {
58 RegToUseForCFI = getSubReg(Reg, AArch64::dsub);
59 for (int I = 0; CSR_AArch64_AAPCS_SaveList[I]; ++I) {
60 if (CSR_AArch64_AAPCS_SaveList[I] == RegToUseForCFI)
61 return true;
62 }
63 return false;
64 }
65
66 RegToUseForCFI = Reg;
67 return true;
68}
69
70const MCPhysReg *
72 assert(MF && "Invalid MachineFunction pointer.");
73
75 // GHC set of callee saved regs is empty as all those regs are
76 // used for passing STG regs around
77 return CSR_AArch64_NoRegs_SaveList;
79 return CSR_AArch64_NoneRegs_SaveList;
81 return CSR_AArch64_AllRegs_SaveList;
82
84 return CSR_Win_AArch64_Arm64EC_Thunk_SaveList;
85
86 // Darwin has its own CSR_AArch64_AAPCS_SaveList, which means most CSR save
87 // lists depending on that will need to have their Darwin variant as well.
89 return getDarwinCalleeSavedRegs(MF);
90
92 return CSR_Win_AArch64_CFGuard_Check_SaveList;
97 Attribute::SwiftError))
98 return CSR_Win_AArch64_AAPCS_SwiftError_SaveList;
100 return CSR_Win_AArch64_AAPCS_SwiftTail_SaveList;
101 return CSR_Win_AArch64_AAPCS_SaveList;
102 }
104 return CSR_AArch64_AAVPCS_SaveList;
106 return CSR_AArch64_SVE_AAPCS_SaveList;
107 if (MF->getFunction().getCallingConv() ==
110 "Calling convention "
111 "AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0 is only "
112 "supported to improve calls to SME ACLE save/restore/disable-za "
113 "functions, and is not intended to be used beyond that scope.");
114 if (MF->getFunction().getCallingConv() ==
117 "Calling convention "
118 "AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1 is "
119 "only supported to improve calls to SME ACLE __arm_get_current_vg "
120 "function, and is not intended to be used beyond that scope.");
121 if (MF->getFunction().getCallingConv() ==
124 "Calling convention "
125 "AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2 is "
126 "only supported to improve calls to SME ACLE __arm_sme_state "
127 "and is not intended to be used beyond that scope.");
129 ->supportSwiftError() &&
131 Attribute::SwiftError))
132 return CSR_AArch64_AAPCS_SwiftError_SaveList;
134 return CSR_AArch64_AAPCS_SwiftTail_SaveList;
136 return CSR_AArch64_RT_MostRegs_SaveList;
138 return CSR_AArch64_RT_AllRegs_SaveList;
140 // This is for OSes other than Windows; Windows is a separate case further
141 // above.
142 return CSR_AArch64_AAPCS_X18_SaveList;
143 if (MF->getInfo<AArch64FunctionInfo>()->isSVECC())
144 return CSR_AArch64_SVE_AAPCS_SaveList;
145 return CSR_AArch64_AAPCS_SaveList;
146}
147
148const MCPhysReg *
150 assert(MF && "Invalid MachineFunction pointer.");
152 "Invalid subtarget for getDarwinCalleeSavedRegs");
153
156 "Calling convention CFGuard_Check is unsupported on Darwin.");
158 return CSR_Darwin_AArch64_AAVPCS_SaveList;
161 "Calling convention SVE_VectorCall is unsupported on Darwin.");
162 if (MF->getFunction().getCallingConv() ==
165 "Calling convention "
166 "AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0 is "
167 "only supported to improve calls to SME ACLE save/restore/disable-za "
168 "functions, and is not intended to be used beyond that scope.");
169 if (MF->getFunction().getCallingConv() ==
172 "Calling convention "
173 "AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1 is "
174 "only supported to improve calls to SME ACLE __arm_get_current_vg "
175 "function, and is not intended to be used beyond that scope.");
176 if (MF->getFunction().getCallingConv() ==
179 "Calling convention "
180 "AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2 is "
181 "only supported to improve calls to SME ACLE __arm_sme_state "
182 "and is not intended to be used beyond that scope.");
184 return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR()
185 ? CSR_Darwin_AArch64_CXX_TLS_PE_SaveList
186 : CSR_Darwin_AArch64_CXX_TLS_SaveList;
188 ->supportSwiftError() &&
190 Attribute::SwiftError))
191 return CSR_Darwin_AArch64_AAPCS_SwiftError_SaveList;
193 return CSR_Darwin_AArch64_AAPCS_SwiftTail_SaveList;
195 return CSR_Darwin_AArch64_RT_MostRegs_SaveList;
197 return CSR_Darwin_AArch64_RT_AllRegs_SaveList;
199 return CSR_Darwin_AArch64_AAPCS_Win64_SaveList;
200 return CSR_Darwin_AArch64_AAPCS_SaveList;
201}
202
204 const MachineFunction *MF) const {
205 assert(MF && "Invalid MachineFunction pointer.");
208 return CSR_Darwin_AArch64_CXX_TLS_ViaCopy_SaveList;
209 return nullptr;
210}
211
213 MachineFunction &MF) const {
214 const MCPhysReg *CSRs = getCalleeSavedRegs(&MF);
215 SmallVector<MCPhysReg, 32> UpdatedCSRs;
216 for (const MCPhysReg *I = CSRs; *I; ++I)
217 UpdatedCSRs.push_back(*I);
218
219 for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
221 UpdatedCSRs.push_back(AArch64::GPR64commonRegClass.getRegister(i));
222 }
223 }
224 // Register lists are zero-terminated.
225 UpdatedCSRs.push_back(0);
226 MF.getRegInfo().setCalleeSavedRegs(UpdatedCSRs);
227}
228
231 unsigned Idx) const {
232 // edge case for GPR/FPR register classes
233 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub)
234 return &AArch64::FPR32RegClass;
235 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub)
236 return &AArch64::FPR64RegClass;
237
238 // Forward to TableGen's default version.
239 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
240}
241
242const uint32_t *
244 CallingConv::ID CC) const {
246 "Invalid subtarget for getDarwinCallPreservedMask");
247
249 return CSR_Darwin_AArch64_CXX_TLS_RegMask;
251 return CSR_Darwin_AArch64_AAVPCS_RegMask;
254 "Calling convention SVE_VectorCall is unsupported on Darwin.");
256 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0_RegMask;
258 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1_RegMask;
260 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2_RegMask;
263 "Calling convention CFGuard_Check is unsupported on Darwin.");
266 ->supportSwiftError() &&
267 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
268 return CSR_Darwin_AArch64_AAPCS_SwiftError_RegMask;
270 return CSR_Darwin_AArch64_AAPCS_SwiftTail_RegMask;
272 return CSR_Darwin_AArch64_RT_MostRegs_RegMask;
274 return CSR_Darwin_AArch64_RT_AllRegs_RegMask;
275 return CSR_Darwin_AArch64_AAPCS_RegMask;
276}
277
278const uint32_t *
280 CallingConv::ID CC) const {
281 bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
282 if (CC == CallingConv::GHC)
283 // This is academic because all GHC calls are (supposed to be) tail calls
284 return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask;
286 return SCS ? CSR_AArch64_NoneRegs_SCS_RegMask
287 : CSR_AArch64_NoneRegs_RegMask;
288 if (CC == CallingConv::AnyReg)
289 return SCS ? CSR_AArch64_AllRegs_SCS_RegMask : CSR_AArch64_AllRegs_RegMask;
290
291 // All the following calling conventions are handled differently on Darwin.
293 if (SCS)
294 report_fatal_error("ShadowCallStack attribute not supported on Darwin.");
295 return getDarwinCallPreservedMask(MF, CC);
296 }
297
299 return SCS ? CSR_AArch64_AAVPCS_SCS_RegMask : CSR_AArch64_AAVPCS_RegMask;
301 return SCS ? CSR_AArch64_SVE_AAPCS_SCS_RegMask
302 : CSR_AArch64_SVE_AAPCS_RegMask;
304 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0_RegMask;
306 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1_RegMask;
308 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2_RegMask;
310 return CSR_Win_AArch64_CFGuard_Check_RegMask;
312 ->supportSwiftError() &&
313 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
314 return SCS ? CSR_AArch64_AAPCS_SwiftError_SCS_RegMask
315 : CSR_AArch64_AAPCS_SwiftError_RegMask;
316 if (CC == CallingConv::SwiftTail) {
317 if (SCS)
318 report_fatal_error("ShadowCallStack attribute not supported with swifttail");
319 return CSR_AArch64_AAPCS_SwiftTail_RegMask;
320 }
322 return SCS ? CSR_AArch64_RT_MostRegs_SCS_RegMask
323 : CSR_AArch64_RT_MostRegs_RegMask;
325 return SCS ? CSR_AArch64_RT_AllRegs_SCS_RegMask
326 : CSR_AArch64_RT_AllRegs_RegMask;
327
328 return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
329}
330
332 const MachineFunction &MF) const {
334 return CSR_AArch64_AAPCS_RegMask;
335
336 return nullptr;
337}
338
340 if (TT.isOSDarwin())
341 return CSR_Darwin_AArch64_TLS_RegMask;
342
343 assert(TT.isOSBinFormatELF() && "Invalid target");
344 return CSR_AArch64_TLS_ELF_RegMask;
345}
346
348 const uint32_t **Mask) const {
349 uint32_t *UpdatedMask = MF.allocateRegMask();
350 unsigned RegMaskSize = MachineOperand::getRegMaskSize(getNumRegs());
351 memcpy(UpdatedMask, *Mask, sizeof(UpdatedMask[0]) * RegMaskSize);
352
353 for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
355 for (MCPhysReg SubReg :
356 subregs_inclusive(AArch64::GPR64commonRegClass.getRegister(i))) {
357 // See TargetRegisterInfo::getCallPreservedMask for how to interpret the
358 // register mask.
359 UpdatedMask[SubReg / 32] |= 1u << (SubReg % 32);
360 }
361 }
362 }
363 *Mask = UpdatedMask;
364}
365
367 return CSR_AArch64_SMStartStop_RegMask;
368}
369
370const uint32_t *
372 return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0_RegMask;
373}
374
376 return CSR_AArch64_NoRegs_RegMask;
377}
378
379const uint32_t *
381 CallingConv::ID CC) const {
382 // This should return a register mask that is the same as that returned by
383 // getCallPreservedMask but that additionally preserves the register used for
384 // the first i64 argument (which must also be the register used to return a
385 // single i64 return value)
386 //
387 // In case that the calling convention does not use the same register for
388 // both, the function should return NULL (does not currently apply)
389 assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
391 return CSR_Darwin_AArch64_AAPCS_ThisReturn_RegMask;
392 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
393}
394
396 return CSR_AArch64_StackProbe_Windows_RegMask;
397}
398
399std::optional<std::string>
401 MCRegister PhysReg) const {
402 if (hasBasePointer(MF) && MCRegisterInfo::regsOverlap(PhysReg, AArch64::X19))
403 return std::string("X19 is used as the frame base pointer register.");
404
406 bool warn = false;
407 if (MCRegisterInfo::regsOverlap(PhysReg, AArch64::X13) ||
408 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X14) ||
409 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X23) ||
410 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X24) ||
411 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X28))
412 warn = true;
413
414 for (unsigned i = AArch64::B16; i <= AArch64::B31; ++i)
415 if (MCRegisterInfo::regsOverlap(PhysReg, i))
416 warn = true;
417
418 if (warn)
419 return std::string(AArch64InstPrinter::getRegisterName(PhysReg)) +
420 " is clobbered by asynchronous signals when using Arm64EC.";
421 }
422
423 return {};
424}
425
428 const AArch64FrameLowering *TFI = getFrameLowering(MF);
429
430 // FIXME: avoid re-calculating this every time.
431 BitVector Reserved(getNumRegs());
432 markSuperRegs(Reserved, AArch64::WSP);
433 markSuperRegs(Reserved, AArch64::WZR);
434
435 if (TFI->hasFP(MF) || TT.isOSDarwin())
436 markSuperRegs(Reserved, AArch64::W29);
437
439 // x13, x14, x23, x24, x28, and v16-v31 are clobbered by asynchronous
440 // signals, so we can't ever use them.
441 markSuperRegs(Reserved, AArch64::W13);
442 markSuperRegs(Reserved, AArch64::W14);
443 markSuperRegs(Reserved, AArch64::W23);
444 markSuperRegs(Reserved, AArch64::W24);
445 markSuperRegs(Reserved, AArch64::W28);
446 for (unsigned i = AArch64::B16; i <= AArch64::B31; ++i)
447 markSuperRegs(Reserved, i);
448 }
449
450 for (size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) {
452 markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(i));
453 }
454
455 if (hasBasePointer(MF))
456 markSuperRegs(Reserved, AArch64::W19);
457
458 // SLH uses register W16/X16 as the taint register.
459 if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening))
460 markSuperRegs(Reserved, AArch64::W16);
461
462 // FFR is modelled as global state that cannot be allocated.
463 if (MF.getSubtarget<AArch64Subtarget>().hasSVE())
464 Reserved.set(AArch64::FFR);
465
466 // SME tiles are not allocatable.
467 if (MF.getSubtarget<AArch64Subtarget>().hasSME()) {
468 for (MCPhysReg SubReg : subregs_inclusive(AArch64::ZA))
469 Reserved.set(SubReg);
470 }
471
472 // VG cannot be allocated
473 Reserved.set(AArch64::VG);
474
475 if (MF.getSubtarget<AArch64Subtarget>().hasSME2()) {
476 for (MCSubRegIterator SubReg(AArch64::ZT0, this, /*self=*/true);
477 SubReg.isValid(); ++SubReg)
478 Reserved.set(*SubReg);
479 }
480
481 markSuperRegs(Reserved, AArch64::FPCR);
482 markSuperRegs(Reserved, AArch64::FPSR);
483
485 markSuperRegs(Reserved, AArch64::X27);
486 markSuperRegs(Reserved, AArch64::X28);
487 markSuperRegs(Reserved, AArch64::W27);
488 markSuperRegs(Reserved, AArch64::W28);
489 }
490
491 assert(checkAllSuperRegsMarked(Reserved));
492 return Reserved;
493}
494
498
499 for (size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) {
501 markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(i));
502 }
503
504 assert(checkAllSuperRegsMarked(Reserved));
505 return Reserved;
506}
507
509 MCRegister Reg) const {
510 return getReservedRegs(MF)[Reg];
511}
512
514 MCRegister Reg) const {
515 return getStrictlyReservedRegs(MF)[Reg];
516}
517
519 return llvm::any_of(*AArch64::GPR64argRegClass.MC, [this, &MF](MCPhysReg r) {
520 return isStrictlyReservedReg(MF, r);
521 });
522}
523
525 const MachineFunction &MF) const {
526 const Function &F = MF.getFunction();
527 F.getContext().diagnose(DiagnosticInfoUnsupported{F, ("AArch64 doesn't support"
528 " function calls if any of the argument registers is reserved.")});
529}
530
532 MCRegister PhysReg) const {
533 // SLH uses register X16 as the taint register but it will fallback to a different
534 // method if the user clobbers it. So X16 is not reserved for inline asm but is
535 // for normal codegen.
536 if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening) &&
537 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X16))
538 return true;
539
540 // ZA/ZT0 registers are reserved but may be permitted in the clobber list.
541 if (PhysReg == AArch64::ZA || PhysReg == AArch64::ZT0)
542 return true;
543
544 return !isReservedReg(MF, PhysReg);
545}
546
549 unsigned Kind) const {
550 return &AArch64::GPR64spRegClass;
551}
552
555 if (RC == &AArch64::CCRRegClass)
556 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
557 return RC;
558}
559
560unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
561
563 const MachineFrameInfo &MFI = MF.getFrameInfo();
564
565 // In the presence of variable sized objects or funclets, if the fixed stack
566 // size is large enough that referencing from the FP won't result in things
567 // being in range relatively often, we can use a base pointer to allow access
568 // from the other direction like the SP normally works.
569 //
570 // Furthermore, if both variable sized objects are present, and the
571 // stack needs to be dynamically re-aligned, the base pointer is the only
572 // reliable way to reference the locals.
573 if (MFI.hasVarSizedObjects() || MF.hasEHFunclets()) {
574 if (hasStackRealignment(MF))
575 return true;
576
577 auto &ST = MF.getSubtarget<AArch64Subtarget>();
578 if (ST.hasSVE() || ST.isStreaming()) {
580 // Frames that have variable sized objects and scalable SVE objects,
581 // should always use a basepointer.
582 if (!AFI->hasCalculatedStackSizeSVE() || AFI->getStackSizeSVE())
583 return true;
584 }
585
586 // Conservatively estimate whether the negative offset from the frame
587 // pointer will be sufficient to reach. If a function has a smallish
588 // frame, it's less likely to have lots of spills and callee saved
589 // space, so it's all more likely to be within range of the frame pointer.
590 // If it's wrong, we'll materialize the constant and still get to the
591 // object; it's just suboptimal. Negative offsets use the unscaled
592 // load/store instructions, which have a 9-bit signed immediate.
593 return MFI.getLocalFrameSize() >= 256;
594 }
595
596 return false;
597}
598
600 MCRegister Reg) const {
603 bool IsVarArg = STI.isCallingConvWin64(MF.getFunction().getCallingConv());
604
605 auto HasReg = [](ArrayRef<MCRegister> RegList, MCRegister Reg) {
606 return llvm::is_contained(RegList, Reg);
607 };
608
609 switch (CC) {
610 default:
611 report_fatal_error("Unsupported calling convention.");
612 case CallingConv::GHC:
613 return HasReg(CC_AArch64_GHC_ArgRegs, Reg);
615 return HasReg(CC_AArch64_Preserve_None_ArgRegs, Reg);
616 case CallingConv::C:
624 if (STI.isTargetWindows()) {
625 if (IsVarArg)
626 return HasReg(CC_AArch64_Win64_VarArg_ArgRegs, Reg);
627 switch (CC) {
628 default:
629 return HasReg(CC_AArch64_Win64PCS_ArgRegs, Reg);
632 return HasReg(CC_AArch64_Win64PCS_Swift_ArgRegs, Reg) ||
633 HasReg(CC_AArch64_Win64PCS_ArgRegs, Reg);
634 }
635 }
636 if (!STI.isTargetDarwin()) {
637 switch (CC) {
638 default:
639 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg);
642 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg) ||
643 HasReg(CC_AArch64_AAPCS_Swift_ArgRegs, Reg);
644 }
645 }
646 if (!IsVarArg) {
647 switch (CC) {
648 default:
649 return HasReg(CC_AArch64_DarwinPCS_ArgRegs, Reg);
652 return HasReg(CC_AArch64_DarwinPCS_ArgRegs, Reg) ||
653 HasReg(CC_AArch64_DarwinPCS_Swift_ArgRegs, Reg);
654 }
655 }
656 if (STI.isTargetILP32())
657 return HasReg(CC_AArch64_DarwinPCS_ILP32_VarArg_ArgRegs, Reg);
658 return HasReg(CC_AArch64_DarwinPCS_VarArg_ArgRegs, Reg);
660 if (IsVarArg)
661 HasReg(CC_AArch64_Win64_VarArg_ArgRegs, Reg);
662 return HasReg(CC_AArch64_Win64PCS_ArgRegs, Reg);
664 return HasReg(CC_AArch64_Win64_CFGuard_Check_ArgRegs, Reg);
670 if (STI.isTargetWindows())
671 return HasReg(CC_AArch64_Win64PCS_ArgRegs, Reg);
672 return HasReg(CC_AArch64_AAPCS_ArgRegs, Reg);
673 }
674}
675
678 const AArch64FrameLowering *TFI = getFrameLowering(MF);
679 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
680}
681
683 const MachineFunction &MF) const {
684 return true;
685}
686
688 const MachineFunction &MF) const {
689 return true;
690}
691
692bool
694 // This function indicates whether the emergency spillslot should be placed
695 // close to the beginning of the stackframe (closer to FP) or the end
696 // (closer to SP).
697 //
698 // The beginning works most reliably if we have a frame pointer.
699 // In the presence of any non-constant space between FP and locals,
700 // (e.g. in case of stack realignment or a scalable SVE area), it is
701 // better to use SP or BP.
702 const AArch64FrameLowering &TFI = *getFrameLowering(MF);
704 assert((!MF.getSubtarget<AArch64Subtarget>().hasSVE() ||
706 "Expected SVE area to be calculated by this point");
707 return TFI.hasFP(MF) && !hasStackRealignment(MF) && !AFI->getStackSizeSVE();
708}
709
711 const MachineFunction &MF) const {
712 return true;
713}
714
715bool
717 const MachineFrameInfo &MFI = MF.getFrameInfo();
719 return true;
720 return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
721}
722
723/// needsFrameBaseReg - Returns true if the instruction's frame index
724/// reference would be better served by a base register other than FP
725/// or SP. Used by LocalStackFrameAllocation to determine which frame index
726/// references it should create new base registers for.
728 int64_t Offset) const {
729 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
730 assert(i < MI->getNumOperands() &&
731 "Instr doesn't have FrameIndex operand!");
732
733 // It's the load/store FI references that cause issues, as it can be difficult
734 // to materialize the offset if it won't fit in the literal field. Estimate
735 // based on the size of the local frame and some conservative assumptions
736 // about the rest of the stack frame (note, this is pre-regalloc, so
737 // we don't know everything for certain yet) whether this offset is likely
738 // to be out of range of the immediate. Return true if so.
739
740 // We only generate virtual base registers for loads and stores, so
741 // return false for everything else.
742 if (!MI->mayLoad() && !MI->mayStore())
743 return false;
744
745 // Without a virtual base register, if the function has variable sized
746 // objects, all fixed-size local references will be via the frame pointer,
747 // Approximate the offset and see if it's legal for the instruction.
748 // Note that the incoming offset is based on the SP value at function entry,
749 // so it'll be negative.
750 MachineFunction &MF = *MI->getParent()->getParent();
751 const AArch64FrameLowering *TFI = getFrameLowering(MF);
752 MachineFrameInfo &MFI = MF.getFrameInfo();
753
754 // Estimate an offset from the frame pointer.
755 // Conservatively assume all GPR callee-saved registers get pushed.
756 // FP, LR, X19-X28, D8-D15. 64-bits each.
757 int64_t FPOffset = Offset - 16 * 20;
758 // Estimate an offset from the stack pointer.
759 // The incoming offset is relating to the SP at the start of the function,
760 // but when we access the local it'll be relative to the SP after local
761 // allocation, so adjust our SP-relative offset by that allocation size.
762 Offset += MFI.getLocalFrameSize();
763 // Assume that we'll have at least some spill slots allocated.
764 // FIXME: This is a total SWAG number. We should run some statistics
765 // and pick a real one.
766 Offset += 128; // 128 bytes of spill slots
767
768 // If there is a frame pointer, try using it.
769 // The FP is only available if there is no dynamic realignment. We
770 // don't know for sure yet whether we'll need that, so we guess based
771 // on whether there are any local variables that would trigger it.
772 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
773 return false;
774
775 // If we can reference via the stack pointer or base pointer, try that.
776 // FIXME: This (and the code that resolves the references) can be improved
777 // to only disallow SP relative references in the live range of
778 // the VLA(s). In practice, it's unclear how much difference that
779 // would make, but it may be worth doing.
780 if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
781 return false;
782
783 // If even offset 0 is illegal, we don't want a virtual base register.
784 if (!isFrameOffsetLegal(MI, AArch64::SP, 0))
785 return false;
786
787 // The offset likely isn't legal; we want to allocate a virtual base register.
788 return true;
789}
790
792 Register BaseReg,
793 int64_t Offset) const {
794 assert(MI && "Unable to get the legal offset for nil instruction.");
797}
798
799/// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
800/// at the beginning of the basic block.
803 int FrameIdx,
804 int64_t Offset) const {
806 DebugLoc DL; // Defaults to "unknown"
807 if (Ins != MBB->end())
808 DL = Ins->getDebugLoc();
809 const MachineFunction &MF = *MBB->getParent();
810 const AArch64InstrInfo *TII =
811 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
812 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
814 Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
815 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
816 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
817
818 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
819 .addFrameIndex(FrameIdx)
820 .addImm(Offset)
821 .addImm(Shifter);
822
823 return BaseReg;
824}
825
827 int64_t Offset) const {
828 // ARM doesn't need the general 64-bit offsets
830
831 unsigned i = 0;
832 while (!MI.getOperand(i).isFI()) {
833 ++i;
834 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
835 }
836
837 const MachineFunction *MF = MI.getParent()->getParent();
838 const AArch64InstrInfo *TII =
839 MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
840 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
841 assert(Done && "Unable to resolve frame index!");
842 (void)Done;
843}
844
845// Create a scratch register for the frame index elimination in an instruction.
846// This function has special handling of stack tagging loop pseudos, in which
847// case it can also change the instruction opcode.
848static Register
850 const AArch64InstrInfo *TII) {
851 // ST*Gloop have a reserved scratch register in operand 1. Use it, and also
852 // replace the instruction with the writeback variant because it will now
853 // satisfy the operand constraints for it.
854 Register ScratchReg;
855 if (MI.getOpcode() == AArch64::STGloop ||
856 MI.getOpcode() == AArch64::STZGloop) {
857 assert(FIOperandNum == 3 &&
858 "Wrong frame index operand for STGloop/STZGloop");
859 unsigned Op = MI.getOpcode() == AArch64::STGloop ? AArch64::STGloop_wback
860 : AArch64::STZGloop_wback;
861 ScratchReg = MI.getOperand(1).getReg();
862 MI.getOperand(3).ChangeToRegister(ScratchReg, false, false, true);
863 MI.setDesc(TII->get(Op));
864 MI.tieOperands(1, 3);
865 } else {
866 ScratchReg =
867 MI.getMF()->getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
868 MI.getOperand(FIOperandNum)
869 .ChangeToRegister(ScratchReg, false, false, true);
870 }
871 return ScratchReg;
872}
873
875 const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
876 // The smallest scalable element supported by scaled SVE addressing
877 // modes are predicates, which are 2 scalable bytes in size. So the scalable
878 // byte offset must always be a multiple of 2.
879 assert(Offset.getScalable() % 2 == 0 && "Invalid frame offset");
880
881 // Add fixed-sized offset using existing DIExpression interface.
882 DIExpression::appendOffset(Ops, Offset.getFixed());
883
884 unsigned VG = getDwarfRegNum(AArch64::VG, true);
885 int64_t VGSized = Offset.getScalable() / 2;
886 if (VGSized > 0) {
887 Ops.push_back(dwarf::DW_OP_constu);
888 Ops.push_back(VGSized);
889 Ops.append({dwarf::DW_OP_bregx, VG, 0ULL});
890 Ops.push_back(dwarf::DW_OP_mul);
891 Ops.push_back(dwarf::DW_OP_plus);
892 } else if (VGSized < 0) {
893 Ops.push_back(dwarf::DW_OP_constu);
894 Ops.push_back(-VGSized);
895 Ops.append({dwarf::DW_OP_bregx, VG, 0ULL});
896 Ops.push_back(dwarf::DW_OP_mul);
897 Ops.push_back(dwarf::DW_OP_minus);
898 }
899}
900
902 int SPAdj, unsigned FIOperandNum,
903 RegScavenger *RS) const {
904 assert(SPAdj == 0 && "Unexpected");
905
906 MachineInstr &MI = *II;
907 MachineBasicBlock &MBB = *MI.getParent();
909 const MachineFrameInfo &MFI = MF.getFrameInfo();
910 const AArch64InstrInfo *TII =
911 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
912 const AArch64FrameLowering *TFI = getFrameLowering(MF);
913 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
914 bool Tagged =
915 MI.getOperand(FIOperandNum).getTargetFlags() & AArch64II::MO_TAGGED;
916 Register FrameReg;
917
918 // Special handling of dbg_value, stackmap patchpoint statepoint instructions.
919 if (MI.getOpcode() == TargetOpcode::STACKMAP ||
920 MI.getOpcode() == TargetOpcode::PATCHPOINT ||
921 MI.getOpcode() == TargetOpcode::STATEPOINT) {
923 TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
924 /*PreferFP=*/true,
925 /*ForSimm=*/false);
926 Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
927 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
928 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
929 return false;
930 }
931
932 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) {
933 MachineOperand &FI = MI.getOperand(FIOperandNum);
935 assert(!Offset.getScalable() &&
936 "Frame offsets with a scalable component are not supported");
937 FI.ChangeToImmediate(Offset.getFixed());
938 return false;
939 }
940
942 if (MI.getOpcode() == AArch64::TAGPstack) {
943 // TAGPstack must use the virtual frame register in its 3rd operand.
945 FrameReg = MI.getOperand(3).getReg();
948 } else if (Tagged) {
950 MFI.getObjectOffset(FrameIndex) + (int64_t)MFI.getStackSize());
951 if (MFI.hasVarSizedObjects() ||
952 isAArch64FrameOffsetLegal(MI, SPOffset, nullptr, nullptr, nullptr) !=
954 // Can't update to SP + offset in place. Precalculate the tagged pointer
955 // in a scratch register.
957 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true);
958 Register ScratchReg =
959 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
960 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset,
961 TII);
962 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AArch64::LDG), ScratchReg)
963 .addReg(ScratchReg)
964 .addReg(ScratchReg)
965 .addImm(0);
966 MI.getOperand(FIOperandNum)
967 .ChangeToRegister(ScratchReg, false, false, true);
968 return false;
969 }
970 FrameReg = AArch64::SP;
972 (int64_t)MFI.getStackSize());
973 } else {
975 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true);
976 }
977
978 // Modify MI as necessary to handle as much of 'Offset' as possible
979 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
980 return true;
981
982 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
983 "Emergency spill slot is out of reach");
984
985 // If we get here, the immediate doesn't fit into the instruction. We folded
986 // as much as possible above. Handle the rest, providing a register that is
987 // SP+LargeImm.
988 Register ScratchReg =
990 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
991 return false;
992}
993
995 MachineFunction &MF) const {
996 const AArch64FrameLowering *TFI = getFrameLowering(MF);
997
998 switch (RC->getID()) {
999 default:
1000 return 0;
1001 case AArch64::GPR32RegClassID:
1002 case AArch64::GPR32spRegClassID:
1003 case AArch64::GPR32allRegClassID:
1004 case AArch64::GPR64spRegClassID:
1005 case AArch64::GPR64allRegClassID:
1006 case AArch64::GPR64RegClassID:
1007 case AArch64::GPR32commonRegClassID:
1008 case AArch64::GPR64commonRegClassID:
1009 return 32 - 1 // XZR/SP
1010 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
1012 - hasBasePointer(MF); // X19
1013 case AArch64::FPR8RegClassID:
1014 case AArch64::FPR16RegClassID:
1015 case AArch64::FPR32RegClassID:
1016 case AArch64::FPR64RegClassID:
1017 case AArch64::FPR128RegClassID:
1018 return 32;
1019
1020 case AArch64::MatrixIndexGPR32_8_11RegClassID:
1021 case AArch64::MatrixIndexGPR32_12_15RegClassID:
1022 return 4;
1023
1024 case AArch64::DDRegClassID:
1025 case AArch64::DDDRegClassID:
1026 case AArch64::DDDDRegClassID:
1027 case AArch64::QQRegClassID:
1028 case AArch64::QQQRegClassID:
1029 case AArch64::QQQQRegClassID:
1030 return 32;
1031
1032 case AArch64::FPR128_loRegClassID:
1033 case AArch64::FPR64_loRegClassID:
1034 case AArch64::FPR16_loRegClassID:
1035 return 16;
1036 case AArch64::FPR128_0to7RegClassID:
1037 return 8;
1038 }
1039}
1040
1042 const MachineFunction &MF) const {
1043 const auto &MFI = MF.getFrameInfo();
1044 if (!MF.hasEHFunclets() && !MFI.hasVarSizedObjects())
1045 return AArch64::SP;
1046 else if (hasStackRealignment(MF))
1047 return getBaseRegister();
1048 return getFrameRegister(MF);
1049}
1050
1051/// SrcRC and DstRC will be morphed into NewRC if this returns true
1053 MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg,
1054 const TargetRegisterClass *DstRC, unsigned DstSubReg,
1055 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
1056 MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
1057
1058 if (MI->isCopy() &&
1059 ((DstRC->getID() == AArch64::GPR64RegClassID) ||
1060 (DstRC->getID() == AArch64::GPR64commonRegClassID)) &&
1061 MI->getOperand(0).getSubReg() && MI->getOperand(1).getSubReg())
1062 // Do not coalesce in the case of a 32-bit subregister copy
1063 // which implements a 32 to 64 bit zero extension
1064 // which relies on the upper 32 bits being zeroed.
1065 return false;
1066
1067 auto IsCoalescerBarrier = [](const MachineInstr &MI) {
1068 switch (MI.getOpcode()) {
1069 case AArch64::COALESCER_BARRIER_FPR16:
1070 case AArch64::COALESCER_BARRIER_FPR32:
1071 case AArch64::COALESCER_BARRIER_FPR64:
1072 case AArch64::COALESCER_BARRIER_FPR128:
1073 return true;
1074 default:
1075 return false;
1076 }
1077 };
1078
1079 // For calls that temporarily have to toggle streaming mode as part of the
1080 // call-sequence, we need to be more careful when coalescing copy instructions
1081 // so that we don't end up coalescing the NEON/FP result or argument register
1082 // with a whole Z-register, such that after coalescing the register allocator
1083 // will try to spill/reload the entire Z register.
1084 //
1085 // We do this by checking if the node has any defs/uses that are
1086 // COALESCER_BARRIER pseudos. These are 'nops' in practice, but they exist to
1087 // instruct the coalescer to avoid coalescing the copy.
1088 if (MI->isCopy() && SubReg != DstSubReg &&
1089 (AArch64::ZPRRegClass.hasSubClassEq(DstRC) ||
1090 AArch64::ZPRRegClass.hasSubClassEq(SrcRC))) {
1091 unsigned SrcReg = MI->getOperand(1).getReg();
1092 if (any_of(MRI.def_instructions(SrcReg), IsCoalescerBarrier))
1093 return false;
1094 unsigned DstReg = MI->getOperand(0).getReg();
1095 if (any_of(MRI.use_nodbg_instructions(DstReg), IsCoalescerBarrier))
1096 return false;
1097 }
1098
1099 return true;
1100}
1101
1103 MCRegister R) const {
1104 return R == AArch64::VG;
1105}
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
static Register createScratchRegisterForInstruction(MachineInstr &MI, unsigned FIOperandNum, const AArch64InstrInfo *TII)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements the BitVector class.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
uint64_t IntrinsicInst * II
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
Definition: StackMaps.cpp:195
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
StackOffset getNonLocalFrameIndexReference(const MachineFunction &MF, int FI) const override
getNonLocalFrameIndexReference - This method returns the offset used to reference a frame index locat...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
StackOffset resolveFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg, bool PreferFP, bool ForSimm) const
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=AArch64::NoRegAltName)
BitVector getStrictlyReservedRegs(const MachineFunction &MF) const
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
BitVector getReservedRegs(const MachineFunction &MF) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
bool requiresRegisterScavenging(const MachineFunction &MF) const override
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
const uint32_t * getWindowsStackProbePreservedMask() const
Stack probing calls preserve different CSRs to the normal CC.
AArch64RegisterInfo(const Triple &TT)
bool isAnyArgRegReserved(const MachineFunction &MF) const
void emitReservedArgRegCallError(const MachineFunction &MF) const
bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const
Return whether the register needs a CFI entry.
bool isStrictlyReservedReg(const MachineFunction &MF, MCRegister Reg) const
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const uint32_t * getTLSCallPreservedMask() const
const uint32_t * getNoPreservedMask() const override
Register getFrameRegister(const MachineFunction &MF) const override
bool shouldAnalyzePhysregInMachineLoopInfo(MCRegister R) const override
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
const MCPhysReg * getDarwinCalleeSavedRegs(const MachineFunction *MF) const
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
const uint32_t * SMEABISupportRoutinesCallPreservedMaskFromX0() const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const override
unsigned getLocalAddressRegister(const MachineFunction &MF) const
bool hasBasePointer(const MachineFunction &MF) const
const uint32_t * getDarwinCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
const uint32_t * getSMStartStopCallPreservedMask() const
bool useFPForScavengingIndex(const MachineFunction &MF) const override
bool cannotEliminateFrame(const MachineFunction &MF) const
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const override
void UpdateCustomCallPreservedMask(MachineFunction &MF, const uint32_t **Mask) const
std::optional< std::string > explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool isXRegisterReservedForRA(size_t i) const
unsigned getNumXRegisterReserved() const
const AArch64TargetLowering * getTargetLowering() const override
bool isCallingConvWin64(CallingConv::ID CC) const
bool isXRegCustomCalleeSaved(size_t i) const
bool isXRegisterReserved(size_t i) const
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value.
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Diagnostic information for unsupported feature in backend.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:264
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:340
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:678
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MCSubRegIterator enumerates all sub-registers of Reg.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
int64_t getLocalFrameSize() const
Get the size of the local object blob.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
uint32_t * allocateRegMask()
Allocate and initialize a register mask with NumRegister bits.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:696
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
int64_t getFixed() const
Returns the fixed component of the stack.
Definition: TypeSize.h:49
TargetOptions Options
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
unsigned getID() const
Return the register class ID number.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Definition: Triple.h:558
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:719
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
@ AArch64_VectorCall
Used between AArch64 Advanced SIMD functions.
Definition: CallingConv.h:221
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
@ AArch64_SVE_VectorCall
Used between AArch64 SVE functions.
Definition: CallingConv.h:224
@ CFGuard_Check
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
Definition: CallingConv.h:82
@ PreserveMost
Used for runtime calls that preserves most registers.
Definition: CallingConv.h:63
@ AnyReg
OBSOLETED - Used for stack based JavaScript calls.
Definition: CallingConv.h:60
@ AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2
Preserve X2-X15, X19-X29, SP, Z0-Z31, P0-P15.
Definition: CallingConv.h:241
@ CXX_FAST_TLS
Used for access functions.
Definition: CallingConv.h:72
@ AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0
Preserve X0-X13, X19-X29, SP, Z0-Z31, P0-P15.
Definition: CallingConv.h:238
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
Definition: CallingConv.h:50
@ AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1
Preserve X1-X15, X19-X29, SP, Z0-Z31, P0-P15.
Definition: CallingConv.h:271
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
Definition: CallingConv.h:66
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ PreserveNone
Used for runtime calls that preserves none general registers.
Definition: CallingConv.h:90
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Definition: CallingConv.h:76
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:159
@ SwiftTail
This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...
Definition: CallingConv.h:87
@ GRAAL
Used by GraalVM. Two additional registers are reserved.
Definition: CallingConv.h:255
@ ARM64EC_Thunk_X64
Calling convention used in the ARM64EC ABI to implement calls between x64 code and thunks.
Definition: CallingConv.h:260
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
@ Done
Definition: Threading.h:61
@ AArch64FrameOffsetIsLegal
Offset is legal.
@ AArch64FrameOffsetCanUpdate
Offset can apply, at least partly.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1729
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:159
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1879