|
LLVM 23.0.0git
|
#include "AArch64RegisterInfo.h"#include "AArch64FrameLowering.h"#include "AArch64InstrInfo.h"#include "AArch64MachineFunctionInfo.h"#include "AArch64SMEAttributes.h"#include "AArch64Subtarget.h"#include "MCTargetDesc/AArch64AddressingModes.h"#include "MCTargetDesc/AArch64InstPrinter.h"#include "llvm/ADT/BitVector.h"#include "llvm/BinaryFormat/Dwarf.h"#include "llvm/CodeGen/LiveRegMatrix.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/RegisterScavenging.h"#include "llvm/CodeGen/TargetFrameLowering.h"#include "llvm/IR/DebugInfoMetadata.h"#include "llvm/IR/DiagnosticInfo.h"#include "llvm/IR/Function.h"#include "llvm/Target/TargetOptions.h"#include "llvm/TargetParser/Triple.h"#include "AArch64GenCallingConv.inc"#include "AArch64GenRegisterInfo.inc"Go to the source code of this file.
Macros | |
| #define | GET_CC_REGISTER_LISTS |
| #define | GET_REGINFO_TARGET_DESC |
Functions | |
| static Register | createScratchRegisterForInstruction (MachineInstr &MI, unsigned FIOperandNum, const AArch64InstrInfo *TII) |
| static bool | HandleDestructivePredicateHint (Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const VirtRegMap *VRM, const MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const AArch64Subtarget &ST, const LiveRegMatrix *Matrix) |
| #define GET_CC_REGISTER_LISTS |
Definition at line 38 of file AArch64RegisterInfo.cpp.
| #define GET_REGINFO_TARGET_DESC |
Definition at line 40 of file AArch64RegisterInfo.cpp.
|
static |
Definition at line 926 of file AArch64RegisterInfo.cpp.
References assert(), MI, and TII.
Referenced by llvm::AArch64RegisterInfo::eliminateFrameIndex().
|
static |
Definition at line 1118 of file AArch64RegisterInfo.cpp.
References A(), llvm::SmallVectorImpl< T >::append(), B(), llvm::ArrayRef< T >::begin(), contains(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::contains(), llvm::MachineRegisterInfo::def_empty(), llvm::AArch64::DestructiveInstTypeMask, llvm::AArch64::DestructivePredicate, llvm::ArrayRef< T >::end(), llvm::MachineRegisterInfo::getCalleeSavedRegs(), llvm::MachineRegisterInfo::getOneDef(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getParent(), llvm::VirtRegMap::getPhys(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::hasOneDef(), I, llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::Register::isValid(), llvm::Register::isVirtual(), Matrix, llvm::ArrayRef< T >::size(), llvm::stable_sort(), and TII.
Referenced by llvm::AArch64RegisterInfo::getRegAllocationHints().