LLVM  14.0.0git
HexagonFrameLowering.cpp
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1 //===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "HexagonFrameLowering.h"
11 #include "HexagonBlockRanges.h"
12 #include "HexagonInstrInfo.h"
14 #include "HexagonRegisterInfo.h"
15 #include "HexagonSubtarget.h"
16 #include "HexagonTargetMachine.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/None.h"
21 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/SetVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/SmallVector.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/MC/MCDwarf.h"
46 #include "llvm/MC/MCRegisterInfo.h"
47 #include "llvm/Pass.h"
48 #include "llvm/Support/CodeGen.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/Debug.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <cstdint>
60 #include <iterator>
61 #include <limits>
62 #include <map>
63 #include <utility>
64 #include <vector>
65 
66 #define DEBUG_TYPE "hexagon-pei"
67 
68 // Hexagon stack frame layout as defined by the ABI:
69 //
70 // Incoming arguments
71 // passed via stack
72 // |
73 // |
74 // SP during function's FP during function's |
75 // +-- runtime (top of stack) runtime (bottom) --+ |
76 // | | |
77 // --++---------------------+------------------+-----------------++-+-------
78 // | parameter area for | variable-size | fixed-size |LR| arg
79 // | called functions | local objects | local objects |FP|
80 // --+----------------------+------------------+-----------------+--+-------
81 // <- size known -> <- size unknown -> <- size known ->
82 //
83 // Low address High address
84 //
85 // <--- stack growth
86 //
87 //
88 // - In any circumstances, the outgoing function arguments are always accessi-
89 // ble using the SP, and the incoming arguments are accessible using the FP.
90 // - If the local objects are not aligned, they can always be accessed using
91 // the FP.
92 // - If there are no variable-sized objects, the local objects can always be
93 // accessed using the SP, regardless whether they are aligned or not. (The
94 // alignment padding will be at the bottom of the stack (highest address),
95 // and so the offset with respect to the SP will be known at the compile-
96 // -time.)
97 //
98 // The only complication occurs if there are both, local aligned objects, and
99 // dynamically allocated (variable-sized) objects. The alignment pad will be
100 // placed between the FP and the local objects, thus preventing the use of the
101 // FP to access the local objects. At the same time, the variable-sized objects
102 // will be between the SP and the local objects, thus introducing an unknown
103 // distance from the SP to the locals.
104 //
105 // To avoid this problem, a new register is created that holds the aligned
106 // address of the bottom of the stack, referred in the sources as AP (aligned
107 // pointer). The AP will be equal to "FP-p", where "p" is the smallest pad
108 // that aligns AP to the required boundary (a maximum of the alignments of
109 // all stack objects, fixed- and variable-sized). All local objects[1] will
110 // then use AP as the base pointer.
111 // [1] The exception is with "fixed" stack objects. "Fixed" stack objects get
112 // their name from being allocated at fixed locations on the stack, relative
113 // to the FP. In the presence of dynamic allocation and local alignment, such
114 // objects can only be accessed through the FP.
115 //
116 // Illustration of the AP:
117 // FP --+
118 // |
119 // ---------------+---------------------+-----+-----------------------++-+--
120 // Rest of the | Local stack objects | Pad | Fixed stack objects |LR|
121 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
122 // ---------------+---------------------+-----+-----------------+-----+--+--
123 // |<-- Multiple of the -->|
124 // stack alignment +-- AP
125 //
126 // The AP is set up at the beginning of the function. Since it is not a dedi-
127 // cated (reserved) register, it needs to be kept live throughout the function
128 // to be available as the base register for local object accesses.
129 // Normally, an address of a stack objects is obtained by a pseudo-instruction
130 // PS_fi. To access local objects with the AP register present, a different
131 // pseudo-instruction needs to be used: PS_fia. The PS_fia takes one extra
132 // argument compared to PS_fi: the first input register is the AP register.
133 // This keeps the register live between its definition and its uses.
134 
135 // The AP register is originally set up using pseudo-instruction PS_aligna:
136 // AP = PS_aligna A
137 // where
138 // A - required stack alignment
139 // The alignment value must be the maximum of all alignments required by
140 // any stack object.
141 
142 // The dynamic allocation uses a pseudo-instruction PS_alloca:
143 // Rd = PS_alloca Rs, A
144 // where
145 // Rd - address of the allocated space
146 // Rs - minimum size (the actual allocated can be larger to accommodate
147 // alignment)
148 // A - required alignment
149 
150 using namespace llvm;
151 
152 static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
153  cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
154 
155 static cl::opt<unsigned> NumberScavengerSlots("number-scavenger-slots",
156  cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2),
158 
159 static cl::opt<int> SpillFuncThreshold("spill-func-threshold",
160  cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"),
162 
163 static cl::opt<int> SpillFuncThresholdOs("spill-func-threshold-Os",
164  cl::Hidden, cl::desc("Specify Os spill func threshold"),
166 
167 static cl::opt<bool> EnableStackOVFSanitizer("enable-stackovf-sanitizer",
168  cl::Hidden, cl::desc("Enable runtime checks for stack overflow."),
169  cl::init(false), cl::ZeroOrMore);
170 
171 static cl::opt<bool> EnableShrinkWrapping("hexagon-shrink-frame",
173  cl::desc("Enable stack frame shrink wrapping"));
174 
175 static cl::opt<unsigned> ShrinkLimit("shrink-frame-limit",
177  cl::desc("Max count of stack frame shrink-wraps"));
178 
179 static cl::opt<bool> EnableSaveRestoreLong("enable-save-restore-long",
180  cl::Hidden, cl::desc("Enable long calls for save-restore stubs."),
181  cl::init(false), cl::ZeroOrMore);
182 
183 static cl::opt<bool> EliminateFramePointer("hexagon-fp-elim", cl::init(true),
184  cl::Hidden, cl::desc("Refrain from using FP whenever possible"));
185 
186 static cl::opt<bool> OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden,
187  cl::init(true), cl::desc("Optimize spill slots"));
188 
189 #ifndef NDEBUG
190 static cl::opt<unsigned> SpillOptMax("spill-opt-max", cl::Hidden,
192 static unsigned SpillOptCount = 0;
193 #endif
194 
195 namespace llvm {
196 
199 
200 } // end namespace llvm
201 
202 namespace {
203 
204  class HexagonCallFrameInformation : public MachineFunctionPass {
205  public:
206  static char ID;
207 
208  HexagonCallFrameInformation() : MachineFunctionPass(ID) {
211  }
212 
213  bool runOnMachineFunction(MachineFunction &MF) override;
214 
215  MachineFunctionProperties getRequiredProperties() const override {
218  }
219  };
220 
222 
223 } // end anonymous namespace
224 
225 bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
226  auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
227  bool NeedCFI = MF.needsFrameMoves();
228 
229  if (!NeedCFI)
230  return false;
231  HFI.insertCFIInstructions(MF);
232  return true;
233 }
234 
235 INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi",
236  "Hexagon call frame information", false, false)
237 
239  return new HexagonCallFrameInformation();
240 }
241 
242 /// Map a register pair Reg to the subregister that has the greater "number",
243 /// i.e. D3 (aka R7:6) will be mapped to R7, etc.
244 static unsigned getMax32BitSubRegister(unsigned Reg,
245  const TargetRegisterInfo &TRI,
246  bool hireg = true) {
247  if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
248  return Reg;
249 
250  unsigned RegNo = 0;
251  for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
252  if (hireg) {
253  if (*SubRegs > RegNo)
254  RegNo = *SubRegs;
255  } else {
256  if (!RegNo || *SubRegs < RegNo)
257  RegNo = *SubRegs;
258  }
259  }
260  return RegNo;
261 }
262 
263 /// Returns the callee saved register with the largest id in the vector.
265  const TargetRegisterInfo &TRI) {
266  static_assert(Hexagon::R1 > 0,
267  "Assume physical registers are encoded as positive integers");
268  if (CSI.empty())
269  return 0;
270 
271  unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
272  for (unsigned I = 1, E = CSI.size(); I < E; ++I) {
273  unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);
274  if (Reg > Max)
275  Max = Reg;
276  }
277  return Max;
278 }
279 
280 /// Checks if the basic block contains any instruction that needs a stack
281 /// frame to be already in place.
282 static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
283  const HexagonRegisterInfo &HRI) {
284  for (const MachineInstr &MI : MBB) {
285  if (MI.isCall())
286  return true;
287  unsigned Opc = MI.getOpcode();
288  switch (Opc) {
289  case Hexagon::PS_alloca:
290  case Hexagon::PS_aligna:
291  return true;
292  default:
293  break;
294  }
295  // Check individual operands.
296  for (const MachineOperand &MO : MI.operands()) {
297  // While the presence of a frame index does not prove that a stack
298  // frame will be required, all frame indexes should be within alloc-
299  // frame/deallocframe. Otherwise, the code that translates a frame
300  // index into an offset would have to be aware of the placement of
301  // the frame creation/destruction instructions.
302  if (MO.isFI())
303  return true;
304  if (MO.isReg()) {
305  Register R = MO.getReg();
306  // Virtual registers will need scavenging, which then may require
307  // a stack slot.
308  if (R.isVirtual())
309  return true;
310  for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
311  if (CSR[*S])
312  return true;
313  continue;
314  }
315  if (MO.isRegMask()) {
316  // A regmask would normally have all callee-saved registers marked
317  // as preserved, so this check would not be needed, but in case of
318  // ever having other regmasks (for other calling conventions),
319  // make sure they would be processed correctly.
320  const uint32_t *BM = MO.getRegMask();
321  for (int x = CSR.find_first(); x >= 0; x = CSR.find_next(x)) {
322  unsigned R = x;
323  // If this regmask does not preserve a CSR, a frame will be needed.
324  if (!(BM[R/32] & (1u << (R%32))))
325  return true;
326  }
327  }
328  }
329  }
330  return false;
331 }
332 
333  /// Returns true if MBB has a machine instructions that indicates a tail call
334  /// in the block.
335 static bool hasTailCall(const MachineBasicBlock &MBB) {
337  if (I == MBB.end())
338  return false;
339  unsigned RetOpc = I->getOpcode();
340  return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;
341 }
342 
343 /// Returns true if MBB contains an instruction that returns.
344 static bool hasReturn(const MachineBasicBlock &MBB) {
345  for (const MachineInstr &MI : MBB.terminators())
346  if (MI.isReturn())
347  return true;
348  return false;
349 }
350 
351 /// Returns the "return" instruction from this block, or nullptr if there
352 /// isn't any.
354  for (auto &I : MBB)
355  if (I.isReturn())
356  return &I;
357  return nullptr;
358 }
359 
360 static bool isRestoreCall(unsigned Opc) {
361  switch (Opc) {
362  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
363  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
364  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
365  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
366  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
367  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
368  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
369  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
370  return true;
371  }
372  return false;
373 }
374 
375 static inline bool isOptNone(const MachineFunction &MF) {
376  return MF.getFunction().hasOptNone() ||
378 }
379 
380 static inline bool isOptSize(const MachineFunction &MF) {
381  const Function &F = MF.getFunction();
382  return F.hasOptSize() && !F.hasMinSize();
383 }
384 
385 static inline bool isMinSize(const MachineFunction &MF) {
386  return MF.getFunction().hasMinSize();
387 }
388 
389 /// Implements shrink-wrapping of the stack frame. By default, stack frame
390 /// is created in the function entry block, and is cleaned up in every block
391 /// that returns. This function finds alternate blocks: one for the frame
392 /// setup (prolog) and one for the cleanup (epilog).
393 void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
394  MachineBasicBlock *&PrologB, MachineBasicBlock *&EpilogB) const {
395  static unsigned ShrinkCounter = 0;
396 
398  MF.getFunction().isVarArg())
399  return;
400  if (ShrinkLimit.getPosition()) {
401  if (ShrinkCounter >= ShrinkLimit)
402  return;
403  ShrinkCounter++;
404  }
405 
406  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
407 
409  MDT.runOnMachineFunction(MF);
411  MPT.runOnMachineFunction(MF);
412 
413  using UnsignedMap = DenseMap<unsigned, unsigned>;
415 
416  UnsignedMap RPO;
417  RPOTType RPOT(&MF);
418  unsigned RPON = 0;
419  for (auto &I : RPOT)
420  RPO[I->getNumber()] = RPON++;
421 
422  // Don't process functions that have loops, at least for now. Placement
423  // of prolog and epilog must take loop structure into account. For simpli-
424  // city don't do it right now.
425  for (auto &I : MF) {
426  unsigned BN = RPO[I.getNumber()];
427  for (MachineBasicBlock *Succ : I.successors())
428  // If found a back-edge, return.
429  if (RPO[Succ->getNumber()] <= BN)
430  return;
431  }
432 
433  // Collect the set of blocks that need a stack frame to execute. Scan
434  // each block for uses/defs of callee-saved registers, calls, etc.
436  BitVector CSR(Hexagon::NUM_TARGET_REGS);
437  for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
438  for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S)
439  CSR[*S] = true;
440 
441  for (auto &I : MF)
442  if (needsStackFrame(I, CSR, HRI))
443  SFBlocks.push_back(&I);
444 
445  LLVM_DEBUG({
446  dbgs() << "Blocks needing SF: {";
447  for (auto &B : SFBlocks)
448  dbgs() << " " << printMBBReference(*B);
449  dbgs() << " }\n";
450  });
451  // No frame needed?
452  if (SFBlocks.empty())
453  return;
454 
455  // Pick a common dominator and a common post-dominator.
456  MachineBasicBlock *DomB = SFBlocks[0];
457  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
458  DomB = MDT.findNearestCommonDominator(DomB, SFBlocks[i]);
459  if (!DomB)
460  break;
461  }
462  MachineBasicBlock *PDomB = SFBlocks[0];
463  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
464  PDomB = MPT.findNearestCommonDominator(PDomB, SFBlocks[i]);
465  if (!PDomB)
466  break;
467  }
468  LLVM_DEBUG({
469  dbgs() << "Computed dom block: ";
470  if (DomB)
471  dbgs() << printMBBReference(*DomB);
472  else
473  dbgs() << "<null>";
474  dbgs() << ", computed pdom block: ";
475  if (PDomB)
476  dbgs() << printMBBReference(*PDomB);
477  else
478  dbgs() << "<null>";
479  dbgs() << "\n";
480  });
481  if (!DomB || !PDomB)
482  return;
483 
484  // Make sure that DomB dominates PDomB and PDomB post-dominates DomB.
485  if (!MDT.dominates(DomB, PDomB)) {
486  LLVM_DEBUG(dbgs() << "Dom block does not dominate pdom block\n");
487  return;
488  }
489  if (!MPT.dominates(PDomB, DomB)) {
490  LLVM_DEBUG(dbgs() << "PDom block does not post-dominate dom block\n");
491  return;
492  }
493 
494  // Finally, everything seems right.
495  PrologB = DomB;
496  EpilogB = PDomB;
497 }
498 
499 /// Perform most of the PEI work here:
500 /// - saving/restoring of the callee-saved registers,
501 /// - stack frame creation and destruction.
502 /// Normally, this work is distributed among various functions, but doing it
503 /// in one place allows shrink-wrapping of the stack frame.
505  MachineBasicBlock &MBB) const {
506  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
507 
508  MachineFrameInfo &MFI = MF.getFrameInfo();
509  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
510 
511  MachineBasicBlock *PrologB = &MF.front(), *EpilogB = nullptr;
513  findShrunkPrologEpilog(MF, PrologB, EpilogB);
514 
515  bool PrologueStubs = false;
516  insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs);
517  insertPrologueInBlock(*PrologB, PrologueStubs);
518  updateEntryPaths(MF, *PrologB);
519 
520  if (EpilogB) {
521  insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
522  insertEpilogueInBlock(*EpilogB);
523  } else {
524  for (auto &B : MF)
525  if (B.isReturnBlock())
526  insertCSRRestoresInBlock(B, CSI, HRI);
527 
528  for (auto &B : MF)
529  if (B.isReturnBlock())
530  insertEpilogueInBlock(B);
531 
532  for (auto &B : MF) {
533  if (B.empty())
534  continue;
535  MachineInstr *RetI = getReturn(B);
536  if (!RetI || isRestoreCall(RetI->getOpcode()))
537  continue;
538  for (auto &R : CSI)
539  RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
540  }
541  }
542 
543  if (EpilogB) {
544  // If there is an epilog block, it may not have a return instruction.
545  // In such case, we need to add the callee-saved registers as live-ins
546  // in all blocks on all paths from the epilog to any return block.
547  unsigned MaxBN = MF.getNumBlockIDs();
548  BitVector DoneT(MaxBN+1), DoneF(MaxBN+1), Path(MaxBN+1);
549  updateExitPaths(*EpilogB, *EpilogB, DoneT, DoneF, Path);
550  }
551 }
552 
553 /// Returns true if the target can safely skip saving callee-saved registers
554 /// for noreturn nounwind functions.
556  const MachineFunction &MF) const {
557  const auto &F = MF.getFunction();
558  assert(F.hasFnAttribute(Attribute::NoReturn) &&
559  F.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
560  !F.getFunction().hasFnAttribute(Attribute::UWTable));
561  (void)F;
562 
563  // No need to save callee saved registers if the function does not return.
564  return MF.getSubtarget<HexagonSubtarget>().noreturnStackElim();
565 }
566 
567 // Helper function used to determine when to eliminate the stack frame for
568 // functions marked as noreturn and when the noreturn-stack-elim options are
569 // specified. When both these conditions are true, then a FP may not be needed
570 // if the function makes a call. It is very similar to enableCalleeSaveSkip,
571 // but it used to check if the allocframe can be eliminated as well.
572 static bool enableAllocFrameElim(const MachineFunction &MF) {
573  const auto &F = MF.getFunction();
574  const auto &MFI = MF.getFrameInfo();
575  const auto &HST = MF.getSubtarget<HexagonSubtarget>();
576  assert(!MFI.hasVarSizedObjects() &&
577  !HST.getRegisterInfo()->hasStackRealignment(MF));
578  return F.hasFnAttribute(Attribute::NoReturn) &&
579  F.hasFnAttribute(Attribute::NoUnwind) &&
580  !F.hasFnAttribute(Attribute::UWTable) && HST.noreturnStackElim() &&
581  MFI.getStackSize() == 0;
582 }
583 
584 void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
585  bool PrologueStubs) const {
586  MachineFunction &MF = *MBB.getParent();
587  MachineFrameInfo &MFI = MF.getFrameInfo();
588  auto &HST = MF.getSubtarget<HexagonSubtarget>();
589  auto &HII = *HST.getInstrInfo();
590  auto &HRI = *HST.getRegisterInfo();
591 
592  Align MaxAlign = std::max(MFI.getMaxAlign(), getStackAlign());
593 
594  // Calculate the total stack frame size.
595  // Get the number of bytes to allocate from the FrameInfo.
596  unsigned FrameSize = MFI.getStackSize();
597  // Round up the max call frame size to the max alignment on the stack.
598  unsigned MaxCFA = alignTo(MFI.getMaxCallFrameSize(), MaxAlign);
599  MFI.setMaxCallFrameSize(MaxCFA);
600 
601  FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign);
602  MFI.setStackSize(FrameSize);
603 
604  bool AlignStack = (MaxAlign > getStackAlign());
605 
606  // Get the number of bytes to allocate from the FrameInfo.
607  unsigned NumBytes = MFI.getStackSize();
608  unsigned SP = HRI.getStackRegister();
609  unsigned MaxCF = MFI.getMaxCallFrameSize();
611 
613  for (auto &MBB : MF)
614  for (auto &MI : MBB)
615  if (MI.getOpcode() == Hexagon::PS_alloca)
616  AdjustRegs.push_back(&MI);
617 
618  for (auto MI : AdjustRegs) {
619  assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");
620  expandAlloca(MI, HII, SP, MaxCF);
621  MI->eraseFromParent();
622  }
623 
624  DebugLoc dl = MBB.findDebugLoc(InsertPt);
625 
626  if (MF.getFunction().isVarArg() &&
627  MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) {
628  // Calculate the size of register saved area.
629  int NumVarArgRegs = 6 - FirstVarArgSavedReg;
630  int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0)
631  ? NumVarArgRegs * 4
632  : NumVarArgRegs * 4 + 4;
633  if (RegisterSavedAreaSizePlusPadding > 0) {
634  // Decrement the stack pointer by size of register saved area plus
635  // padding if any.
636  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
637  .addReg(SP)
638  .addImm(-RegisterSavedAreaSizePlusPadding)
640 
641  int NumBytes = 0;
642  // Copy all the named arguments below register saved area.
643  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
644  for (int i = HMFI.getFirstNamedArgFrameIndex(),
645  e = HMFI.getLastNamedArgFrameIndex(); i >= e; --i) {
646  uint64_t ObjSize = MFI.getObjectSize(i);
647  Align ObjAlign = MFI.getObjectAlign(i);
648 
649  // Determine the kind of load/store that should be used.
650  unsigned LDOpc, STOpc;
651  uint64_t OpcodeChecker = ObjAlign.value();
652 
653  // Handle cases where alignment of an object is > its size.
654  if (ObjAlign > ObjSize) {
655  if (ObjSize <= 1)
656  OpcodeChecker = 1;
657  else if (ObjSize <= 2)
658  OpcodeChecker = 2;
659  else if (ObjSize <= 4)
660  OpcodeChecker = 4;
661  else if (ObjSize > 4)
662  OpcodeChecker = 8;
663  }
664 
665  switch (OpcodeChecker) {
666  case 1:
667  LDOpc = Hexagon::L2_loadrb_io;
668  STOpc = Hexagon::S2_storerb_io;
669  break;
670  case 2:
671  LDOpc = Hexagon::L2_loadrh_io;
672  STOpc = Hexagon::S2_storerh_io;
673  break;
674  case 4:
675  LDOpc = Hexagon::L2_loadri_io;
676  STOpc = Hexagon::S2_storeri_io;
677  break;
678  case 8:
679  default:
680  LDOpc = Hexagon::L2_loadrd_io;
681  STOpc = Hexagon::S2_storerd_io;
682  break;
683  }
684 
685  unsigned RegUsed = LDOpc == Hexagon::L2_loadrd_io ? Hexagon::D3
686  : Hexagon::R6;
687  int LoadStoreCount = ObjSize / OpcodeChecker;
688 
689  if (ObjSize % OpcodeChecker)
690  ++LoadStoreCount;
691 
692  // Get the start location of the load. NumBytes is basically the
693  // offset from the stack pointer of previous function, which would be
694  // the caller in this case, as this function has variable argument
695  // list.
696  if (NumBytes != 0)
697  NumBytes = alignTo(NumBytes, ObjAlign);
698 
699  int Count = 0;
700  while (Count < LoadStoreCount) {
701  // Load the value of the named argument on stack.
702  BuildMI(MBB, InsertPt, dl, HII.get(LDOpc), RegUsed)
703  .addReg(SP)
704  .addImm(RegisterSavedAreaSizePlusPadding +
705  ObjAlign.value() * Count + NumBytes)
707 
708  // Store it below the register saved area plus padding.
709  BuildMI(MBB, InsertPt, dl, HII.get(STOpc))
710  .addReg(SP)
711  .addImm(ObjAlign.value() * Count + NumBytes)
712  .addReg(RegUsed)
714 
715  Count++;
716  }
717  NumBytes += MFI.getObjectSize(i);
718  }
719 
720  // Make NumBytes 8 byte aligned
721  NumBytes = alignTo(NumBytes, 8);
722 
723  // If the number of registers having variable arguments is odd,
724  // leave 4 bytes of padding to get to the location where first
725  // variable argument which was passed through register was copied.
726  NumBytes = (NumVarArgRegs % 2 == 0) ? NumBytes : NumBytes + 4;
727 
728  for (int j = FirstVarArgSavedReg, i = 0; j < 6; ++j, ++i) {
729  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_storeri_io))
730  .addReg(SP)
731  .addImm(NumBytes + 4 * i)
732  .addReg(Hexagon::R0 + j)
734  }
735  }
736  }
737 
738  if (hasFP(MF)) {
739  insertAllocframe(MBB, InsertPt, NumBytes);
740  if (AlignStack) {
741  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
742  .addReg(SP)
743  .addImm(-int64_t(MaxAlign.value()));
744  }
745  // If the stack-checking is enabled, and we spilled the callee-saved
746  // registers inline (i.e. did not use a spill function), then call
747  // the stack checker directly.
748  if (EnableStackOVFSanitizer && !PrologueStubs)
749  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
750  .addExternalSymbol("__runtime_stack_check");
751  } else if (NumBytes > 0) {
752  assert(alignTo(NumBytes, 8) == NumBytes);
753  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
754  .addReg(SP)
755  .addImm(-int(NumBytes));
756  }
757 }
758 
759 void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
760  MachineFunction &MF = *MBB.getParent();
761  auto &HST = MF.getSubtarget<HexagonSubtarget>();
762  auto &HII = *HST.getInstrInfo();
763  auto &HRI = *HST.getRegisterInfo();
764  unsigned SP = HRI.getStackRegister();
765 
767  DebugLoc dl = MBB.findDebugLoc(InsertPt);
768 
769  if (!hasFP(MF)) {
770  MachineFrameInfo &MFI = MF.getFrameInfo();
771  unsigned NumBytes = MFI.getStackSize();
772  if (MF.getFunction().isVarArg() &&
773  MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) {
774  // On Hexagon Linux, deallocate the stack for the register saved area.
775  int NumVarArgRegs = 6 - FirstVarArgSavedReg;
776  int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ?
777  (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4);
778  NumBytes += RegisterSavedAreaSizePlusPadding;
779  }
780  if (NumBytes) {
781  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
782  .addReg(SP)
783  .addImm(NumBytes);
784  }
785  return;
786  }
787 
788  MachineInstr *RetI = getReturn(MBB);
789  unsigned RetOpc = RetI ? RetI->getOpcode() : 0;
790 
791  // Handle EH_RETURN.
792  if (RetOpc == Hexagon::EH_RETURN_JMPR) {
793  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
794  .addDef(Hexagon::D15)
795  .addReg(Hexagon::R30);
796  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP)
797  .addReg(SP)
798  .addReg(Hexagon::R28);
799  return;
800  }
801 
802  // Check for RESTORE_DEALLOC_RET* tail call. Don't emit an extra dealloc-
803  // frame instruction if we encounter it.
804  if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4 ||
805  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC ||
806  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT ||
807  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC) {
808  MachineBasicBlock::iterator It = RetI;
809  ++It;
810  // Delete all instructions after the RESTORE (except labels).
811  while (It != MBB.end()) {
812  if (!It->isLabel())
813  It = MBB.erase(It);
814  else
815  ++It;
816  }
817  return;
818  }
819 
820  // It is possible that the restoring code is a call to a library function.
821  // All of the restore* functions include "deallocframe", so we need to make
822  // sure that we don't add an extra one.
823  bool NeedsDeallocframe = true;
824  if (!MBB.empty() && InsertPt != MBB.begin()) {
825  MachineBasicBlock::iterator PrevIt = std::prev(InsertPt);
826  unsigned COpc = PrevIt->getOpcode();
827  if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 ||
828  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC ||
829  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT ||
830  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC ||
831  COpc == Hexagon::PS_call_nr || COpc == Hexagon::PS_callr_nr)
832  NeedsDeallocframe = false;
833  }
834 
836  !MF.getFunction().isVarArg()) {
837  if (!NeedsDeallocframe)
838  return;
839  // If the returning instruction is PS_jmpret, replace it with
840  // dealloc_return, otherwise just add deallocframe. The function
841  // could be returning via a tail call.
842  if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) {
843  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
844  .addDef(Hexagon::D15)
845  .addReg(Hexagon::R30);
846  return;
847  }
848  unsigned NewOpc = Hexagon::L4_return;
849  MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc))
850  .addDef(Hexagon::D15)
851  .addReg(Hexagon::R30);
852  // Transfer the function live-out registers.
853  NewI->copyImplicitOps(MF, *RetI);
854  MBB.erase(RetI);
855  } else {
856  // L2_deallocframe instruction after it.
857  // Calculate the size of register saved area.
858  int NumVarArgRegs = 6 - FirstVarArgSavedReg;
859  int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ?
860  (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4);
861 
864  : std::prev(Term);
865  if (I == MBB.end() ||
866  (I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT &&
867  I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC &&
868  I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 &&
869  I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC))
870  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
871  .addDef(Hexagon::D15)
872  .addReg(Hexagon::R30);
873  if (RegisterSavedAreaSizePlusPadding != 0)
874  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
875  .addReg(SP)
876  .addImm(RegisterSavedAreaSizePlusPadding);
877  }
878 }
879 
880 void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB,
881  MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const {
882  MachineFunction &MF = *MBB.getParent();
883  auto &HST = MF.getSubtarget<HexagonSubtarget>();
884  auto &HII = *HST.getInstrInfo();
885  auto &HRI = *HST.getRegisterInfo();
886 
887  // Check for overflow.
888  // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
889  const unsigned int ALLOCFRAME_MAX = 16384;
890 
891  // Create a dummy memory operand to avoid allocframe from being treated as
892  // a volatile memory reference.
895 
896  DebugLoc dl = MBB.findDebugLoc(InsertPt);
897  unsigned SP = HRI.getStackRegister();
898 
899  if (NumBytes >= ALLOCFRAME_MAX) {
900  // Emit allocframe(#0).
901  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
902  .addDef(SP)
903  .addReg(SP)
904  .addImm(0)
905  .addMemOperand(MMO);
906 
907  // Subtract the size from the stack pointer.
908  unsigned SP = HRI.getStackRegister();
909  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
910  .addReg(SP)
911  .addImm(-int(NumBytes));
912  } else {
913  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
914  .addDef(SP)
915  .addReg(SP)
916  .addImm(NumBytes)
917  .addMemOperand(MMO);
918  }
919 }
920 
921 void HexagonFrameLowering::updateEntryPaths(MachineFunction &MF,
922  MachineBasicBlock &SaveB) const {
923  SetVector<unsigned> Worklist;
924 
925  MachineBasicBlock &EntryB = MF.front();
926  Worklist.insert(EntryB.getNumber());
927 
928  unsigned SaveN = SaveB.getNumber();
929  auto &CSI = MF.getFrameInfo().getCalleeSavedInfo();
930 
931  for (unsigned i = 0; i < Worklist.size(); ++i) {
932  unsigned BN = Worklist[i];
934  for (auto &R : CSI)
935  if (!MBB.isLiveIn(R.getReg()))
936  MBB.addLiveIn(R.getReg());
937  if (BN != SaveN)
938  for (auto &SB : MBB.successors())
939  Worklist.insert(SB->getNumber());
940  }
941 }
942 
943 bool HexagonFrameLowering::updateExitPaths(MachineBasicBlock &MBB,
944  MachineBasicBlock &RestoreB, BitVector &DoneT, BitVector &DoneF,
945  BitVector &Path) const {
946  assert(MBB.getNumber() >= 0);
947  unsigned BN = MBB.getNumber();
948  if (Path[BN] || DoneF[BN])
949  return false;
950  if (DoneT[BN])
951  return true;
952 
953  auto &CSI = MBB.getParent()->getFrameInfo().getCalleeSavedInfo();
954 
955  Path[BN] = true;
956  bool ReachedExit = false;
957  for (auto &SB : MBB.successors())
958  ReachedExit |= updateExitPaths(*SB, RestoreB, DoneT, DoneF, Path);
959 
960  if (!MBB.empty() && MBB.back().isReturn()) {
961  // Add implicit uses of all callee-saved registers to the reached
962  // return instructions. This is to prevent the anti-dependency breaker
963  // from renaming these registers.
964  MachineInstr &RetI = MBB.back();
965  if (!isRestoreCall(RetI.getOpcode()))
966  for (auto &R : CSI)
967  RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
968  ReachedExit = true;
969  }
970 
971  // We don't want to add unnecessary live-ins to the restore block: since
972  // the callee-saved registers are being defined in it, the entry of the
973  // restore block cannot be on the path from the definitions to any exit.
974  if (ReachedExit && &MBB != &RestoreB) {
975  for (auto &R : CSI)
976  if (!MBB.isLiveIn(R.getReg()))
977  MBB.addLiveIn(R.getReg());
978  DoneT[BN] = true;
979  }
980  if (!ReachedExit)
981  DoneF[BN] = true;
982 
983  Path[BN] = false;
984  return ReachedExit;
985 }
986 
989  // The CFI instructions need to be inserted right after allocframe.
990  // An exception to this is a situation where allocframe is bundled
991  // with a call: then the CFI instructions need to be inserted before
992  // the packet with the allocframe+call (in case the call throws an
993  // exception).
994  auto End = B.instr_end();
995 
996  for (MachineInstr &I : B) {
997  MachineBasicBlock::iterator It = I.getIterator();
998  if (!I.isBundle()) {
999  if (I.getOpcode() == Hexagon::S2_allocframe)
1000  return std::next(It);
1001  continue;
1002  }
1003  // I is a bundle.
1004  bool HasCall = false, HasAllocFrame = false;
1005  auto T = It.getInstrIterator();
1006  while (++T != End && T->isBundled()) {
1007  if (T->getOpcode() == Hexagon::S2_allocframe)
1008  HasAllocFrame = true;
1009  else if (T->isCall())
1010  HasCall = true;
1011  }
1012  if (HasAllocFrame)
1013  return HasCall ? It : std::next(It);
1014  }
1015  return None;
1016 }
1017 
1019  for (auto &B : MF) {
1020  auto At = findCFILocation(B);
1021  if (At.hasValue())
1022  insertCFIInstructionsAt(B, At.getValue());
1023  }
1024 }
1025 
1026 void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB,
1027  MachineBasicBlock::iterator At) const {
1028  MachineFunction &MF = *MBB.getParent();
1029  MachineFrameInfo &MFI = MF.getFrameInfo();
1030  MachineModuleInfo &MMI = MF.getMMI();
1031  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1032  auto &HII = *HST.getInstrInfo();
1033  auto &HRI = *HST.getRegisterInfo();
1034 
1035  // If CFI instructions have debug information attached, something goes
1036  // wrong with the final assembly generation: the prolog_end is placed
1037  // in a wrong location.
1038  DebugLoc DL;
1039  const MCInstrDesc &CFID = HII.get(TargetOpcode::CFI_INSTRUCTION);
1040 
1041  MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
1042  bool HasFP = hasFP(MF);
1043 
1044  if (HasFP) {
1045  unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(), true);
1046  unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(), true);
1047 
1048  // Define CFA via an offset from the value of FP.
1049  //
1050  // -8 -4 0 (SP)
1051  // --+----+----+---------------------
1052  // | FP | LR | increasing addresses -->
1053  // --+----+----+---------------------
1054  // | +-- Old SP (before allocframe)
1055  // +-- New FP (after allocframe)
1056  //
1057  // MCCFIInstruction::cfiDefCfa adds the offset from the register.
1058  // MCCFIInstruction::createOffset takes the offset without sign change.
1059  auto DefCfa = MCCFIInstruction::cfiDefCfa(FrameLabel, DwFPReg, 8);
1060  BuildMI(MBB, At, DL, CFID)
1061  .addCFIIndex(MF.addFrameInst(DefCfa));
1062  // R31 (return addr) = CFA - 4
1063  auto OffR31 = MCCFIInstruction::createOffset(FrameLabel, DwRAReg, -4);
1064  BuildMI(MBB, At, DL, CFID)
1065  .addCFIIndex(MF.addFrameInst(OffR31));
1066  // R30 (frame ptr) = CFA - 8
1067  auto OffR30 = MCCFIInstruction::createOffset(FrameLabel, DwFPReg, -8);
1068  BuildMI(MBB, At, DL, CFID)
1069  .addCFIIndex(MF.addFrameInst(OffR30));
1070  }
1071 
1072  static unsigned int RegsToMove[] = {
1073  Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,
1074  Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
1075  Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
1076  Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
1077  Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9,
1078  Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13,
1079  Hexagon::NoRegister
1080  };
1081 
1082  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1083 
1084  for (unsigned i = 0; RegsToMove[i] != Hexagon::NoRegister; ++i) {
1085  unsigned Reg = RegsToMove[i];
1086  auto IfR = [Reg] (const CalleeSavedInfo &C) -> bool {
1087  return C.getReg() == Reg;
1088  };
1089  auto F = find_if(CSI, IfR);
1090  if (F == CSI.end())
1091  continue;
1092 
1093  int64_t Offset;
1094  if (HasFP) {
1095  // If the function has a frame pointer (i.e. has an allocframe),
1096  // then the CFA has been defined in terms of FP. Any offsets in
1097  // the following CFI instructions have to be defined relative
1098  // to FP, which points to the bottom of the stack frame.
1099  // The function getFrameIndexReference can still choose to use SP
1100  // for the offset calculation, so we cannot simply call it here.
1101  // Instead, get the offset (relative to the FP) directly.
1102  Offset = MFI.getObjectOffset(F->getFrameIdx());
1103  } else {
1104  Register FrameReg;
1105  Offset =
1106  getFrameIndexReference(MF, F->getFrameIdx(), FrameReg).getFixed();
1107  }
1108  // Subtract 8 to make room for R30 and R31, which are added above.
1109  Offset -= 8;
1110 
1111  if (Reg < Hexagon::D0 || Reg > Hexagon::D15) {
1112  unsigned DwarfReg = HRI.getDwarfRegNum(Reg, true);
1113  auto OffReg = MCCFIInstruction::createOffset(FrameLabel, DwarfReg,
1114  Offset);
1115  BuildMI(MBB, At, DL, CFID)
1116  .addCFIIndex(MF.addFrameInst(OffReg));
1117  } else {
1118  // Split the double regs into subregs, and generate appropriate
1119  // cfi_offsets.
1120  // The only reason, we are split double regs is, llvm-mc does not
1121  // understand paired registers for cfi_offset.
1122  // Eg .cfi_offset r1:0, -64
1123 
1124  Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);
1125  Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);
1126  unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
1127  unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
1128  auto OffHi = MCCFIInstruction::createOffset(FrameLabel, HiDwarfReg,
1129  Offset+4);
1130  BuildMI(MBB, At, DL, CFID)
1131  .addCFIIndex(MF.addFrameInst(OffHi));
1132  auto OffLo = MCCFIInstruction::createOffset(FrameLabel, LoDwarfReg,
1133  Offset);
1134  BuildMI(MBB, At, DL, CFID)
1135  .addCFIIndex(MF.addFrameInst(OffLo));
1136  }
1137  }
1138 }
1139 
1141  if (MF.getFunction().hasFnAttribute(Attribute::Naked))
1142  return false;
1143 
1144  auto &MFI = MF.getFrameInfo();
1145  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1146  bool HasExtraAlign = HRI.hasStackRealignment(MF);
1147  bool HasAlloca = MFI.hasVarSizedObjects();
1148 
1149  // Insert ALLOCFRAME if we need to or at -O0 for the debugger. Think
1150  // that this shouldn't be required, but doing so now because gcc does and
1151  // gdb can't break at the start of the function without it. Will remove if
1152  // this turns out to be a gdb bug.
1153  //
1154  if (MF.getTarget().getOptLevel() == CodeGenOpt::None)
1155  return true;
1156 
1157  // By default we want to use SP (since it's always there). FP requires
1158  // some setup (i.e. ALLOCFRAME).
1159  // Both, alloca and stack alignment modify the stack pointer by an
1160  // undetermined value, so we need to save it at the entry to the function
1161  // (i.e. use allocframe).
1162  if (HasAlloca || HasExtraAlign)
1163  return true;
1164 
1165  if (MFI.getStackSize() > 0) {
1166  // If FP-elimination is disabled, we have to use FP at this point.
1167  const TargetMachine &TM = MF.getTarget();
1168  if (TM.Options.DisableFramePointerElim(MF) || !EliminateFramePointer)
1169  return true;
1171  return true;
1172  }
1173 
1174  const auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1175  if ((MFI.hasCalls() && !enableAllocFrameElim(MF)) || HMFI.hasClobberLR())
1176  return true;
1177 
1178  return false;
1179 }
1180 
1185 };
1186 
1187 static const char *getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType,
1188  bool Stkchk = false) {
1189  const char * V4SpillToMemoryFunctions[] = {
1190  "__save_r16_through_r17",
1191  "__save_r16_through_r19",
1192  "__save_r16_through_r21",
1193  "__save_r16_through_r23",
1194  "__save_r16_through_r25",
1195  "__save_r16_through_r27" };
1196 
1197  const char * V4SpillToMemoryStkchkFunctions[] = {
1198  "__save_r16_through_r17_stkchk",
1199  "__save_r16_through_r19_stkchk",
1200  "__save_r16_through_r21_stkchk",
1201  "__save_r16_through_r23_stkchk",
1202  "__save_r16_through_r25_stkchk",
1203  "__save_r16_through_r27_stkchk" };
1204 
1205  const char * V4SpillFromMemoryFunctions[] = {
1206  "__restore_r16_through_r17_and_deallocframe",
1207  "__restore_r16_through_r19_and_deallocframe",
1208  "__restore_r16_through_r21_and_deallocframe",
1209  "__restore_r16_through_r23_and_deallocframe",
1210  "__restore_r16_through_r25_and_deallocframe",
1211  "__restore_r16_through_r27_and_deallocframe" };
1212 
1213  const char * V4SpillFromMemoryTailcallFunctions[] = {
1214  "__restore_r16_through_r17_and_deallocframe_before_tailcall",
1215  "__restore_r16_through_r19_and_deallocframe_before_tailcall",
1216  "__restore_r16_through_r21_and_deallocframe_before_tailcall",
1217  "__restore_r16_through_r23_and_deallocframe_before_tailcall",
1218  "__restore_r16_through_r25_and_deallocframe_before_tailcall",
1219  "__restore_r16_through_r27_and_deallocframe_before_tailcall"
1220  };
1221 
1222  const char **SpillFunc = nullptr;
1223 
1224  switch(SpillType) {
1225  case SK_ToMem:
1226  SpillFunc = Stkchk ? V4SpillToMemoryStkchkFunctions
1227  : V4SpillToMemoryFunctions;
1228  break;
1229  case SK_FromMem:
1230  SpillFunc = V4SpillFromMemoryFunctions;
1231  break;
1232  case SK_FromMemTailcall:
1233  SpillFunc = V4SpillFromMemoryTailcallFunctions;
1234  break;
1235  }
1236  assert(SpillFunc && "Unknown spill kind");
1237 
1238  // Spill all callee-saved registers up to the highest register used.
1239  switch (MaxReg) {
1240  case Hexagon::R17:
1241  return SpillFunc[0];
1242  case Hexagon::R19:
1243  return SpillFunc[1];
1244  case Hexagon::R21:
1245  return SpillFunc[2];
1246  case Hexagon::R23:
1247  return SpillFunc[3];
1248  case Hexagon::R25:
1249  return SpillFunc[4];
1250  case Hexagon::R27:
1251  return SpillFunc[5];
1252  default:
1253  llvm_unreachable("Unhandled maximum callee save register");
1254  }
1255  return nullptr;
1256 }
1257 
1260  Register &FrameReg) const {
1261  auto &MFI = MF.getFrameInfo();
1262  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1263 
1264  int Offset = MFI.getObjectOffset(FI);
1265  bool HasAlloca = MFI.hasVarSizedObjects();
1266  bool HasExtraAlign = HRI.hasStackRealignment(MF);
1267  bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None;
1268 
1269  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1270  unsigned FrameSize = MFI.getStackSize();
1271  Register SP = HRI.getStackRegister();
1272  Register FP = HRI.getFrameRegister();
1273  Register AP = HMFI.getStackAlignBasePhysReg();
1274  // It may happen that AP will be absent even HasAlloca && HasExtraAlign
1275  // is true. HasExtraAlign may be set because of vector spills, without
1276  // aligned locals or aligned outgoing function arguments. Since vector
1277  // spills will ultimately be "unaligned", it is safe to use FP as the
1278  // base register.
1279  // In fact, in such a scenario the stack is actually not required to be
1280  // aligned, although it may end up being aligned anyway, since this
1281  // particular case is not easily detectable. The alignment will be
1282  // unnecessary, but not incorrect.
1283  // Unfortunately there is no quick way to verify that the above is
1284  // indeed the case (and that it's not a result of an error), so just
1285  // assume that missing AP will be replaced by FP.
1286  // (A better fix would be to rematerialize AP from FP and always align
1287  // vector spills.)
1288  if (AP == 0)
1289  AP = FP;
1290 
1291  bool UseFP = false, UseAP = false; // Default: use SP (except at -O0).
1292  // Use FP at -O0, except when there are objects with extra alignment.
1293  // That additional alignment requirement may cause a pad to be inserted,
1294  // which will make it impossible to use FP to access objects located
1295  // past the pad.
1296  if (NoOpt && !HasExtraAlign)
1297  UseFP = true;
1298  if (MFI.isFixedObjectIndex(FI) || MFI.isObjectPreAllocated(FI)) {
1299  // Fixed and preallocated objects will be located before any padding
1300  // so FP must be used to access them.
1301  UseFP |= (HasAlloca || HasExtraAlign);
1302  } else {
1303  if (HasAlloca) {
1304  if (HasExtraAlign)
1305  UseAP = true;
1306  else
1307  UseFP = true;
1308  }
1309  }
1310 
1311  // If FP was picked, then there had better be FP.
1312  bool HasFP = hasFP(MF);
1313  assert((HasFP || !UseFP) && "This function must have frame pointer");
1314 
1315  // Having FP implies allocframe. Allocframe will store extra 8 bytes:
1316  // FP/LR. If the base register is used to access an object across these
1317  // 8 bytes, then the offset will need to be adjusted by 8.
1318  //
1319  // After allocframe:
1320  // HexagonISelLowering adds 8 to ---+
1321  // the offsets of all stack-based |
1322  // arguments (*) |
1323  // |
1324  // getObjectOffset < 0 0 8 getObjectOffset >= 8
1325  // ------------------------+-----+------------------------> increasing
1326  // <local objects> |FP/LR| <input arguments> addresses
1327  // -----------------+------+-----+------------------------>
1328  // | |
1329  // SP/AP point --+ +-- FP points here (**)
1330  // somewhere on
1331  // this side of FP/LR
1332  //
1333  // (*) See LowerFormalArguments. The FP/LR is assumed to be present.
1334  // (**) *FP == old-FP. FP+0..7 are the bytes of FP/LR.
1335 
1336  // The lowering assumes that FP/LR is present, and so the offsets of
1337  // the formal arguments start at 8. If FP/LR is not there we need to
1338  // reduce the offset by 8.
1339  if (Offset > 0 && !HasFP)
1340  Offset -= 8;
1341 
1342  if (UseFP)
1343  FrameReg = FP;
1344  else if (UseAP)
1345  FrameReg = AP;
1346  else
1347  FrameReg = SP;
1348 
1349  // Calculate the actual offset in the instruction. If there is no FP
1350  // (in other words, no allocframe), then SP will not be adjusted (i.e.
1351  // there will be no SP -= FrameSize), so the frame size should not be
1352  // added to the calculated offset.
1353  int RealOffset = Offset;
1354  if (!UseFP && !UseAP)
1355  RealOffset = FrameSize+Offset;
1356  return StackOffset::getFixed(RealOffset);
1357 }
1358 
1359 bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
1360  const CSIVect &CSI, const HexagonRegisterInfo &HRI,
1361  bool &PrologueStubs) const {
1362  if (CSI.empty())
1363  return true;
1364 
1366  PrologueStubs = false;
1367  MachineFunction &MF = *MBB.getParent();
1368  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1369  auto &HII = *HST.getInstrInfo();
1370 
1371  if (useSpillFunction(MF, CSI)) {
1372  PrologueStubs = true;
1373  unsigned MaxReg = getMaxCalleeSavedReg(CSI, HRI);
1374  bool StkOvrFlowEnabled = EnableStackOVFSanitizer;
1375  const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem,
1376  StkOvrFlowEnabled);
1377  auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1378  bool IsPIC = HTM.isPositionIndependent();
1379  bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1380 
1381  // Call spill function.
1382  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1383  unsigned SpillOpc;
1384  if (StkOvrFlowEnabled) {
1385  if (LongCalls)
1386  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC
1387  : Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT;
1388  else
1389  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC
1390  : Hexagon::SAVE_REGISTERS_CALL_V4STK;
1391  } else {
1392  if (LongCalls)
1393  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC
1394  : Hexagon::SAVE_REGISTERS_CALL_V4_EXT;
1395  else
1396  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_PIC
1397  : Hexagon::SAVE_REGISTERS_CALL_V4;
1398  }
1399 
1400  MachineInstr *SaveRegsCall =
1401  BuildMI(MBB, MI, DL, HII.get(SpillOpc))
1402  .addExternalSymbol(SpillFun);
1403 
1404  // Add callee-saved registers as use.
1405  addCalleeSaveRegistersAsImpOperand(SaveRegsCall, CSI, false, true);
1406  // Add live in registers.
1407  for (const CalleeSavedInfo &I : CSI)
1408  MBB.addLiveIn(I.getReg());
1409  return true;
1410  }
1411 
1412  for (const CalleeSavedInfo &I : CSI) {
1413  unsigned Reg = I.getReg();
1414  // Add live in registers. We treat eh_return callee saved register r0 - r3
1415  // specially. They are not really callee saved registers as they are not
1416  // supposed to be killed.
1417  bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);
1418  int FI = I.getFrameIdx();
1419  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1420  HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
1421  if (IsKill)
1422  MBB.addLiveIn(Reg);
1423  }
1424  return true;
1425 }
1426 
1427 bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
1428  const CSIVect &CSI, const HexagonRegisterInfo &HRI) const {
1429  if (CSI.empty())
1430  return false;
1431 
1433  MachineFunction &MF = *MBB.getParent();
1434  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1435  auto &HII = *HST.getInstrInfo();
1436 
1437  if (useRestoreFunction(MF, CSI)) {
1438  bool HasTC = hasTailCall(MBB) || !hasReturn(MBB);
1439  unsigned MaxR = getMaxCalleeSavedReg(CSI, HRI);
1441  const char *RestoreFn = getSpillFunctionFor(MaxR, Kind);
1442  auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1443  bool IsPIC = HTM.isPositionIndependent();
1444  bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1445 
1446  // Call spill function.
1447  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc()
1448  : MBB.findDebugLoc(MBB.end());
1449  MachineInstr *DeallocCall = nullptr;
1450 
1451  if (HasTC) {
1452  unsigned RetOpc;
1453  if (LongCalls)
1454  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
1455  : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT;
1456  else
1457  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
1458  : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
1459  DeallocCall = BuildMI(MBB, MI, DL, HII.get(RetOpc))
1460  .addExternalSymbol(RestoreFn);
1461  } else {
1462  // The block has a return.
1464  assert(It->isReturn() && std::next(It) == MBB.end());
1465  unsigned RetOpc;
1466  if (LongCalls)
1467  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
1468  : Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT;
1469  else
1470  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC
1471  : Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
1472  DeallocCall = BuildMI(MBB, It, DL, HII.get(RetOpc))
1473  .addExternalSymbol(RestoreFn);
1474  // Transfer the function live-out registers.
1475  DeallocCall->copyImplicitOps(MF, *It);
1476  }
1477  addCalleeSaveRegistersAsImpOperand(DeallocCall, CSI, true, false);
1478  return true;
1479  }
1480 
1481  for (const CalleeSavedInfo &I : CSI) {
1482  unsigned Reg = I.getReg();
1483  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1484  int FI = I.getFrameIdx();
1485  HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI);
1486  }
1487 
1488  return true;
1489 }
1490 
1494  MachineInstr &MI = *I;
1495  unsigned Opc = MI.getOpcode();
1496  (void)Opc; // Silence compiler warning.
1497  assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
1498  "Cannot handle this call frame pseudo instruction");
1499  return MBB.erase(I);
1500 }
1501 
1503  MachineFunction &MF, RegScavenger *RS) const {
1504  // If this function has uses aligned stack and also has variable sized stack
1505  // objects, then we need to map all spill slots to fixed positions, so that
1506  // they can be accessed through FP. Otherwise they would have to be accessed
1507  // via AP, which may not be available at the particular place in the program.
1508  MachineFrameInfo &MFI = MF.getFrameInfo();
1509  bool HasAlloca = MFI.hasVarSizedObjects();
1510  bool NeedsAlign = (MFI.getMaxAlign() > getStackAlign());
1511 
1512  if (!HasAlloca || !NeedsAlign)
1513  return;
1514 
1515  SmallSet<int, 4> DealignSlots;
1516  unsigned LFS = MFI.getLocalFrameSize();
1517  for (int i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
1518  if (!MFI.isSpillSlotObjectIndex(i) || MFI.isDeadObjectIndex(i))
1519  continue;
1520  unsigned S = MFI.getObjectSize(i);
1521  // Reduce the alignment to at most 8. This will require unaligned vector
1522  // stores if they happen here.
1523  Align A = std::max(MFI.getObjectAlign(i), Align(8));
1524  MFI.setObjectAlignment(i, Align(8));
1525  LFS = alignTo(LFS+S, A);
1526  MFI.mapLocalFrameObject(i, -static_cast<int64_t>(LFS));
1527  DealignSlots.insert(i);
1528  }
1529 
1530  MFI.setLocalFrameSize(LFS);
1531  Align A = MFI.getLocalFrameMaxAlign();
1532  assert(A <= 8 && "Unexpected local frame alignment");
1533  if (A == 1)
1534  MFI.setLocalFrameMaxAlign(Align(8));
1536 
1537  // Go over all MachineMemOperands in the code, and change the ones that
1538  // refer to the dealigned stack slots to reflect the new alignment.
1539  if (!DealignSlots.empty()) {
1540  for (MachineBasicBlock &BB : MF) {
1541  for (MachineInstr &MI : BB) {
1542  bool KeepOld = true;
1543  ArrayRef<MachineMemOperand*> memops = MI.memoperands();
1545  for (MachineMemOperand *MMO : memops) {
1546  auto *PV = MMO->getPseudoValue();
1547  if (auto *FS = dyn_cast_or_null<FixedStackPseudoSourceValue>(PV)) {
1548  int FI = FS->getFrameIndex();
1549  if (DealignSlots.count(FI)) {
1550  auto *NewMMO = MF.getMachineMemOperand(
1551  MMO->getPointerInfo(), MMO->getFlags(), MMO->getSize(),
1552  MFI.getObjectAlign(FI), MMO->getAAInfo(), MMO->getRanges(),
1553  MMO->getSyncScopeID(), MMO->getSuccessOrdering(),
1554  MMO->getFailureOrdering());
1555  new_memops.push_back(NewMMO);
1556  KeepOld = false;
1557  continue;
1558  }
1559  }
1560  new_memops.push_back(MMO);
1561  }
1562  if (!KeepOld)
1563  MI.setMemRefs(MF, new_memops);
1564  }
1565  }
1566  }
1567 
1568  // Set the physical aligned-stack base address register.
1569  unsigned AP = 0;
1570  if (const MachineInstr *AI = getAlignaInstr(MF))
1571  AP = AI->getOperand(0).getReg();
1572  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1573  HMFI.setStackAlignBasePhysReg(AP);
1574 }
1575 
1576 /// Returns true if there are no caller-saved registers available in class RC.
1578  const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
1580 
1581  auto IsUsed = [&HRI,&MRI] (unsigned Reg) -> bool {
1582  for (MCRegAliasIterator AI(Reg, &HRI, true); AI.isValid(); ++AI)
1583  if (MRI.isPhysRegUsed(*AI))
1584  return true;
1585  return false;
1586  };
1587 
1588  // Check for an unused caller-saved register. Callee-saved registers
1589  // have become pristine by now.
1590  for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)
1591  if (!IsUsed(*P))
1592  return false;
1593 
1594  // All caller-saved registers are used.
1595  return true;
1596 }
1597 
1598 #ifndef NDEBUG
1599 static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
1600  dbgs() << '{';
1601  for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
1602  unsigned R = x;
1603  dbgs() << ' ' << printReg(R, &TRI);
1604  }
1605  dbgs() << " }";
1606 }
1607 #endif
1608 
1610  const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
1611  LLVM_DEBUG(dbgs() << __func__ << " on " << MF.getName() << '\n');
1612  MachineFrameInfo &MFI = MF.getFrameInfo();
1613  BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1614 
1615  // Generate a set of unique, callee-saved registers (SRegs), where each
1616  // register in the set is maximal in terms of sub-/super-register relation,
1617  // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
1618 
1619  // (1) For each callee-saved register, add that register and all of its
1620  // sub-registers to SRegs.
1621  LLVM_DEBUG(dbgs() << "Initial CS registers: {");
1622  for (const CalleeSavedInfo &I : CSI) {
1623  unsigned R = I.getReg();
1624  LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));
1625  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1626  SRegs[*SR] = true;
1627  }
1628  LLVM_DEBUG(dbgs() << " }\n");
1629  LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI);
1630  dbgs() << "\n");
1631 
1632  // (2) For each reserved register, remove that register and all of its
1633  // sub- and super-registers from SRegs.
1634  BitVector Reserved = TRI->getReservedRegs(MF);
1635  for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
1636  unsigned R = x;
1637  for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1638  SRegs[*SR] = false;
1639  }
1640  LLVM_DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI);
1641  dbgs() << "\n");
1642  LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI);
1643  dbgs() << "\n");
1644 
1645  // (3) Collect all registers that have at least one sub-register in SRegs,
1646  // and also have no sub-registers that are reserved. These will be the can-
1647  // didates for saving as a whole instead of their individual sub-registers.
1648  // (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)
1649  BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
1650  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1651  unsigned R = x;
1652  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
1653  TmpSup[*SR] = true;
1654  }
1655  for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
1656  unsigned R = x;
1657  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) {
1658  if (!Reserved[*SR])
1659  continue;
1660  TmpSup[R] = false;
1661  break;
1662  }
1663  }
1664  LLVM_DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI);
1665  dbgs() << "\n");
1666 
1667  // (4) Include all super-registers found in (3) into SRegs.
1668  SRegs |= TmpSup;
1669  LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI);
1670  dbgs() << "\n");
1671 
1672  // (5) For each register R in SRegs, if any super-register of R is in SRegs,
1673  // remove R from SRegs.
1674  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1675  unsigned R = x;
1676  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {
1677  if (!SRegs[*SR])
1678  continue;
1679  SRegs[R] = false;
1680  break;
1681  }
1682  }
1683  LLVM_DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI);
1684  dbgs() << "\n");
1685 
1686  // Now, for each register that has a fixed stack slot, create the stack
1687  // object for it.
1688  CSI.clear();
1689 
1691 
1692  unsigned NumFixed;
1693  int MinOffset = 0; // CS offsets are negative.
1694  const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
1695  for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
1696  if (!SRegs[S->Reg])
1697  continue;
1698  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1699  int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset);
1700  MinOffset = std::min(MinOffset, S->Offset);
1701  CSI.push_back(CalleeSavedInfo(S->Reg, FI));
1702  SRegs[S->Reg] = false;
1703  }
1704 
1705  // There can be some registers that don't have fixed slots. For example,
1706  // we need to store R0-R3 in functions with exception handling. For each
1707  // such register, create a non-fixed stack object.
1708  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1709  unsigned R = x;
1711  unsigned Size = TRI->getSpillSize(*RC);
1712  int Off = MinOffset - Size;
1713  Align Alignment = std::min(TRI->getSpillAlign(*RC), getStackAlign());
1714  Off &= -Alignment.value();
1715  int FI = MFI.CreateFixedSpillStackObject(Size, Off);
1716  MinOffset = std::min(MinOffset, Off);
1717  CSI.push_back(CalleeSavedInfo(R, FI));
1718  SRegs[R] = false;
1719  }
1720 
1721  LLVM_DEBUG({
1722  dbgs() << "CS information: {";
1723  for (const CalleeSavedInfo &I : CSI) {
1724  int FI = I.getFrameIdx();
1725  int Off = MFI.getObjectOffset(FI);
1726  dbgs() << ' ' << printReg(I.getReg(), TRI) << ":fi#" << FI << ":sp";
1727  if (Off >= 0)
1728  dbgs() << '+';
1729  dbgs() << Off;
1730  }
1731  dbgs() << " }\n";
1732  });
1733 
1734 #ifndef NDEBUG
1735  // Verify that all registers were handled.
1736  bool MissedReg = false;
1737  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1738  unsigned R = x;
1739  dbgs() << printReg(R, TRI) << ' ';
1740  MissedReg = true;
1741  }
1742  if (MissedReg)
1743  llvm_unreachable("...there are unhandled callee-saved registers!");
1744 #endif
1745 
1746  return true;
1747 }
1748 
1749 bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B,
1751  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1752  MachineInstr *MI = &*It;
1753  DebugLoc DL = MI->getDebugLoc();
1754  Register DstR = MI->getOperand(0).getReg();
1755  Register SrcR = MI->getOperand(1).getReg();
1756  if (!Hexagon::ModRegsRegClass.contains(DstR) ||
1757  !Hexagon::ModRegsRegClass.contains(SrcR))
1758  return false;
1759 
1760  Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1761  BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));
1762  BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR)
1763  .addReg(TmpR, RegState::Kill);
1764 
1765  NewRegs.push_back(TmpR);
1766  B.erase(It);
1767  return true;
1768 }
1769 
1770 bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B,
1772  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1773  MachineInstr *MI = &*It;
1774  if (!MI->getOperand(0).isFI())
1775  return false;
1776 
1777  DebugLoc DL = MI->getDebugLoc();
1778  unsigned Opc = MI->getOpcode();
1779  Register SrcR = MI->getOperand(2).getReg();
1780  bool IsKill = MI->getOperand(2).isKill();
1781  int FI = MI->getOperand(0).getIndex();
1782 
1783  // TmpR = C2_tfrpr SrcR if SrcR is a predicate register
1784  // TmpR = A2_tfrcrr SrcR if SrcR is a modifier register
1785  Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1786  unsigned TfrOpc = (Opc == Hexagon::STriw_pred) ? Hexagon::C2_tfrpr
1787  : Hexagon::A2_tfrcrr;
1788  BuildMI(B, It, DL, HII.get(TfrOpc), TmpR)
1789  .addReg(SrcR, getKillRegState(IsKill));
1790 
1791  // S2_storeri_io FI, 0, TmpR
1792  BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io))
1793  .addFrameIndex(FI)
1794  .addImm(0)
1795  .addReg(TmpR, RegState::Kill)
1796  .cloneMemRefs(*MI);
1797 
1798  NewRegs.push_back(TmpR);
1799  B.erase(It);
1800  return true;
1801 }
1802 
1803 bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B,
1805  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1806  MachineInstr *MI = &*It;
1807  if (!MI->getOperand(1).isFI())
1808  return false;
1809 
1810  DebugLoc DL = MI->getDebugLoc();
1811  unsigned Opc = MI->getOpcode();
1812  Register DstR = MI->getOperand(0).getReg();
1813  int FI = MI->getOperand(1).getIndex();
1814 
1815  // TmpR = L2_loadri_io FI, 0
1816  Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1817  BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)
1818  .addFrameIndex(FI)
1819  .addImm(0)
1820  .cloneMemRefs(*MI);
1821 
1822  // DstR = C2_tfrrp TmpR if DstR is a predicate register
1823  // DstR = A2_tfrrcr TmpR if DstR is a modifier register
1824  unsigned TfrOpc = (Opc == Hexagon::LDriw_pred) ? Hexagon::C2_tfrrp
1825  : Hexagon::A2_tfrrcr;
1826  BuildMI(B, It, DL, HII.get(TfrOpc), DstR)
1827  .addReg(TmpR, RegState::Kill);
1828 
1829  NewRegs.push_back(TmpR);
1830  B.erase(It);
1831  return true;
1832 }
1833 
1834 bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
1836  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1837  MachineInstr *MI = &*It;
1838  if (!MI->getOperand(0).isFI())
1839  return false;
1840 
1841  DebugLoc DL = MI->getDebugLoc();
1842  Register SrcR = MI->getOperand(2).getReg();
1843  bool IsKill = MI->getOperand(2).isKill();
1844  int FI = MI->getOperand(0).getIndex();
1845  auto *RC = &Hexagon::HvxVRRegClass;
1846 
1847  // Insert transfer to general vector register.
1848  // TmpR0 = A2_tfrsi 0x01010101
1849  // TmpR1 = V6_vandqrt Qx, TmpR0
1850  // store FI, 0, TmpR1
1851  Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1852  Register TmpR1 = MRI.createVirtualRegister(RC);
1853 
1854  BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1855  .addImm(0x01010101);
1856 
1857  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1)
1858  .addReg(SrcR, getKillRegState(IsKill))
1859  .addReg(TmpR0, RegState::Kill);
1860 
1861  auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo();
1862  HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI);
1863  expandStoreVec(B, std::prev(It), MRI, HII, NewRegs);
1864 
1865  NewRegs.push_back(TmpR0);
1866  NewRegs.push_back(TmpR1);
1867  B.erase(It);
1868  return true;
1869 }
1870 
1871 bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
1873  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1874  MachineInstr *MI = &*It;
1875  if (!MI->getOperand(1).isFI())
1876  return false;
1877 
1878  DebugLoc DL = MI->getDebugLoc();
1879  Register DstR = MI->getOperand(0).getReg();
1880  int FI = MI->getOperand(1).getIndex();
1881  auto *RC = &Hexagon::HvxVRRegClass;
1882 
1883  // TmpR0 = A2_tfrsi 0x01010101
1884  // TmpR1 = load FI, 0
1885  // DstR = V6_vandvrt TmpR1, TmpR0
1886  Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1887  Register TmpR1 = MRI.createVirtualRegister(RC);
1888 
1889  BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1890  .addImm(0x01010101);
1891  MachineFunction &MF = *B.getParent();
1892  auto *HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1893  HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI);
1894  expandLoadVec(B, std::prev(It), MRI, HII, NewRegs);
1895 
1896  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)
1897  .addReg(TmpR1, RegState::Kill)
1898  .addReg(TmpR0, RegState::Kill);
1899 
1900  NewRegs.push_back(TmpR0);
1901  NewRegs.push_back(TmpR1);
1902  B.erase(It);
1903  return true;
1904 }
1905 
1906 bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
1908  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1909  MachineFunction &MF = *B.getParent();
1910  auto &MFI = MF.getFrameInfo();
1911  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1912  MachineInstr *MI = &*It;
1913  if (!MI->getOperand(0).isFI())
1914  return false;
1915 
1916  // It is possible that the double vector being stored is only partially
1917  // defined. From the point of view of the liveness tracking, it is ok to
1918  // store it as a whole, but if we break it up we may end up storing a
1919  // register that is entirely undefined.
1920  LivePhysRegs LPR(HRI);
1921  LPR.addLiveIns(B);
1923  for (auto R = B.begin(); R != It; ++R) {
1924  Clobbers.clear();
1925  LPR.stepForward(*R, Clobbers);
1926  }
1927 
1928  DebugLoc DL = MI->getDebugLoc();
1929  Register SrcR = MI->getOperand(2).getReg();
1930  Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);
1931  Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
1932  bool IsKill = MI->getOperand(2).isKill();
1933  int FI = MI->getOperand(0).getIndex();
1934  bool NeedsAligna = needsAligna(MF);
1935 
1936  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1937  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1938  Align HasAlign = MFI.getObjectAlign(FI);
1939  unsigned StoreOpc;
1940 
1941  auto UseAligned = [&](Align NeedAlign, Align HasAlign) {
1942  return !NeedsAligna && (NeedAlign <= HasAlign);
1943  };
1944 
1945  // Store low part.
1946  if (LPR.contains(SrcLo)) {
1947  StoreOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vS32b_ai
1948  : Hexagon::V6_vS32Ub_ai;
1949  BuildMI(B, It, DL, HII.get(StoreOpc))
1950  .addFrameIndex(FI)
1951  .addImm(0)
1952  .addReg(SrcLo, getKillRegState(IsKill))
1953  .cloneMemRefs(*MI);
1954  }
1955 
1956  // Store high part.
1957  if (LPR.contains(SrcHi)) {
1958  StoreOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vS32b_ai
1959  : Hexagon::V6_vS32Ub_ai;
1960  BuildMI(B, It, DL, HII.get(StoreOpc))
1961  .addFrameIndex(FI)
1962  .addImm(Size)
1963  .addReg(SrcHi, getKillRegState(IsKill))
1964  .cloneMemRefs(*MI);
1965  }
1966 
1967  B.erase(It);
1968  return true;
1969 }
1970 
1971 bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,
1973  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1974  MachineFunction &MF = *B.getParent();
1975  auto &MFI = MF.getFrameInfo();
1976  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1977  MachineInstr *MI = &*It;
1978  if (!MI->getOperand(1).isFI())
1979  return false;
1980 
1981  DebugLoc DL = MI->getDebugLoc();
1982  Register DstR = MI->getOperand(0).getReg();
1983  Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
1984  Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
1985  int FI = MI->getOperand(1).getIndex();
1986  bool NeedsAligna = needsAligna(MF);
1987 
1988  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1989  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1990  Align HasAlign = MFI.getObjectAlign(FI);
1991  unsigned LoadOpc;
1992 
1993  auto UseAligned = [&](Align NeedAlign, Align HasAlign) {
1994  return !NeedsAligna && (NeedAlign <= HasAlign);
1995  };
1996 
1997  // Load low part.
1998  LoadOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vL32b_ai
1999  : Hexagon::V6_vL32Ub_ai;
2000  BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)
2001  .addFrameIndex(FI)
2002  .addImm(0)
2003  .cloneMemRefs(*MI);
2004 
2005  // Load high part.
2006  LoadOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vL32b_ai
2007  : Hexagon::V6_vL32Ub_ai;
2008  BuildMI(B, It, DL, HII.get(LoadOpc), DstHi)
2009  .addFrameIndex(FI)
2010  .addImm(Size)
2011  .cloneMemRefs(*MI);
2012 
2013  B.erase(It);
2014  return true;
2015 }
2016 
2017 bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B,
2019  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
2020  MachineFunction &MF = *B.getParent();
2021  auto &MFI = MF.getFrameInfo();
2022  MachineInstr *MI = &*It;
2023  if (!MI->getOperand(0).isFI())
2024  return false;
2025 
2026  bool NeedsAligna = needsAligna(MF);
2027  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2028  DebugLoc DL = MI->getDebugLoc();
2029  Register SrcR = MI->getOperand(2).getReg();
2030  bool IsKill = MI->getOperand(2).isKill();
2031  int FI = MI->getOperand(0).getIndex();
2032 
2033  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
2034  Align HasAlign = MFI.getObjectAlign(FI);
2035  bool UseAligned = !NeedsAligna && (NeedAlign <= HasAlign);
2036  unsigned StoreOpc = UseAligned ? Hexagon::V6_vS32b_ai
2037  : Hexagon::V6_vS32Ub_ai;
2038  BuildMI(B, It, DL, HII.get(StoreOpc))
2039  .addFrameIndex(FI)
2040  .addImm(0)
2041  .addReg(SrcR, getKillRegState(IsKill))
2042  .cloneMemRefs(*MI);
2043 
2044  B.erase(It);
2045  return true;
2046 }
2047 
2048 bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,
2050  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
2051  MachineFunction &MF = *B.getParent();
2052  auto &MFI = MF.getFrameInfo();
2053  MachineInstr *MI = &*It;
2054  if (!MI->getOperand(1).isFI())
2055  return false;
2056 
2057  bool NeedsAligna = needsAligna(MF);
2058  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2059  DebugLoc DL = MI->getDebugLoc();
2060  Register DstR = MI->getOperand(0).getReg();
2061  int FI = MI->getOperand(1).getIndex();
2062 
2063  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
2064  Align HasAlign = MFI.getObjectAlign(FI);
2065  bool UseAligned = !NeedsAligna && (NeedAlign <= HasAlign);
2066  unsigned LoadOpc = UseAligned ? Hexagon::V6_vL32b_ai
2067  : Hexagon::V6_vL32Ub_ai;
2068  BuildMI(B, It, DL, HII.get(LoadOpc), DstR)
2069  .addFrameIndex(FI)
2070  .addImm(0)
2071  .cloneMemRefs(*MI);
2072 
2073  B.erase(It);
2074  return true;
2075 }
2076 
2077 bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
2078  SmallVectorImpl<unsigned> &NewRegs) const {
2079  auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
2081  bool Changed = false;
2082 
2083  for (auto &B : MF) {
2084  // Traverse the basic block.
2086  for (auto I = B.begin(), E = B.end(); I != E; I = NextI) {
2087  MachineInstr *MI = &*I;
2088  NextI = std::next(I);
2089  unsigned Opc = MI->getOpcode();
2090 
2091  switch (Opc) {
2092  case TargetOpcode::COPY:
2093  Changed |= expandCopy(B, I, MRI, HII, NewRegs);
2094  break;
2095  case Hexagon::STriw_pred:
2096  case Hexagon::STriw_ctr:
2097  Changed |= expandStoreInt(B, I, MRI, HII, NewRegs);
2098  break;
2099  case Hexagon::LDriw_pred:
2100  case Hexagon::LDriw_ctr:
2101  Changed |= expandLoadInt(B, I, MRI, HII, NewRegs);
2102  break;
2103  case Hexagon::PS_vstorerq_ai:
2104  Changed |= expandStoreVecPred(B, I, MRI, HII, NewRegs);
2105  break;
2106  case Hexagon::PS_vloadrq_ai:
2107  Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs);
2108  break;
2109  case Hexagon::PS_vloadrw_ai:
2110  Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs);
2111  break;
2112  case Hexagon::PS_vstorerw_ai:
2113  Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs);
2114  break;
2115  }
2116  }
2117  }
2118 
2119  return Changed;
2120 }
2121 
2123  BitVector &SavedRegs,
2124  RegScavenger *RS) const {
2125  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2126 
2127  SavedRegs.resize(HRI.getNumRegs());
2128 
2129  // If we have a function containing __builtin_eh_return we want to spill and
2130  // restore all callee saved registers. Pretend that they are used.
2132  for (const MCPhysReg *R = HRI.getCalleeSavedRegs(&MF); *R; ++R)
2133  SavedRegs.set(*R);
2134 
2135  // Replace predicate register pseudo spill code.
2136  SmallVector<unsigned,8> NewRegs;
2137  expandSpillMacros(MF, NewRegs);
2138  if (OptimizeSpillSlots && !isOptNone(MF))
2139  optimizeSpillSlots(MF, NewRegs);
2140 
2141  // We need to reserve a spill slot if scavenging could potentially require
2142  // spilling a scavenged register.
2143  if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {
2144  MachineFrameInfo &MFI = MF.getFrameInfo();
2147  // Reserve an int register in any case, because it could be used to hold
2148  // the stack offset in case it does not fit into a spill instruction.
2149  SpillRCs.insert(&Hexagon::IntRegsRegClass);
2150 
2151  for (unsigned VR : NewRegs)
2152  SpillRCs.insert(MRI.getRegClass(VR));
2153 
2154  for (auto *RC : SpillRCs) {
2155  if (!needToReserveScavengingSpillSlots(MF, HRI, RC))
2156  continue;
2157  unsigned Num = 1;
2158  switch (RC->getID()) {
2159  case Hexagon::IntRegsRegClassID:
2160  Num = NumberScavengerSlots;
2161  break;
2162  case Hexagon::HvxQRRegClassID:
2163  Num = 2; // Vector predicate spills also need a vector register.
2164  break;
2165  }
2166  unsigned S = HRI.getSpillSize(*RC);
2167  Align A = HRI.getSpillAlign(*RC);
2168  for (unsigned i = 0; i < Num; i++) {
2169  int NewFI = MFI.CreateSpillStackObject(S, A);
2170  RS->addScavengingFrameIndex(NewFI);
2171  }
2172  }
2173  }
2174 
2175  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2176 }
2177 
2178 unsigned HexagonFrameLowering::findPhysReg(MachineFunction &MF,
2182  const TargetRegisterClass *RC) const {
2183  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2184  auto &MRI = MF.getRegInfo();
2185 
2186  auto isDead = [&FIR,&DeadMap] (unsigned Reg) -> bool {
2187  auto F = DeadMap.find({Reg,0});
2188  if (F == DeadMap.end())
2189  return false;
2190  for (auto &DR : F->second)
2191  if (DR.contains(FIR))
2192  return true;
2193  return false;
2194  };
2195 
2196  for (unsigned Reg : RC->getRawAllocationOrder(MF)) {
2197  bool Dead = true;
2198  for (auto R : HexagonBlockRanges::expandToSubRegs({Reg,0}, MRI, HRI)) {
2199  if (isDead(R.Reg))
2200  continue;
2201  Dead = false;
2202  break;
2203  }
2204  if (Dead)
2205  return Reg;
2206  }
2207  return 0;
2208 }
2209 
2210 void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
2211  SmallVectorImpl<unsigned> &VRegs) const {
2212  auto &HST = MF.getSubtarget<HexagonSubtarget>();
2213  auto &HII = *HST.getInstrInfo();
2214  auto &HRI = *HST.getRegisterInfo();
2215  auto &MRI = MF.getRegInfo();
2216  HexagonBlockRanges HBR(MF);
2217 
2218  using BlockIndexMap =
2219  std::map<MachineBasicBlock *, HexagonBlockRanges::InstrIndexMap>;
2220  using BlockRangeMap =
2221  std::map<MachineBasicBlock *, HexagonBlockRanges::RangeList>;
2222  using IndexType = HexagonBlockRanges::IndexType;
2223 
2224  struct SlotInfo {
2225  BlockRangeMap Map;
2226  unsigned Size = 0;
2227  const TargetRegisterClass *RC = nullptr;
2228 
2229  SlotInfo() = default;
2230  };
2231 
2232  BlockIndexMap BlockIndexes;
2233  SmallSet<int,4> BadFIs;
2234  std::map<int,SlotInfo> FIRangeMap;
2235 
2236  // Accumulate register classes: get a common class for a pre-existing
2237  // class HaveRC and a new class NewRC. Return nullptr if a common class
2238  // cannot be found, otherwise return the resulting class. If HaveRC is
2239  // nullptr, assume that it is still unset.
2240  auto getCommonRC =
2241  [](const TargetRegisterClass *HaveRC,
2242  const TargetRegisterClass *NewRC) -> const TargetRegisterClass * {
2243  if (HaveRC == nullptr || HaveRC == NewRC)
2244  return NewRC;
2245  // Different classes, both non-null. Pick the more general one.
2246  if (HaveRC->hasSubClassEq(NewRC))
2247  return HaveRC;
2248  if (NewRC->hasSubClassEq(HaveRC))
2249  return NewRC;
2250  return nullptr;
2251  };
2252 
2253  // Scan all blocks in the function. Check all occurrences of frame indexes,
2254  // and collect relevant information.
2255  for (auto &B : MF) {
2256  std::map<int,IndexType> LastStore, LastLoad;
2257  // Emplace appears not to be supported in gcc 4.7.2-4.
2258  //auto P = BlockIndexes.emplace(&B, HexagonBlockRanges::InstrIndexMap(B));
2259  auto P = BlockIndexes.insert(
2260  std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B)));
2261  auto &IndexMap = P.first->second;
2262  LLVM_DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n"
2263  << IndexMap << '\n');
2264 
2265  for (auto &In : B) {
2266  int LFI, SFI;
2267  bool Load = HII.isLoadFromStackSlot(In, LFI) && !HII.isPredicated(In);
2268  bool Store = HII.isStoreToStackSlot(In, SFI) && !HII.isPredicated(In);
2269  if (Load && Store) {
2270  // If it's both a load and a store, then we won't handle it.
2271  BadFIs.insert(LFI);
2272  BadFIs.insert(SFI);
2273  continue;
2274  }
2275  // Check for register classes of the register used as the source for
2276  // the store, and the register used as the destination for the load.
2277  // Also, only accept base+imm_offset addressing modes. Other addressing
2278  // modes can have side-effects (post-increments, etc.). For stack
2279  // slots they are very unlikely, so there is not much loss due to
2280  // this restriction.
2281  if (Load || Store) {
2282  int TFI = Load ? LFI : SFI;
2283  unsigned AM = HII.getAddrMode(In);
2284  SlotInfo &SI = FIRangeMap[TFI];
2285  bool Bad = (AM != HexagonII::BaseImmOffset);
2286  if (!Bad) {
2287  // If the addressing mode is ok, check the register class.
2288  unsigned OpNum = Load ? 0 : 2;
2289  auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF);
2290  RC = getCommonRC(SI.RC, RC);
2291  if (RC == nullptr)
2292  Bad = true;
2293  else
2294  SI.RC = RC;
2295  }
2296  if (!Bad) {
2297  // Check sizes.
2298  unsigned S = HII.getMemAccessSize(In);
2299  if (SI.Size != 0 && SI.Size != S)
2300  Bad = true;
2301  else
2302  SI.Size = S;
2303  }
2304  if (!Bad) {
2305  for (auto *Mo : In.memoperands()) {
2306  if (!Mo->isVolatile() && !Mo->isAtomic())
2307  continue;
2308  Bad = true;
2309  break;
2310  }
2311  }
2312  if (Bad)
2313  BadFIs.insert(TFI);
2314  }
2315 
2316  // Locate uses of frame indices.
2317  for (unsigned i = 0, n = In.getNumOperands(); i < n; ++i) {
2318  const MachineOperand &Op = In.getOperand(i);
2319  if (!Op.isFI())
2320  continue;
2321  int FI = Op.getIndex();
2322  // Make sure that the following operand is an immediate and that
2323  // it is 0. This is the offset in the stack object.
2324  if (i+1 >= n || !In.getOperand(i+1).isImm() ||
2325  In.getOperand(i+1).getImm() != 0)
2326  BadFIs.insert(FI);
2327  if (BadFIs.count(FI))
2328  continue;
2329 
2330  IndexType Index = IndexMap.getIndex(&In);
2331  if (Load) {
2332  if (LastStore[FI] == IndexType::None)
2333  LastStore[FI] = IndexType::Entry;
2334  LastLoad[FI] = Index;
2335  } else if (Store) {
2336  HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2337  if (LastStore[FI] != IndexType::None)
2338  RL.add(LastStore[FI], LastLoad[FI], false, false);
2339  else if (LastLoad[FI] != IndexType::None)
2340  RL.add(IndexType::Entry, LastLoad[FI], false, false);
2341  LastLoad[FI] = IndexType::None;
2342  LastStore[FI] = Index;
2343  } else {
2344  BadFIs.insert(FI);
2345  }
2346  }
2347  }
2348 
2349  for (auto &I : LastLoad) {
2350  IndexType LL = I.second;
2351  if (LL == IndexType::None)
2352  continue;
2353  auto &RL = FIRangeMap[I.first].Map[&B];
2354  IndexType &LS = LastStore[I.first];
2355  if (LS != IndexType::None)
2356  RL.add(LS, LL, false, false);
2357  else
2358  RL.add(IndexType::Entry, LL, false, false);
2359  LS = IndexType::None;
2360  }
2361  for (auto &I : LastStore) {
2362  IndexType LS = I.second;
2363  if (LS == IndexType::None)
2364  continue;
2365  auto &RL = FIRangeMap[I.first].Map[&B];
2366  RL.add(LS, IndexType::None, false, false);
2367  }
2368  }
2369 
2370  LLVM_DEBUG({
2371  for (auto &P : FIRangeMap) {
2372  dbgs() << "fi#" << P.first;
2373  if (BadFIs.count(P.first))
2374  dbgs() << " (bad)";
2375  dbgs() << " RC: ";
2376  if (P.second.RC != nullptr)
2377  dbgs() << HRI.getRegClassName(P.second.RC) << '\n';
2378  else
2379  dbgs() << "<null>\n";
2380  for (auto &R : P.second.Map)
2381  dbgs() << " " << printMBBReference(*R.first) << " { " << R.second
2382  << "}\n";
2383  }
2384  });
2385 
2386  // When a slot is loaded from in a block without being stored to in the
2387  // same block, it is live-on-entry to this block. To avoid CFG analysis,
2388  // consider this slot to be live-on-exit from all blocks.
2389  SmallSet<int,4> LoxFIs;
2390 
2391  std::map<MachineBasicBlock*,std::vector<int>> BlockFIMap;
2392 
2393  for (auto &P : FIRangeMap) {
2394  // P = pair(FI, map: BB->RangeList)
2395  if (BadFIs.count(P.first))
2396  continue;
2397  for (auto &B : MF) {
2398  auto F = P.second.Map.find(&B);
2399  // F = pair(BB, RangeList)
2400  if (F == P.second.Map.end() || F->second.empty())
2401  continue;
2402  HexagonBlockRanges::IndexRange &IR = F->second.front();
2403  if (IR.start() == IndexType::Entry)
2404  LoxFIs.insert(P.first);
2405  BlockFIMap[&B].push_back(P.first);
2406  }
2407  }
2408 
2409  LLVM_DEBUG({
2410  dbgs() << "Block-to-FI map (* -- live-on-exit):\n";
2411  for (auto &P : BlockFIMap) {
2412  auto &FIs = P.second;
2413  if (FIs.empty())
2414  continue;
2415  dbgs() << " " << printMBBReference(*P.first) << ": {";
2416  for (auto I : FIs) {
2417  dbgs() << " fi#" << I;
2418  if (LoxFIs.count(I))
2419  dbgs() << '*';
2420  }
2421  dbgs() << " }\n";
2422  }
2423  });
2424 
2425 #ifndef NDEBUG
2426  bool HasOptLimit = SpillOptMax.getPosition();
2427 #endif
2428 
2429  // eliminate loads, when all loads eliminated, eliminate all stores.
2430  for (auto &B : MF) {
2431  auto F = BlockIndexes.find(&B);
2432  assert(F != BlockIndexes.end());
2433  HexagonBlockRanges::InstrIndexMap &IM = F->second;
2434  HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM);
2435  HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM);
2436  LLVM_DEBUG(dbgs() << printMBBReference(B) << " dead map\n"
2438 
2439  for (auto FI : BlockFIMap[&B]) {
2440  if (BadFIs.count(FI))
2441  continue;
2442  LLVM_DEBUG(dbgs() << "Working on fi#" << FI << '\n');
2443  HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2444  for (auto &Range : RL) {
2445  LLVM_DEBUG(dbgs() << "--Examining range:" << RL << '\n');
2446  if (!IndexType::isInstr(Range.start()) ||
2447  !IndexType::isInstr(Range.end()))
2448  continue;
2449  MachineInstr &SI = *IM.getInstr(Range.start());
2450  MachineInstr &EI = *IM.getInstr(Range.end());
2451  assert(SI.mayStore() && "Unexpected start instruction");
2452  assert(EI.mayLoad() && "Unexpected end instruction");
2453  MachineOperand &SrcOp = SI.getOperand(2);
2454 
2456  SrcOp.getSubReg() };
2457  auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
2458  // The this-> is needed to unconfuse MSVC.
2459  unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
2460  LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI)
2461  << '\n');
2462  if (FoundR == 0)
2463  continue;
2464 #ifndef NDEBUG
2465  if (HasOptLimit) {
2466  if (SpillOptCount >= SpillOptMax)
2467  return;
2468  SpillOptCount++;
2469  }
2470 #endif
2471 
2472  // Generate the copy-in: "FoundR = COPY SrcR" at the store location.
2473  MachineBasicBlock::iterator StartIt = SI.getIterator(), NextIt;
2474  MachineInstr *CopyIn = nullptr;
2475  if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) {
2476  const DebugLoc &DL = SI.getDebugLoc();
2477  CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)
2478  .add(SrcOp);
2479  }
2480 
2481  ++StartIt;
2482  // Check if this is a last store and the FI is live-on-exit.
2483  if (LoxFIs.count(FI) && (&Range == &RL.back())) {
2484  // Update store's source register.
2485  if (unsigned SR = SrcOp.getSubReg())
2486  SrcOp.setReg(HRI.getSubReg(FoundR, SR));
2487  else
2488  SrcOp.setReg(FoundR);
2489  SrcOp.setSubReg(0);
2490  // We are keeping this register live.
2491  SrcOp.setIsKill(false);
2492  } else {
2493  B.erase(&SI);
2494  IM.replaceInstr(&SI, CopyIn);
2495  }
2496 
2497  auto EndIt = std::next(EI.getIterator());
2498  for (auto It = StartIt; It != EndIt; It = NextIt) {
2499  MachineInstr &MI = *It;
2500  NextIt = std::next(It);
2501  int TFI;
2502  if (!HII.isLoadFromStackSlot(MI, TFI) || TFI != FI)
2503  continue;
2504  Register DstR = MI.getOperand(0).getReg();
2505  assert(MI.getOperand(0).getSubReg() == 0);
2506  MachineInstr *CopyOut = nullptr;
2507  if (DstR != FoundR) {
2508  DebugLoc DL = MI.getDebugLoc();
2509  unsigned MemSize = HII.getMemAccessSize(MI);
2510  assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
2511  unsigned CopyOpc = TargetOpcode::COPY;
2512  if (HII.isSignExtendingLoad(MI))
2513  CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;
2514  else if (HII.isZeroExtendingLoad(MI))
2515  CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;
2516  CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)
2517  .addReg(FoundR, getKillRegState(&MI == &EI));
2518  }
2519  IM.replaceInstr(&MI, CopyOut);
2520  B.erase(It);
2521  }
2522 
2523  // Update the dead map.
2524  HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 };
2525  for (auto RR : HexagonBlockRanges::expandToSubRegs(FoundRR, MRI, HRI))
2526  DM[RR].subtract(Range);
2527  } // for Range in range list
2528  }
2529  }
2530 }
2531 
2532 void HexagonFrameLowering::expandAlloca(MachineInstr *AI,
2533  const HexagonInstrInfo &HII, unsigned SP, unsigned CF) const {
2534  MachineBasicBlock &MB = *AI->getParent();
2535  DebugLoc DL = AI->getDebugLoc();
2536  unsigned A = AI->getOperand(2).getImm();
2537 
2538  // Have
2539  // Rd = alloca Rs, #A
2540  //
2541  // If Rs and Rd are different registers, use this sequence:
2542  // Rd = sub(r29, Rs)
2543  // r29 = sub(r29, Rs)
2544  // Rd = and(Rd, #-A) ; if necessary
2545  // r29 = and(r29, #-A) ; if necessary
2546  // Rd = add(Rd, #CF) ; CF size aligned to at most A
2547  // otherwise, do
2548  // Rd = sub(r29, Rs)
2549  // Rd = and(Rd, #-A) ; if necessary
2550  // r29 = Rd
2551  // Rd = add(Rd, #CF) ; CF size aligned to at most A
2552 
2553  MachineOperand &RdOp = AI->getOperand(0);
2554  MachineOperand &RsOp = AI->getOperand(1);
2555  unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg();
2556 
2557  // Rd = sub(r29, Rs)
2558  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
2559  .addReg(SP)
2560  .addReg(Rs);
2561  if (Rs != Rd) {
2562  // r29 = sub(r29, Rs)
2563  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)
2564  .addReg(SP)
2565  .addReg(Rs);
2566  }
2567  if (A > 8) {
2568  // Rd = and(Rd, #-A)
2569  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
2570  .addReg(Rd)
2571  .addImm(-int64_t(A));
2572  if (Rs != Rd)
2573  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)
2574  .addReg(SP)
2575  .addImm(-int64_t(A));
2576  }
2577  if (Rs == Rd) {
2578  // r29 = Rd
2579  BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)
2580  .addReg(Rd);
2581  }
2582  if (CF > 0) {
2583  // Rd = add(Rd, #CF)
2584  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
2585  .addReg(Rd)
2586  .addImm(CF);
2587  }
2588 }
2589 
2591  const MachineFrameInfo &MFI = MF.getFrameInfo();
2592  if (!MFI.hasVarSizedObjects())
2593  return false;
2594  // Do not check for max stack object alignment here, because the stack
2595  // may not be complete yet. Assume that we will need PS_aligna if there
2596  // are variable-sized objects.
2597  return true;
2598 }
2599 
2601  const MachineFunction &MF) const {
2602  for (auto &B : MF)
2603  for (auto &I : B)
2604  if (I.getOpcode() == Hexagon::PS_aligna)
2605  return &I;
2606  return nullptr;
2607 }
2608 
2609 /// Adds all callee-saved registers as implicit uses or defs to the
2610 /// instruction.
2611 void HexagonFrameLowering::addCalleeSaveRegistersAsImpOperand(MachineInstr *MI,
2612  const CSIVect &CSI, bool IsDef, bool IsKill) const {
2613  // Add the callee-saved registers as implicit uses.
2614  for (auto &R : CSI)
2615  MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
2616 }
2617 
2618 /// Determine whether the callee-saved register saves and restores should
2619 /// be generated via inline code. If this function returns "true", inline
2620 /// code will be generated. If this function returns "false", additional
2621 /// checks are performed, which may still lead to the inline code.
2622 bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF,
2623  const CSIVect &CSI) const {
2625  return true;
2627  return true;
2628  if (!hasFP(MF))
2629  return true;
2630  if (!isOptSize(MF) && !isMinSize(MF))
2632  return true;
2633 
2634  // Check if CSI only has double registers, and if the registers form
2635  // a contiguous block starting from D8.
2636  BitVector Regs(Hexagon::NUM_TARGET_REGS);
2637  for (const CalleeSavedInfo &I : CSI) {
2638  unsigned R = I.getReg();
2639  if (!Hexagon::DoubleRegsRegClass.contains(R))
2640  return true;
2641  Regs[R] = true;
2642  }
2643  int F = Regs.find_first();
2644  if (F != Hexagon::D8)
2645  return true;
2646  while (F >= 0) {
2647  int N = Regs.find_next(F);
2648  if (N >= 0 && N != F+1)
2649  return true;
2650  F = N;
2651  }
2652 
2653  return false;
2654 }
2655 
2656 bool HexagonFrameLowering::useSpillFunction(const MachineFunction &MF,
2657  const CSIVect &CSI) const {
2658  if (shouldInlineCSR(MF, CSI))
2659  return false;
2660  unsigned NumCSI = CSI.size();
2661  if (NumCSI <= 1)
2662  return false;
2663 
2664  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs
2666  return Threshold < NumCSI;
2667 }
2668 
2669 bool HexagonFrameLowering::useRestoreFunction(const MachineFunction &MF,
2670  const CSIVect &CSI) const {
2671  if (shouldInlineCSR(MF, CSI))
2672  return false;
2673  // The restore functions do a bit more than just restoring registers.
2674  // The non-returning versions will go back directly to the caller's
2675  // caller, others will clean up the stack frame in preparation for
2676  // a tail call. Using them can still save code size even if only one
2677  // register is getting restores. Make the decision based on -Oz:
2678  // using -Os will use inline restore for a single register.
2679  if (isMinSize(MF))
2680  return true;
2681  unsigned NumCSI = CSI.size();
2682  if (NumCSI <= 1)
2683  return false;
2684 
2685  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs-1
2687  return Threshold < NumCSI;
2688 }
2689 
2690 bool HexagonFrameLowering::mayOverflowFrameOffset(MachineFunction &MF) const {
2691  unsigned StackSize = MF.getFrameInfo().estimateStackSize(MF);
2692  auto &HST = MF.getSubtarget<HexagonSubtarget>();
2693  // A fairly simplistic guess as to whether a potential load/store to a
2694  // stack location could require an extra register.
2695  if (HST.useHVXOps() && StackSize > 256)
2696  return true;
2697 
2698  // Check if the function has store-immediate instructions that access
2699  // the stack. Since the offset field is not extendable, if the stack
2700  // size exceeds the offset limit (6 bits, shifted), the stores will
2701  // require a new base register.
2702  bool HasImmStack = false;
2703  unsigned MinLS = ~0u; // Log_2 of the memory access size.
2704 
2705  for (const MachineBasicBlock &B : MF) {
2706  for (const MachineInstr &MI : B) {
2707  unsigned LS = 0;
2708  switch (MI.getOpcode()) {
2709  case Hexagon::S4_storeirit_io:
2710  case Hexagon::S4_storeirif_io:
2711  case Hexagon::S4_storeiri_io:
2712  ++LS;
2714  case Hexagon::S4_storeirht_io:
2715  case Hexagon::S4_storeirhf_io:
2716  case Hexagon::S4_storeirh_io:
2717  ++LS;
2719  case Hexagon::S4_storeirbt_io:
2720  case Hexagon::S4_storeirbf_io:
2721  case Hexagon::S4_storeirb_io:
2722  if (MI.getOperand(0).isFI())
2723  HasImmStack = true;
2724  MinLS = std::min(MinLS, LS);
2725  break;
2726  }
2727  }
2728  }
2729 
2730  if (HasImmStack)
2731  return !isUInt<6>(StackSize >> MinLS);
2732 
2733  return false;
2734 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MachineDominatorTree::findNearestCommonDominator
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B.
Definition: MachineDominators.h:155
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:188
CmpMode::FP
@ FP
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:353
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:71
llvm::MachineFrameInfo::estimateStackSize
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
Definition: MachineFrameInfo.cpp:137
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1563
llvm::MachineRegisterInfo::isPhysRegUsed
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:583
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::HexagonRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: HexagonRegisterInfo.cpp:119
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:579
Optional.h
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
llvm::createHexagonCallFrameInformation
FunctionPass * createHexagonCallFrameInformation()
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
SpillFuncThreshold
static cl::opt< int > SpillFuncThreshold("spill-func-threshold", cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"), cl::init(6), cl::ZeroOrMore)
llvm::MachineModuleInfo::getContext
const MCContext & getContext() const
Definition: MachineModuleInfo.h:166
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
llvm::Function::hasOptNone
bool hasOptNone() const
Do not optimize this function (-O0).
Definition: Function.h:655
SpillFuncThresholdOs
static cl::opt< int > SpillFuncThresholdOs("spill-func-threshold-Os", cl::Hidden, cl::desc("Specify Os spill func threshold"), cl::init(1), cl::ZeroOrMore)
getMaxCalleeSavedReg
static unsigned getMaxCalleeSavedReg(ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo &TRI)
Returns the callee saved register with the largest id in the vector.
Definition: HexagonFrameLowering.cpp:264
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
T
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:62
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
Pass.h
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
DM
static RegisterPass< DebugifyModulePass > DM("debugify", "Attach debug info to everything")
llvm::SetVector::size
size_type size() const
Determine the number of elements in the SetVector.
Definition: SetVector.h:77
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1005
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:435
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:119
llvm::HexagonFrameLowering::getFrameIndexReference
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: HexagonFrameLowering.cpp:1259
HexagonSubtarget.h
llvm::HexagonTargetMachine
Definition: HexagonTargetMachine.h:25
findCFILocation
static Optional< MachineBasicBlock::iterator > findCFILocation(MachineBasicBlock &B)
Definition: HexagonFrameLowering.cpp:988
ErrorHandling.h
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::HexagonBlockRanges::IndexRange
Definition: HexagonBlockRanges.h:81
RPO
rpo function Deduce function attributes in RPO
Definition: FunctionAttrs.cpp:1953
dump_registers
static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI)
Definition: HexagonFrameLowering.cpp:1599
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
MachineBasicBlock.h
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MachineFunction::getNumBlockIDs
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
Definition: MachineFunction.h:768
llvm::MachineBasicBlock::findDebugLoc
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
Definition: MachineBasicBlock.cpp:1372
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::HexagonMachineFunctionInfo::setStackAlignBasePhysReg
void setStackAlignBasePhysReg(unsigned R)
Definition: HexagonMachineFunctionInfo.h:84
llvm::HexagonRegisterInfo::isEHReturnCalleeSaveReg
bool isEHReturnCalleeSaveReg(unsigned Reg) const
Definition: HexagonRegisterInfo.cpp:61
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
DenseMap.h
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:333
llvm::MachineFrameInfo::setStackSize
void setStackSize(uint64_t Size)
Set the size of the stack.
Definition: MachineFrameInfo.h:556
llvm::MachineFrameInfo::isObjectPreAllocated
bool isObjectPreAllocated(int ObjectIdx) const
Return true if the object was pre-allocated into the local block.
Definition: MachineFrameInfo.h:446
llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
Definition: HexagonFrameLowering.cpp:1609
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
getSpillFunctionFor
static const char * getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType, bool Stkchk=false)
Definition: HexagonFrameLowering.cpp:1187
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
llvm::Optional
Definition: APInt.h:33
llvm::MachineFrameInfo::setMaxCallFrameSize
void setMaxCallFrameSize(unsigned S)
Definition: MachineFrameInfo.h:632
HexagonFrameLowering.h
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
SpillOptMax
static cl::opt< unsigned > SpillOptMax("spill-opt-max", cl::Hidden, cl::init(std::numeric_limits< unsigned >::max()))
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::MachineDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachineDominators.h:109
llvm::MachineBasicBlock::back
MachineInstr & back()
Definition: MachineBasicBlock.h:252
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:393
llvm::MachineBasicBlock::terminators
iterator_range< iterator > terminators()
Definition: MachineBasicBlock.h:292
HexagonTargetMachine.h
isMinSize
static bool isMinSize(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:385
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1564
llvm::MachineDominatorTree::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: MachineDominators.cpp:52
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:622
llvm::MachineFrameInfo::setObjectAlignment
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
Definition: MachineFrameInfo.h:474
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
HexagonBaseInfo.h
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:207
llvm::HexagonRegisterInfo::getCallerSavedRegs
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
Definition: HexagonRegisterInfo.cpp:67
MachineRegisterInfo.h
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1298
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
getMax32BitSubRegister
static unsigned getMax32BitSubRegister(unsigned Reg, const TargetRegisterInfo &TRI, bool hireg=true)
Map a register pair Reg to the subregister that has the greater "number", i.e.
Definition: HexagonFrameLowering.cpp:244
llvm::HexagonFrameLowering::insertCFIInstructions
void insertCFIInstructions(MachineFunction &MF) const
Definition: HexagonFrameLowering.cpp:1018
llvm::HexagonSubtarget::isEnvironmentMusl
bool isEnvironmentMusl() const
Definition: HexagonSubtarget.h:115
CommandLine.h
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
SK_ToMem
@ SK_ToMem
Definition: HexagonFrameLowering.cpp:1182
R2
#define R2(n)
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:835
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
SpillOptCount
static unsigned SpillOptCount
Definition: HexagonFrameLowering.cpp:192
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::HexagonBlockRanges::RegisterRef::Reg
llvm::Register Reg
Definition: HexagonBlockRanges.h:36
llvm::msgpack::Type::Map
@ Map
llvm::HexagonMachineFunctionInfo
Hexagon target-specific information for each MachineFunction.
Definition: HexagonMachineFunctionInfo.h:25
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1471
isOptSize
static bool isOptSize(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:380
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:739
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::ARM_PROC::A
@ A
Definition: ARMBaseInfo.h:34
llvm::MachineFrameInfo::setLocalFrameMaxAlign
void setLocalFrameMaxAlign(Align Alignment)
Required alignment of the local object blob, which is the strictest alignment of any object in it.
Definition: MachineFrameInfo.h:425
hasTailCall
static bool hasTailCall(const MachineBasicBlock &MBB)
Returns true if MBB has a machine instructions that indicates a tail call in the block.
Definition: HexagonFrameLowering.cpp:335
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:199
llvm::HexagonFrameLowering::enableCalleeSaveSkip
bool enableCalleeSaveSkip(const MachineFunction &MF) const override
Returns true if the target can safely skip saving callee-saved registers for noreturn nounwind functi...
Definition: HexagonFrameLowering.cpp:555
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::HexagonFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: HexagonFrameLowering.cpp:1140
llvm::HexagonBlockRanges::RegisterRef
Definition: HexagonBlockRanges.h:35
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
PseudoSourceValue.h
llvm::HexagonBlockRanges::PrintRangeMap
Definition: HexagonBlockRanges.h:152
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:180
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:82
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:77
llvm::HexagonFrameLowering::needsAligna
bool needsAligna(const MachineFunction &MF) const
Definition: HexagonFrameLowering.cpp:2590
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
EnableStackOVFSanitizer
static cl::opt< bool > EnableStackOVFSanitizer("enable-stackovf-sanitizer", cl::Hidden, cl::desc("Enable runtime checks for stack overflow."), cl::init(false), cl::ZeroOrMore)
EnableShrinkWrapping
static cl::opt< bool > EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable stack frame shrink wrapping"))
BitVector.h
llvm::MachineFrameInfo::getLocalFrameMaxAlign
Align getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
Definition: MachineFrameInfo.h:430
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:553
needsStackFrame
static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR, const HexagonRegisterInfo &HRI)
Checks if the basic block contains any instruction that needs a stack frame to be already in place.
Definition: HexagonFrameLowering.cpp:282
DebugLoc.h
IR
Statically lint checks LLVM IR
Definition: Lint.cpp:746
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:494
llvm::BitVector
Definition: BitVector.h:74
HexagonInstrInfo.h
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
NumberScavengerSlots
static cl::opt< unsigned > NumberScavengerSlots("number-scavenger-slots", cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2), cl::ZeroOrMore)
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:656
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::HexagonBlockRanges::RegisterRef::Sub
unsigned Sub
Definition: HexagonBlockRanges.h:37
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::None
const NoneType None
Definition: None.h:23
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFrameInfo::isDeadObjectIndex
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
Definition: MachineFrameInfo.h:713
llvm::HexagonMachineFunctionInfo::hasEHReturn
bool hasEHReturn() const
Definition: HexagonMachineFunctionInfo.h:78
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:44
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::MachineFrameInfo::CreateSpillStackObject
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
Definition: MachineFrameInfo.cpp:66
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::HexagonBlockRanges::RangeList
Definition: HexagonBlockRanges.h:108
needToReserveScavengingSpillSlots
static bool needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC)
Returns true if there are no caller-saved registers available in class RC.
Definition: HexagonFrameLowering.cpp:1577
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:120
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:124
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:592
llvm::MachineInstrBundleIterator::getInstrIterator
instr_iterator getInstrIterator() const
Definition: MachineInstrBundleIterator.h:274
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:288
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
DisableDeallocRet
static cl::opt< bool > DisableDeallocRet("disable-hexagon-dealloc-ret", cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"))
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:626
llvm::cl::opt< bool >
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:282
llvm::MachineFrameInfo::CreateFixedSpillStackObject
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:102
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
llvm::CodeGenOpt::Default
@ Default
Definition: CodeGen.h:55
llvm::initializeHexagonCallFrameInformationPass
void initializeHexagonCallFrameInformationPass(PassRegistry &)
llvm::MachineFrameInfo::getLocalFrameSize
int64_t getLocalFrameSize() const
Get the size of the local object blob.
Definition: MachineFrameInfo.h:421
llvm::HexagonBlockRanges::InstrIndexMap::replaceInstr
void replaceInstr(MachineInstr *OldMI, MachineInstr *NewMI)
Definition: HexagonBlockRanges.cpp:206
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
EliminateFramePointer
static cl::opt< bool > EliminateFramePointer("hexagon-fp-elim", cl::init(true), cl::Hidden, cl::desc("Refrain from using FP whenever possible"))
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:954
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::HexagonBlockRanges::RangeList::add
void add(IndexType Start, IndexType End, bool Fixed, bool TiedEnd)
Definition: HexagonBlockRanges.h:110
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:467
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
MCRegisterInfo.h
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:266
MachineFunctionPass.h
llvm::MachineFrameInfo::mapLocalFrameObject
void mapLocalFrameObject(int ObjectIndex, int64_t Offset)
Map a frame index into the local object block.
Definition: MachineFrameInfo.h:402
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:546
HexagonRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:657
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:229
llvm::RegScavenger::addScavengingFrameIndex
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Definition: RegisterScavenging.h:123
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:524
MachineModuleInfo.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
MachinePostDominators.h
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
HexagonBlockRanges.h
R6
#define R6(n)
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:813
llvm::HexagonII::BaseImmOffset
@ BaseImmOffset
Definition: HexagonBaseInfo.h:34
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::SetVector::insert
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:755
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:241
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
None.h
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:1073
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:171
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:359
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:999
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::HexagonBlockRanges::expandToSubRegs
static RegisterSet expandToSubRegs(RegisterRef R, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
Definition: HexagonBlockRanges.cpp:261
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
enableAllocFrameElim
static bool enableAllocFrameElim(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:572
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
Compiler.h
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
OptimizeSpillSlots
static cl::opt< bool > OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden, cl::init(true), cl::desc("Optimize spill slots"))
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:290
llvm::MCContext::createTempSymbol
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:303
SK_FromMemTailcall
@ SK_FromMemTailcall
Definition: HexagonFrameLowering.cpp:1184
llvm::StackOffset::getFixed
static StackOffset getFixed(ScalarTy Fixed)
Definition: TypeSize.h:143
llvm::MachinePostDominatorTree
MachinePostDominatorTree - an analysis pass wrapper for DominatorTree used to compute the post-domina...
Definition: MachinePostDominators.h:27
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:569
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
getReturn
static MachineInstr * getReturn(MachineBasicBlock &MBB)
Returns the "return" instruction from this block, or nullptr if there isn't any.
Definition: HexagonFrameLowering.cpp:353
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:371
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1676
hasReturn
static bool hasReturn(const MachineBasicBlock &MBB)
Returns true if MBB contains an instruction that returns.
Definition: HexagonFrameLowering.cpp:344
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:581
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::MachinePostDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachinePostDominators.h:54
EnableSaveRestoreLong
static cl::opt< bool > EnableSaveRestoreLong("enable-save-restore-long", cl::Hidden, cl::desc("Enable long calls for save-restore stubs."), cl::init(false), cl::ZeroOrMore)
j
return j(j<< 16)
llvm::MachineFunction::getBlockNumbered
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
Definition: MachineFunction.h:758
llvm::HexagonFrameLowering::getCalleeSavedSpillSlots
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
Definition: HexagonFrameLowering.h:90
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::HexagonBlockRanges::RegToRangeMap
std::map< RegisterRef, RangeList > RegToRangeMap
Definition: HexagonBlockRanges.h:145
llvm::MachineFunction::needsFrameMoves
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
Definition: MachineFunction.cpp:592
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
ShrinkLimit
static cl::opt< unsigned > ShrinkLimit("shrink-frame-limit", cl::init(std::numeric_limits< unsigned >::max()), cl::Hidden, cl::ZeroOrMore, cl::desc("Max count of stack frame shrink-wraps"))
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:637
llvm::HexagonFrameLowering::getAlignaInstr
const MachineInstr * getAlignaInstr(const MachineFunction &MF) const
Definition: HexagonFrameLowering.cpp:2600
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::AArch64CC::LS
@ LS
Definition: AArch64BaseInfo.h:264
Function.h
llvm::HexagonBlockRanges::InstrIndexMap
Definition: HexagonBlockRanges.h:125
llvm::HexagonFrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: HexagonFrameLowering.cpp:1491
x
TODO unsigned x
Definition: README.txt:10
llvm::HexagonBlockRanges::InstrIndexMap::getIndex
IndexType getIndex(MachineInstr *MI) const
Definition: HexagonBlockRanges.cpp:176
llvm::HexagonBlockRanges::IndexType
Definition: HexagonBlockRanges.h:47
isRestoreCall
static bool isRestoreCall(unsigned Opc)
Definition: HexagonFrameLowering.cpp:360
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:581
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:686
llvm::BitVector::find_next
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:300
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
llvm::ReversePostOrderTraversal
Definition: PostOrderIterator.h:290
llvm::MachinePostDominatorTree::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: MachinePostDominators.cpp:40
CodeGen.h
llvm::MCSubRegIterator
MCSubRegIterator enumerates all sub-registers of Reg.
Definition: MCRegisterInfo.h:594
llvm::Function::isVarArg
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:190
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
llvm::MachineFunction::addFrameInst
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:291
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
PostOrderIterator.h
llvm::HexagonFrameLowering::determineCalleeSaves
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: HexagonFrameLowering.cpp:2122
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:272
MachineInstrBuilder.h
llvm::HexagonFrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Perform most of the PEI work here:
Definition: HexagonFrameLowering.cpp:504
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::BitVector::find_first
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:292
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:207
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
SpillKind
SpillKind
Definition: HexagonFrameLowering.cpp:1181
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:244
llvm::HexagonBlockRanges
Definition: HexagonBlockRanges.h:31
llvm::HexagonBlockRanges::InstrIndexMap::getInstr
MachineInstr * getInstr(IndexType Idx) const
Definition: HexagonBlockRanges.cpp:171
Threshold
static cl::opt< unsigned > Threshold("loop-unswitch-threshold", cl::desc("Max loop size to unswitch"), cl::init(100), cl::Hidden)
llvm::SmallSet::empty
LLVM_NODISCARD bool empty() const
Definition: SmallSet.h:155
MachineMemOperand.h
llvm::SmallVectorImpl< unsigned >
isOptNone
static bool isOptNone(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:375
HexagonMachineFunctionInfo.h
MachineOperand.h
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:658
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:562
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:126
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::TargetFrameLowering::determineCalleeSaves
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: TargetFrameLoweringImpl.cpp:78
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachinePostDominatorTree::findNearestCommonDominator
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B) const
Definition: MachinePostDominators.h:77
llvm::cl::desc
Definition: CommandLine.h:412
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
RegisterScavenging.h
raw_ostream.h
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:46
n
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Definition: README.txt:685
llvm::SetVector
A vector that has set insertion semantics.
Definition: SetVector.h:40
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstrBundleIterator< const MachineInstr >
llvm::TargetFrameLowering::SpillSlot
Definition: TargetFrameLowering.h:51
llvm::M68kBeads::Term
@ Term
Definition: M68kBaseInfo.h:71
SK_FromMem
@ SK_FromMem
Definition: HexagonFrameLowering.cpp:1183
llvm::MachineFrameInfo::setLocalFrameSize
void setLocalFrameSize(int64_t sz)
Set the size of the local object blob.
Definition: MachineFrameInfo.h:418
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1021
TargetRegisterInfo.h
INITIALIZE_PASS
INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi", "Hexagon call frame information", false, false) FunctionPass *llvm
Definition: HexagonFrameLowering.cpp:235
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:274
llvm::MachineFrameInfo::setUseLocalStackAllocationBlock
void setUseLocalStackAllocationBlock(bool v)
setUseLocalStackAllocationBlock - Set whether the local allocation blob should be allocated together ...
Definition: MachineFrameInfo.h:441
llvm::SrcOp
Definition: MachineIRBuilder.h:119
SetVector.h
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:572
MachineDominators.h
llvm::HexagonFrameLowering::FirstVarArgSavedReg
int FirstVarArgSavedReg
Definition: HexagonFrameLowering.h:34
SmallSet.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
LivePhysRegs.h
llvm::HexagonFrameLowering::processFunctionBeforeFrameFinalized
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: HexagonFrameLowering.cpp:1502