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HexagonFrameLowering.cpp
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1 //===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "HexagonFrameLowering.h"
11 #include "HexagonBlockRanges.h"
12 #include "HexagonInstrInfo.h"
14 #include "HexagonRegisterInfo.h"
15 #include "HexagonSubtarget.h"
16 #include "HexagonTargetMachine.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/None.h"
21 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/SetVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/SmallVector.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/MC/MCDwarf.h"
46 #include "llvm/MC/MCRegisterInfo.h"
47 #include "llvm/Pass.h"
48 #include "llvm/Support/CodeGen.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/Debug.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <cstdint>
60 #include <iterator>
61 #include <limits>
62 #include <map>
63 #include <optional>
64 #include <utility>
65 #include <vector>
66 
67 #define DEBUG_TYPE "hexagon-pei"
68 
69 // Hexagon stack frame layout as defined by the ABI:
70 //
71 // Incoming arguments
72 // passed via stack
73 // |
74 // |
75 // SP during function's FP during function's |
76 // +-- runtime (top of stack) runtime (bottom) --+ |
77 // | | |
78 // --++---------------------+------------------+-----------------++-+-------
79 // | parameter area for | variable-size | fixed-size |LR| arg
80 // | called functions | local objects | local objects |FP|
81 // --+----------------------+------------------+-----------------+--+-------
82 // <- size known -> <- size unknown -> <- size known ->
83 //
84 // Low address High address
85 //
86 // <--- stack growth
87 //
88 //
89 // - In any circumstances, the outgoing function arguments are always accessi-
90 // ble using the SP, and the incoming arguments are accessible using the FP.
91 // - If the local objects are not aligned, they can always be accessed using
92 // the FP.
93 // - If there are no variable-sized objects, the local objects can always be
94 // accessed using the SP, regardless whether they are aligned or not. (The
95 // alignment padding will be at the bottom of the stack (highest address),
96 // and so the offset with respect to the SP will be known at the compile-
97 // -time.)
98 //
99 // The only complication occurs if there are both, local aligned objects, and
100 // dynamically allocated (variable-sized) objects. The alignment pad will be
101 // placed between the FP and the local objects, thus preventing the use of the
102 // FP to access the local objects. At the same time, the variable-sized objects
103 // will be between the SP and the local objects, thus introducing an unknown
104 // distance from the SP to the locals.
105 //
106 // To avoid this problem, a new register is created that holds the aligned
107 // address of the bottom of the stack, referred in the sources as AP (aligned
108 // pointer). The AP will be equal to "FP-p", where "p" is the smallest pad
109 // that aligns AP to the required boundary (a maximum of the alignments of
110 // all stack objects, fixed- and variable-sized). All local objects[1] will
111 // then use AP as the base pointer.
112 // [1] The exception is with "fixed" stack objects. "Fixed" stack objects get
113 // their name from being allocated at fixed locations on the stack, relative
114 // to the FP. In the presence of dynamic allocation and local alignment, such
115 // objects can only be accessed through the FP.
116 //
117 // Illustration of the AP:
118 // FP --+
119 // |
120 // ---------------+---------------------+-----+-----------------------++-+--
121 // Rest of the | Local stack objects | Pad | Fixed stack objects |LR|
122 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
123 // ---------------+---------------------+-----+-----------------+-----+--+--
124 // |<-- Multiple of the -->|
125 // stack alignment +-- AP
126 //
127 // The AP is set up at the beginning of the function. Since it is not a dedi-
128 // cated (reserved) register, it needs to be kept live throughout the function
129 // to be available as the base register for local object accesses.
130 // Normally, an address of a stack objects is obtained by a pseudo-instruction
131 // PS_fi. To access local objects with the AP register present, a different
132 // pseudo-instruction needs to be used: PS_fia. The PS_fia takes one extra
133 // argument compared to PS_fi: the first input register is the AP register.
134 // This keeps the register live between its definition and its uses.
135 
136 // The AP register is originally set up using pseudo-instruction PS_aligna:
137 // AP = PS_aligna A
138 // where
139 // A - required stack alignment
140 // The alignment value must be the maximum of all alignments required by
141 // any stack object.
142 
143 // The dynamic allocation uses a pseudo-instruction PS_alloca:
144 // Rd = PS_alloca Rs, A
145 // where
146 // Rd - address of the allocated space
147 // Rs - minimum size (the actual allocated can be larger to accommodate
148 // alignment)
149 // A - required alignment
150 
151 using namespace llvm;
152 
153 static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
154  cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
155 
156 static cl::opt<unsigned>
157  NumberScavengerSlots("number-scavenger-slots", cl::Hidden,
158  cl::desc("Set the number of scavenger slots"),
159  cl::init(2));
160 
161 static cl::opt<int>
162  SpillFuncThreshold("spill-func-threshold", cl::Hidden,
163  cl::desc("Specify O2(not Os) spill func threshold"),
164  cl::init(6));
165 
166 static cl::opt<int>
167  SpillFuncThresholdOs("spill-func-threshold-Os", cl::Hidden,
168  cl::desc("Specify Os spill func threshold"),
169  cl::init(1));
170 
172  "enable-stackovf-sanitizer", cl::Hidden,
173  cl::desc("Enable runtime checks for stack overflow."), cl::init(false));
174 
175 static cl::opt<bool>
176  EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden,
177  cl::desc("Enable stack frame shrink wrapping"));
178 
179 static cl::opt<unsigned>
180  ShrinkLimit("shrink-frame-limit",
182  cl::desc("Max count of stack frame shrink-wraps"));
183 
184 static cl::opt<bool>
185  EnableSaveRestoreLong("enable-save-restore-long", cl::Hidden,
186  cl::desc("Enable long calls for save-restore stubs."),
187  cl::init(false));
188 
189 static cl::opt<bool> EliminateFramePointer("hexagon-fp-elim", cl::init(true),
190  cl::Hidden, cl::desc("Refrain from using FP whenever possible"));
191 
192 static cl::opt<bool> OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden,
193  cl::init(true), cl::desc("Optimize spill slots"));
194 
195 #ifndef NDEBUG
196 static cl::opt<unsigned> SpillOptMax("spill-opt-max", cl::Hidden,
198 static unsigned SpillOptCount = 0;
199 #endif
200 
201 namespace llvm {
202 
205 
206 } // end namespace llvm
207 
208 namespace {
209 
210  class HexagonCallFrameInformation : public MachineFunctionPass {
211  public:
212  static char ID;
213 
214  HexagonCallFrameInformation() : MachineFunctionPass(ID) {
217  }
218 
219  bool runOnMachineFunction(MachineFunction &MF) override;
220 
221  MachineFunctionProperties getRequiredProperties() const override {
224  }
225  };
226 
228 
229 } // end anonymous namespace
230 
231 bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
232  auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
233  bool NeedCFI = MF.needsFrameMoves();
234 
235  if (!NeedCFI)
236  return false;
237  HFI.insertCFIInstructions(MF);
238  return true;
239 }
240 
241 INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi",
242  "Hexagon call frame information", false, false)
243 
245  return new HexagonCallFrameInformation();
246 }
247 
248 /// Map a register pair Reg to the subregister that has the greater "number",
249 /// i.e. D3 (aka R7:6) will be mapped to R7, etc.
251  const TargetRegisterInfo &TRI,
252  bool hireg = true) {
253  if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
254  return Reg;
255 
256  Register RegNo = 0;
257  for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
258  if (hireg) {
259  if (*SubRegs > RegNo)
260  RegNo = *SubRegs;
261  } else {
262  if (!RegNo || *SubRegs < RegNo)
263  RegNo = *SubRegs;
264  }
265  }
266  return RegNo;
267 }
268 
269 /// Returns the callee saved register with the largest id in the vector.
271  const TargetRegisterInfo &TRI) {
272  static_assert(Hexagon::R1 > 0,
273  "Assume physical registers are encoded as positive integers");
274  if (CSI.empty())
275  return 0;
276 
277  Register Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
278  for (unsigned I = 1, E = CSI.size(); I < E; ++I) {
280  if (Reg > Max)
281  Max = Reg;
282  }
283  return Max;
284 }
285 
286 /// Checks if the basic block contains any instruction that needs a stack
287 /// frame to be already in place.
288 static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
289  const HexagonRegisterInfo &HRI) {
290  for (const MachineInstr &MI : MBB) {
291  if (MI.isCall())
292  return true;
293  unsigned Opc = MI.getOpcode();
294  switch (Opc) {
295  case Hexagon::PS_alloca:
296  case Hexagon::PS_aligna:
297  return true;
298  default:
299  break;
300  }
301  // Check individual operands.
302  for (const MachineOperand &MO : MI.operands()) {
303  // While the presence of a frame index does not prove that a stack
304  // frame will be required, all frame indexes should be within alloc-
305  // frame/deallocframe. Otherwise, the code that translates a frame
306  // index into an offset would have to be aware of the placement of
307  // the frame creation/destruction instructions.
308  if (MO.isFI())
309  return true;
310  if (MO.isReg()) {
311  Register R = MO.getReg();
312  // Virtual registers will need scavenging, which then may require
313  // a stack slot.
314  if (R.isVirtual())
315  return true;
316  for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
317  if (CSR[*S])
318  return true;
319  continue;
320  }
321  if (MO.isRegMask()) {
322  // A regmask would normally have all callee-saved registers marked
323  // as preserved, so this check would not be needed, but in case of
324  // ever having other regmasks (for other calling conventions),
325  // make sure they would be processed correctly.
326  const uint32_t *BM = MO.getRegMask();
327  for (int x = CSR.find_first(); x >= 0; x = CSR.find_next(x)) {
328  unsigned R = x;
329  // If this regmask does not preserve a CSR, a frame will be needed.
330  if (!(BM[R/32] & (1u << (R%32))))
331  return true;
332  }
333  }
334  }
335  }
336  return false;
337 }
338 
339  /// Returns true if MBB has a machine instructions that indicates a tail call
340  /// in the block.
341 static bool hasTailCall(const MachineBasicBlock &MBB) {
343  if (I == MBB.end())
344  return false;
345  unsigned RetOpc = I->getOpcode();
346  return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;
347 }
348 
349 /// Returns true if MBB contains an instruction that returns.
350 static bool hasReturn(const MachineBasicBlock &MBB) {
351  for (const MachineInstr &MI : MBB.terminators())
352  if (MI.isReturn())
353  return true;
354  return false;
355 }
356 
357 /// Returns the "return" instruction from this block, or nullptr if there
358 /// isn't any.
360  for (auto &I : MBB)
361  if (I.isReturn())
362  return &I;
363  return nullptr;
364 }
365 
366 static bool isRestoreCall(unsigned Opc) {
367  switch (Opc) {
368  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
369  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
370  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
371  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
372  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
373  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
374  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
375  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
376  return true;
377  }
378  return false;
379 }
380 
381 static inline bool isOptNone(const MachineFunction &MF) {
382  return MF.getFunction().hasOptNone() ||
384 }
385 
386 static inline bool isOptSize(const MachineFunction &MF) {
387  const Function &F = MF.getFunction();
388  return F.hasOptSize() && !F.hasMinSize();
389 }
390 
391 static inline bool isMinSize(const MachineFunction &MF) {
392  return MF.getFunction().hasMinSize();
393 }
394 
395 /// Implements shrink-wrapping of the stack frame. By default, stack frame
396 /// is created in the function entry block, and is cleaned up in every block
397 /// that returns. This function finds alternate blocks: one for the frame
398 /// setup (prolog) and one for the cleanup (epilog).
399 void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
400  MachineBasicBlock *&PrologB, MachineBasicBlock *&EpilogB) const {
401  static unsigned ShrinkCounter = 0;
402 
404  MF.getFunction().isVarArg())
405  return;
406  if (ShrinkLimit.getPosition()) {
407  if (ShrinkCounter >= ShrinkLimit)
408  return;
409  ShrinkCounter++;
410  }
411 
412  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
413 
415  MDT.runOnMachineFunction(MF);
417  MPT.runOnMachineFunction(MF);
418 
419  using UnsignedMap = DenseMap<unsigned, unsigned>;
421 
422  UnsignedMap RPO;
423  RPOTType RPOT(&MF);
424  unsigned RPON = 0;
425  for (auto &I : RPOT)
426  RPO[I->getNumber()] = RPON++;
427 
428  // Don't process functions that have loops, at least for now. Placement
429  // of prolog and epilog must take loop structure into account. For simpli-
430  // city don't do it right now.
431  for (auto &I : MF) {
432  unsigned BN = RPO[I.getNumber()];
433  for (MachineBasicBlock *Succ : I.successors())
434  // If found a back-edge, return.
435  if (RPO[Succ->getNumber()] <= BN)
436  return;
437  }
438 
439  // Collect the set of blocks that need a stack frame to execute. Scan
440  // each block for uses/defs of callee-saved registers, calls, etc.
442  BitVector CSR(Hexagon::NUM_TARGET_REGS);
443  for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
444  for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S)
445  CSR[*S] = true;
446 
447  for (auto &I : MF)
448  if (needsStackFrame(I, CSR, HRI))
449  SFBlocks.push_back(&I);
450 
451  LLVM_DEBUG({
452  dbgs() << "Blocks needing SF: {";
453  for (auto &B : SFBlocks)
454  dbgs() << " " << printMBBReference(*B);
455  dbgs() << " }\n";
456  });
457  // No frame needed?
458  if (SFBlocks.empty())
459  return;
460 
461  // Pick a common dominator and a common post-dominator.
462  MachineBasicBlock *DomB = SFBlocks[0];
463  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
464  DomB = MDT.findNearestCommonDominator(DomB, SFBlocks[i]);
465  if (!DomB)
466  break;
467  }
468  MachineBasicBlock *PDomB = SFBlocks[0];
469  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
470  PDomB = MPT.findNearestCommonDominator(PDomB, SFBlocks[i]);
471  if (!PDomB)
472  break;
473  }
474  LLVM_DEBUG({
475  dbgs() << "Computed dom block: ";
476  if (DomB)
477  dbgs() << printMBBReference(*DomB);
478  else
479  dbgs() << "<null>";
480  dbgs() << ", computed pdom block: ";
481  if (PDomB)
482  dbgs() << printMBBReference(*PDomB);
483  else
484  dbgs() << "<null>";
485  dbgs() << "\n";
486  });
487  if (!DomB || !PDomB)
488  return;
489 
490  // Make sure that DomB dominates PDomB and PDomB post-dominates DomB.
491  if (!MDT.dominates(DomB, PDomB)) {
492  LLVM_DEBUG(dbgs() << "Dom block does not dominate pdom block\n");
493  return;
494  }
495  if (!MPT.dominates(PDomB, DomB)) {
496  LLVM_DEBUG(dbgs() << "PDom block does not post-dominate dom block\n");
497  return;
498  }
499 
500  // Finally, everything seems right.
501  PrologB = DomB;
502  EpilogB = PDomB;
503 }
504 
505 /// Perform most of the PEI work here:
506 /// - saving/restoring of the callee-saved registers,
507 /// - stack frame creation and destruction.
508 /// Normally, this work is distributed among various functions, but doing it
509 /// in one place allows shrink-wrapping of the stack frame.
511  MachineBasicBlock &MBB) const {
512  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
513 
514  MachineFrameInfo &MFI = MF.getFrameInfo();
515  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
516 
517  MachineBasicBlock *PrologB = &MF.front(), *EpilogB = nullptr;
519  findShrunkPrologEpilog(MF, PrologB, EpilogB);
520 
521  bool PrologueStubs = false;
522  insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs);
523  insertPrologueInBlock(*PrologB, PrologueStubs);
524  updateEntryPaths(MF, *PrologB);
525 
526  if (EpilogB) {
527  insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
528  insertEpilogueInBlock(*EpilogB);
529  } else {
530  for (auto &B : MF)
531  if (B.isReturnBlock())
532  insertCSRRestoresInBlock(B, CSI, HRI);
533 
534  for (auto &B : MF)
535  if (B.isReturnBlock())
536  insertEpilogueInBlock(B);
537 
538  for (auto &B : MF) {
539  if (B.empty())
540  continue;
541  MachineInstr *RetI = getReturn(B);
542  if (!RetI || isRestoreCall(RetI->getOpcode()))
543  continue;
544  for (auto &R : CSI)
545  RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
546  }
547  }
548 
549  if (EpilogB) {
550  // If there is an epilog block, it may not have a return instruction.
551  // In such case, we need to add the callee-saved registers as live-ins
552  // in all blocks on all paths from the epilog to any return block.
553  unsigned MaxBN = MF.getNumBlockIDs();
554  BitVector DoneT(MaxBN+1), DoneF(MaxBN+1), Path(MaxBN+1);
555  updateExitPaths(*EpilogB, *EpilogB, DoneT, DoneF, Path);
556  }
557 }
558 
559 /// Returns true if the target can safely skip saving callee-saved registers
560 /// for noreturn nounwind functions.
562  const MachineFunction &MF) const {
563  const auto &F = MF.getFunction();
564  assert(F.hasFnAttribute(Attribute::NoReturn) &&
565  F.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
566  !F.getFunction().hasFnAttribute(Attribute::UWTable));
567  (void)F;
568 
569  // No need to save callee saved registers if the function does not return.
570  return MF.getSubtarget<HexagonSubtarget>().noreturnStackElim();
571 }
572 
573 // Helper function used to determine when to eliminate the stack frame for
574 // functions marked as noreturn and when the noreturn-stack-elim options are
575 // specified. When both these conditions are true, then a FP may not be needed
576 // if the function makes a call. It is very similar to enableCalleeSaveSkip,
577 // but it used to check if the allocframe can be eliminated as well.
578 static bool enableAllocFrameElim(const MachineFunction &MF) {
579  const auto &F = MF.getFunction();
580  const auto &MFI = MF.getFrameInfo();
581  const auto &HST = MF.getSubtarget<HexagonSubtarget>();
582  assert(!MFI.hasVarSizedObjects() &&
583  !HST.getRegisterInfo()->hasStackRealignment(MF));
584  return F.hasFnAttribute(Attribute::NoReturn) &&
585  F.hasFnAttribute(Attribute::NoUnwind) &&
586  !F.hasFnAttribute(Attribute::UWTable) && HST.noreturnStackElim() &&
587  MFI.getStackSize() == 0;
588 }
589 
590 void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
591  bool PrologueStubs) const {
592  MachineFunction &MF = *MBB.getParent();
593  MachineFrameInfo &MFI = MF.getFrameInfo();
594  auto &HST = MF.getSubtarget<HexagonSubtarget>();
595  auto &HII = *HST.getInstrInfo();
596  auto &HRI = *HST.getRegisterInfo();
597 
598  Align MaxAlign = std::max(MFI.getMaxAlign(), getStackAlign());
599 
600  // Calculate the total stack frame size.
601  // Get the number of bytes to allocate from the FrameInfo.
602  unsigned FrameSize = MFI.getStackSize();
603  // Round up the max call frame size to the max alignment on the stack.
604  unsigned MaxCFA = alignTo(MFI.getMaxCallFrameSize(), MaxAlign);
605  MFI.setMaxCallFrameSize(MaxCFA);
606 
607  FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign);
608  MFI.setStackSize(FrameSize);
609 
610  bool AlignStack = (MaxAlign > getStackAlign());
611 
612  // Get the number of bytes to allocate from the FrameInfo.
613  unsigned NumBytes = MFI.getStackSize();
614  Register SP = HRI.getStackRegister();
615  unsigned MaxCF = MFI.getMaxCallFrameSize();
617 
619  for (auto &MBB : MF)
620  for (auto &MI : MBB)
621  if (MI.getOpcode() == Hexagon::PS_alloca)
622  AdjustRegs.push_back(&MI);
623 
624  for (auto *MI : AdjustRegs) {
625  assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");
626  expandAlloca(MI, HII, SP, MaxCF);
627  MI->eraseFromParent();
628  }
629 
630  DebugLoc dl = MBB.findDebugLoc(InsertPt);
631 
632  if (MF.getFunction().isVarArg() &&
633  MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) {
634  // Calculate the size of register saved area.
635  int NumVarArgRegs = 6 - FirstVarArgSavedReg;
636  int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0)
637  ? NumVarArgRegs * 4
638  : NumVarArgRegs * 4 + 4;
639  if (RegisterSavedAreaSizePlusPadding > 0) {
640  // Decrement the stack pointer by size of register saved area plus
641  // padding if any.
642  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
643  .addReg(SP)
644  .addImm(-RegisterSavedAreaSizePlusPadding)
646 
647  int NumBytes = 0;
648  // Copy all the named arguments below register saved area.
649  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
650  for (int i = HMFI.getFirstNamedArgFrameIndex(),
651  e = HMFI.getLastNamedArgFrameIndex(); i >= e; --i) {
652  uint64_t ObjSize = MFI.getObjectSize(i);
653  Align ObjAlign = MFI.getObjectAlign(i);
654 
655  // Determine the kind of load/store that should be used.
656  unsigned LDOpc, STOpc;
657  uint64_t OpcodeChecker = ObjAlign.value();
658 
659  // Handle cases where alignment of an object is > its size.
660  if (ObjAlign > ObjSize) {
661  if (ObjSize <= 1)
662  OpcodeChecker = 1;
663  else if (ObjSize <= 2)
664  OpcodeChecker = 2;
665  else if (ObjSize <= 4)
666  OpcodeChecker = 4;
667  else if (ObjSize > 4)
668  OpcodeChecker = 8;
669  }
670 
671  switch (OpcodeChecker) {
672  case 1:
673  LDOpc = Hexagon::L2_loadrb_io;
674  STOpc = Hexagon::S2_storerb_io;
675  break;
676  case 2:
677  LDOpc = Hexagon::L2_loadrh_io;
678  STOpc = Hexagon::S2_storerh_io;
679  break;
680  case 4:
681  LDOpc = Hexagon::L2_loadri_io;
682  STOpc = Hexagon::S2_storeri_io;
683  break;
684  case 8:
685  default:
686  LDOpc = Hexagon::L2_loadrd_io;
687  STOpc = Hexagon::S2_storerd_io;
688  break;
689  }
690 
691  Register RegUsed = LDOpc == Hexagon::L2_loadrd_io ? Hexagon::D3
692  : Hexagon::R6;
693  int LoadStoreCount = ObjSize / OpcodeChecker;
694 
695  if (ObjSize % OpcodeChecker)
696  ++LoadStoreCount;
697 
698  // Get the start location of the load. NumBytes is basically the
699  // offset from the stack pointer of previous function, which would be
700  // the caller in this case, as this function has variable argument
701  // list.
702  if (NumBytes != 0)
703  NumBytes = alignTo(NumBytes, ObjAlign);
704 
705  int Count = 0;
706  while (Count < LoadStoreCount) {
707  // Load the value of the named argument on stack.
708  BuildMI(MBB, InsertPt, dl, HII.get(LDOpc), RegUsed)
709  .addReg(SP)
710  .addImm(RegisterSavedAreaSizePlusPadding +
711  ObjAlign.value() * Count + NumBytes)
713 
714  // Store it below the register saved area plus padding.
715  BuildMI(MBB, InsertPt, dl, HII.get(STOpc))
716  .addReg(SP)
717  .addImm(ObjAlign.value() * Count + NumBytes)
718  .addReg(RegUsed)
720 
721  Count++;
722  }
723  NumBytes += MFI.getObjectSize(i);
724  }
725 
726  // Make NumBytes 8 byte aligned
727  NumBytes = alignTo(NumBytes, 8);
728 
729  // If the number of registers having variable arguments is odd,
730  // leave 4 bytes of padding to get to the location where first
731  // variable argument which was passed through register was copied.
732  NumBytes = (NumVarArgRegs % 2 == 0) ? NumBytes : NumBytes + 4;
733 
734  for (int j = FirstVarArgSavedReg, i = 0; j < 6; ++j, ++i) {
735  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_storeri_io))
736  .addReg(SP)
737  .addImm(NumBytes + 4 * i)
738  .addReg(Hexagon::R0 + j)
740  }
741  }
742  }
743 
744  if (hasFP(MF)) {
745  insertAllocframe(MBB, InsertPt, NumBytes);
746  if (AlignStack) {
747  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
748  .addReg(SP)
749  .addImm(-int64_t(MaxAlign.value()));
750  }
751  // If the stack-checking is enabled, and we spilled the callee-saved
752  // registers inline (i.e. did not use a spill function), then call
753  // the stack checker directly.
754  if (EnableStackOVFSanitizer && !PrologueStubs)
755  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
756  .addExternalSymbol("__runtime_stack_check");
757  } else if (NumBytes > 0) {
758  assert(alignTo(NumBytes, 8) == NumBytes);
759  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
760  .addReg(SP)
761  .addImm(-int(NumBytes));
762  }
763 }
764 
765 void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
766  MachineFunction &MF = *MBB.getParent();
767  auto &HST = MF.getSubtarget<HexagonSubtarget>();
768  auto &HII = *HST.getInstrInfo();
769  auto &HRI = *HST.getRegisterInfo();
770  Register SP = HRI.getStackRegister();
771 
773  DebugLoc dl = MBB.findDebugLoc(InsertPt);
774 
775  if (!hasFP(MF)) {
776  MachineFrameInfo &MFI = MF.getFrameInfo();
777  unsigned NumBytes = MFI.getStackSize();
778  if (MF.getFunction().isVarArg() &&
779  MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) {
780  // On Hexagon Linux, deallocate the stack for the register saved area.
781  int NumVarArgRegs = 6 - FirstVarArgSavedReg;
782  int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ?
783  (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4);
784  NumBytes += RegisterSavedAreaSizePlusPadding;
785  }
786  if (NumBytes) {
787  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
788  .addReg(SP)
789  .addImm(NumBytes);
790  }
791  return;
792  }
793 
794  MachineInstr *RetI = getReturn(MBB);
795  unsigned RetOpc = RetI ? RetI->getOpcode() : 0;
796 
797  // Handle EH_RETURN.
798  if (RetOpc == Hexagon::EH_RETURN_JMPR) {
799  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
800  .addDef(Hexagon::D15)
801  .addReg(Hexagon::R30);
802  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP)
803  .addReg(SP)
804  .addReg(Hexagon::R28);
805  return;
806  }
807 
808  // Check for RESTORE_DEALLOC_RET* tail call. Don't emit an extra dealloc-
809  // frame instruction if we encounter it.
810  if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4 ||
811  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC ||
812  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT ||
813  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC) {
814  MachineBasicBlock::iterator It = RetI;
815  ++It;
816  // Delete all instructions after the RESTORE (except labels).
817  while (It != MBB.end()) {
818  if (!It->isLabel())
819  It = MBB.erase(It);
820  else
821  ++It;
822  }
823  return;
824  }
825 
826  // It is possible that the restoring code is a call to a library function.
827  // All of the restore* functions include "deallocframe", so we need to make
828  // sure that we don't add an extra one.
829  bool NeedsDeallocframe = true;
830  if (!MBB.empty() && InsertPt != MBB.begin()) {
831  MachineBasicBlock::iterator PrevIt = std::prev(InsertPt);
832  unsigned COpc = PrevIt->getOpcode();
833  if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 ||
834  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC ||
835  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT ||
836  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC ||
837  COpc == Hexagon::PS_call_nr || COpc == Hexagon::PS_callr_nr)
838  NeedsDeallocframe = false;
839  }
840 
842  !MF.getFunction().isVarArg()) {
843  if (!NeedsDeallocframe)
844  return;
845  // If the returning instruction is PS_jmpret, replace it with
846  // dealloc_return, otherwise just add deallocframe. The function
847  // could be returning via a tail call.
848  if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) {
849  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
850  .addDef(Hexagon::D15)
851  .addReg(Hexagon::R30);
852  return;
853  }
854  unsigned NewOpc = Hexagon::L4_return;
855  MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc))
856  .addDef(Hexagon::D15)
857  .addReg(Hexagon::R30);
858  // Transfer the function live-out registers.
859  NewI->copyImplicitOps(MF, *RetI);
860  MBB.erase(RetI);
861  } else {
862  // L2_deallocframe instruction after it.
863  // Calculate the size of register saved area.
864  int NumVarArgRegs = 6 - FirstVarArgSavedReg;
865  int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ?
866  (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4);
867 
870  : std::prev(Term);
871  if (I == MBB.end() ||
872  (I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT &&
873  I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC &&
874  I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 &&
875  I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC))
876  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
877  .addDef(Hexagon::D15)
878  .addReg(Hexagon::R30);
879  if (RegisterSavedAreaSizePlusPadding != 0)
880  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
881  .addReg(SP)
882  .addImm(RegisterSavedAreaSizePlusPadding);
883  }
884 }
885 
886 void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB,
887  MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const {
888  MachineFunction &MF = *MBB.getParent();
889  auto &HST = MF.getSubtarget<HexagonSubtarget>();
890  auto &HII = *HST.getInstrInfo();
891  auto &HRI = *HST.getRegisterInfo();
892 
893  // Check for overflow.
894  // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
895  const unsigned int ALLOCFRAME_MAX = 16384;
896 
897  // Create a dummy memory operand to avoid allocframe from being treated as
898  // a volatile memory reference.
901 
902  DebugLoc dl = MBB.findDebugLoc(InsertPt);
903  Register SP = HRI.getStackRegister();
904 
905  if (NumBytes >= ALLOCFRAME_MAX) {
906  // Emit allocframe(#0).
907  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
908  .addDef(SP)
909  .addReg(SP)
910  .addImm(0)
911  .addMemOperand(MMO);
912 
913  // Subtract the size from the stack pointer.
914  Register SP = HRI.getStackRegister();
915  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
916  .addReg(SP)
917  .addImm(-int(NumBytes));
918  } else {
919  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
920  .addDef(SP)
921  .addReg(SP)
922  .addImm(NumBytes)
923  .addMemOperand(MMO);
924  }
925 }
926 
927 void HexagonFrameLowering::updateEntryPaths(MachineFunction &MF,
928  MachineBasicBlock &SaveB) const {
929  SetVector<unsigned> Worklist;
930 
931  MachineBasicBlock &EntryB = MF.front();
932  Worklist.insert(EntryB.getNumber());
933 
934  unsigned SaveN = SaveB.getNumber();
935  auto &CSI = MF.getFrameInfo().getCalleeSavedInfo();
936 
937  for (unsigned i = 0; i < Worklist.size(); ++i) {
938  unsigned BN = Worklist[i];
940  for (auto &R : CSI)
941  if (!MBB.isLiveIn(R.getReg()))
942  MBB.addLiveIn(R.getReg());
943  if (BN != SaveN)
944  for (auto &SB : MBB.successors())
945  Worklist.insert(SB->getNumber());
946  }
947 }
948 
949 bool HexagonFrameLowering::updateExitPaths(MachineBasicBlock &MBB,
950  MachineBasicBlock &RestoreB, BitVector &DoneT, BitVector &DoneF,
951  BitVector &Path) const {
952  assert(MBB.getNumber() >= 0);
953  unsigned BN = MBB.getNumber();
954  if (Path[BN] || DoneF[BN])
955  return false;
956  if (DoneT[BN])
957  return true;
958 
959  auto &CSI = MBB.getParent()->getFrameInfo().getCalleeSavedInfo();
960 
961  Path[BN] = true;
962  bool ReachedExit = false;
963  for (auto &SB : MBB.successors())
964  ReachedExit |= updateExitPaths(*SB, RestoreB, DoneT, DoneF, Path);
965 
966  if (!MBB.empty() && MBB.back().isReturn()) {
967  // Add implicit uses of all callee-saved registers to the reached
968  // return instructions. This is to prevent the anti-dependency breaker
969  // from renaming these registers.
970  MachineInstr &RetI = MBB.back();
971  if (!isRestoreCall(RetI.getOpcode()))
972  for (auto &R : CSI)
973  RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
974  ReachedExit = true;
975  }
976 
977  // We don't want to add unnecessary live-ins to the restore block: since
978  // the callee-saved registers are being defined in it, the entry of the
979  // restore block cannot be on the path from the definitions to any exit.
980  if (ReachedExit && &MBB != &RestoreB) {
981  for (auto &R : CSI)
982  if (!MBB.isLiveIn(R.getReg()))
983  MBB.addLiveIn(R.getReg());
984  DoneT[BN] = true;
985  }
986  if (!ReachedExit)
987  DoneF[BN] = true;
988 
989  Path[BN] = false;
990  return ReachedExit;
991 }
992 
993 static std::optional<MachineBasicBlock::iterator>
995  // The CFI instructions need to be inserted right after allocframe.
996  // An exception to this is a situation where allocframe is bundled
997  // with a call: then the CFI instructions need to be inserted before
998  // the packet with the allocframe+call (in case the call throws an
999  // exception).
1000  auto End = B.instr_end();
1001 
1002  for (MachineInstr &I : B) {
1003  MachineBasicBlock::iterator It = I.getIterator();
1004  if (!I.isBundle()) {
1005  if (I.getOpcode() == Hexagon::S2_allocframe)
1006  return std::next(It);
1007  continue;
1008  }
1009  // I is a bundle.
1010  bool HasCall = false, HasAllocFrame = false;
1011  auto T = It.getInstrIterator();
1012  while (++T != End && T->isBundled()) {
1013  if (T->getOpcode() == Hexagon::S2_allocframe)
1014  HasAllocFrame = true;
1015  else if (T->isCall())
1016  HasCall = true;
1017  }
1018  if (HasAllocFrame)
1019  return HasCall ? It : std::next(It);
1020  }
1021  return None;
1022 }
1023 
1025  for (auto &B : MF) {
1026  auto At = findCFILocation(B);
1027  if (At)
1028  insertCFIInstructionsAt(B, At.value());
1029  }
1030 }
1031 
1032 void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB,
1033  MachineBasicBlock::iterator At) const {
1034  MachineFunction &MF = *MBB.getParent();
1035  MachineFrameInfo &MFI = MF.getFrameInfo();
1036  MachineModuleInfo &MMI = MF.getMMI();
1037  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1038  auto &HII = *HST.getInstrInfo();
1039  auto &HRI = *HST.getRegisterInfo();
1040 
1041  // If CFI instructions have debug information attached, something goes
1042  // wrong with the final assembly generation: the prolog_end is placed
1043  // in a wrong location.
1044  DebugLoc DL;
1045  const MCInstrDesc &CFID = HII.get(TargetOpcode::CFI_INSTRUCTION);
1046 
1047  MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
1048  bool HasFP = hasFP(MF);
1049 
1050  if (HasFP) {
1051  unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(), true);
1052  unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(), true);
1053 
1054  // Define CFA via an offset from the value of FP.
1055  //
1056  // -8 -4 0 (SP)
1057  // --+----+----+---------------------
1058  // | FP | LR | increasing addresses -->
1059  // --+----+----+---------------------
1060  // | +-- Old SP (before allocframe)
1061  // +-- New FP (after allocframe)
1062  //
1063  // MCCFIInstruction::cfiDefCfa adds the offset from the register.
1064  // MCCFIInstruction::createOffset takes the offset without sign change.
1065  auto DefCfa = MCCFIInstruction::cfiDefCfa(FrameLabel, DwFPReg, 8);
1066  BuildMI(MBB, At, DL, CFID)
1067  .addCFIIndex(MF.addFrameInst(DefCfa));
1068  // R31 (return addr) = CFA - 4
1069  auto OffR31 = MCCFIInstruction::createOffset(FrameLabel, DwRAReg, -4);
1070  BuildMI(MBB, At, DL, CFID)
1071  .addCFIIndex(MF.addFrameInst(OffR31));
1072  // R30 (frame ptr) = CFA - 8
1073  auto OffR30 = MCCFIInstruction::createOffset(FrameLabel, DwFPReg, -8);
1074  BuildMI(MBB, At, DL, CFID)
1075  .addCFIIndex(MF.addFrameInst(OffR30));
1076  }
1077 
1078  static Register RegsToMove[] = {
1079  Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,
1080  Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
1081  Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
1082  Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
1083  Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9,
1084  Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13,
1085  Hexagon::NoRegister
1086  };
1087 
1088  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1089 
1090  for (unsigned i = 0; RegsToMove[i] != Hexagon::NoRegister; ++i) {
1091  Register Reg = RegsToMove[i];
1092  auto IfR = [Reg] (const CalleeSavedInfo &C) -> bool {
1093  return C.getReg() == Reg;
1094  };
1095  auto F = find_if(CSI, IfR);
1096  if (F == CSI.end())
1097  continue;
1098 
1099  int64_t Offset;
1100  if (HasFP) {
1101  // If the function has a frame pointer (i.e. has an allocframe),
1102  // then the CFA has been defined in terms of FP. Any offsets in
1103  // the following CFI instructions have to be defined relative
1104  // to FP, which points to the bottom of the stack frame.
1105  // The function getFrameIndexReference can still choose to use SP
1106  // for the offset calculation, so we cannot simply call it here.
1107  // Instead, get the offset (relative to the FP) directly.
1108  Offset = MFI.getObjectOffset(F->getFrameIdx());
1109  } else {
1110  Register FrameReg;
1111  Offset =
1112  getFrameIndexReference(MF, F->getFrameIdx(), FrameReg).getFixed();
1113  }
1114  // Subtract 8 to make room for R30 and R31, which are added above.
1115  Offset -= 8;
1116 
1117  if (Reg < Hexagon::D0 || Reg > Hexagon::D15) {
1118  unsigned DwarfReg = HRI.getDwarfRegNum(Reg, true);
1119  auto OffReg = MCCFIInstruction::createOffset(FrameLabel, DwarfReg,
1120  Offset);
1121  BuildMI(MBB, At, DL, CFID)
1122  .addCFIIndex(MF.addFrameInst(OffReg));
1123  } else {
1124  // Split the double regs into subregs, and generate appropriate
1125  // cfi_offsets.
1126  // The only reason, we are split double regs is, llvm-mc does not
1127  // understand paired registers for cfi_offset.
1128  // Eg .cfi_offset r1:0, -64
1129 
1130  Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);
1131  Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);
1132  unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
1133  unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
1134  auto OffHi = MCCFIInstruction::createOffset(FrameLabel, HiDwarfReg,
1135  Offset+4);
1136  BuildMI(MBB, At, DL, CFID)
1137  .addCFIIndex(MF.addFrameInst(OffHi));
1138  auto OffLo = MCCFIInstruction::createOffset(FrameLabel, LoDwarfReg,
1139  Offset);
1140  BuildMI(MBB, At, DL, CFID)
1141  .addCFIIndex(MF.addFrameInst(OffLo));
1142  }
1143  }
1144 }
1145 
1147  if (MF.getFunction().hasFnAttribute(Attribute::Naked))
1148  return false;
1149 
1150  auto &MFI = MF.getFrameInfo();
1151  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1152  bool HasExtraAlign = HRI.hasStackRealignment(MF);
1153  bool HasAlloca = MFI.hasVarSizedObjects();
1154 
1155  // Insert ALLOCFRAME if we need to or at -O0 for the debugger. Think
1156  // that this shouldn't be required, but doing so now because gcc does and
1157  // gdb can't break at the start of the function without it. Will remove if
1158  // this turns out to be a gdb bug.
1159  //
1160  if (MF.getTarget().getOptLevel() == CodeGenOpt::None)
1161  return true;
1162 
1163  // By default we want to use SP (since it's always there). FP requires
1164  // some setup (i.e. ALLOCFRAME).
1165  // Both, alloca and stack alignment modify the stack pointer by an
1166  // undetermined value, so we need to save it at the entry to the function
1167  // (i.e. use allocframe).
1168  if (HasAlloca || HasExtraAlign)
1169  return true;
1170 
1171  if (MFI.getStackSize() > 0) {
1172  // If FP-elimination is disabled, we have to use FP at this point.
1173  const TargetMachine &TM = MF.getTarget();
1174  if (TM.Options.DisableFramePointerElim(MF) || !EliminateFramePointer)
1175  return true;
1177  return true;
1178  }
1179 
1180  const auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1181  if ((MFI.hasCalls() && !enableAllocFrameElim(MF)) || HMFI.hasClobberLR())
1182  return true;
1183 
1184  return false;
1185 }
1186 
1191 };
1192 
1193 static const char *getSpillFunctionFor(Register MaxReg, SpillKind SpillType,
1194  bool Stkchk = false) {
1195  const char * V4SpillToMemoryFunctions[] = {
1196  "__save_r16_through_r17",
1197  "__save_r16_through_r19",
1198  "__save_r16_through_r21",
1199  "__save_r16_through_r23",
1200  "__save_r16_through_r25",
1201  "__save_r16_through_r27" };
1202 
1203  const char * V4SpillToMemoryStkchkFunctions[] = {
1204  "__save_r16_through_r17_stkchk",
1205  "__save_r16_through_r19_stkchk",
1206  "__save_r16_through_r21_stkchk",
1207  "__save_r16_through_r23_stkchk",
1208  "__save_r16_through_r25_stkchk",
1209  "__save_r16_through_r27_stkchk" };
1210 
1211  const char * V4SpillFromMemoryFunctions[] = {
1212  "__restore_r16_through_r17_and_deallocframe",
1213  "__restore_r16_through_r19_and_deallocframe",
1214  "__restore_r16_through_r21_and_deallocframe",
1215  "__restore_r16_through_r23_and_deallocframe",
1216  "__restore_r16_through_r25_and_deallocframe",
1217  "__restore_r16_through_r27_and_deallocframe" };
1218 
1219  const char * V4SpillFromMemoryTailcallFunctions[] = {
1220  "__restore_r16_through_r17_and_deallocframe_before_tailcall",
1221  "__restore_r16_through_r19_and_deallocframe_before_tailcall",
1222  "__restore_r16_through_r21_and_deallocframe_before_tailcall",
1223  "__restore_r16_through_r23_and_deallocframe_before_tailcall",
1224  "__restore_r16_through_r25_and_deallocframe_before_tailcall",
1225  "__restore_r16_through_r27_and_deallocframe_before_tailcall"
1226  };
1227 
1228  const char **SpillFunc = nullptr;
1229 
1230  switch(SpillType) {
1231  case SK_ToMem:
1232  SpillFunc = Stkchk ? V4SpillToMemoryStkchkFunctions
1233  : V4SpillToMemoryFunctions;
1234  break;
1235  case SK_FromMem:
1236  SpillFunc = V4SpillFromMemoryFunctions;
1237  break;
1238  case SK_FromMemTailcall:
1239  SpillFunc = V4SpillFromMemoryTailcallFunctions;
1240  break;
1241  }
1242  assert(SpillFunc && "Unknown spill kind");
1243 
1244  // Spill all callee-saved registers up to the highest register used.
1245  switch (MaxReg) {
1246  case Hexagon::R17:
1247  return SpillFunc[0];
1248  case Hexagon::R19:
1249  return SpillFunc[1];
1250  case Hexagon::R21:
1251  return SpillFunc[2];
1252  case Hexagon::R23:
1253  return SpillFunc[3];
1254  case Hexagon::R25:
1255  return SpillFunc[4];
1256  case Hexagon::R27:
1257  return SpillFunc[5];
1258  default:
1259  llvm_unreachable("Unhandled maximum callee save register");
1260  }
1261  return nullptr;
1262 }
1263 
1266  Register &FrameReg) const {
1267  auto &MFI = MF.getFrameInfo();
1268  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1269 
1270  int Offset = MFI.getObjectOffset(FI);
1271  bool HasAlloca = MFI.hasVarSizedObjects();
1272  bool HasExtraAlign = HRI.hasStackRealignment(MF);
1273  bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None;
1274 
1275  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1276  unsigned FrameSize = MFI.getStackSize();
1277  Register SP = HRI.getStackRegister();
1278  Register FP = HRI.getFrameRegister();
1279  Register AP = HMFI.getStackAlignBaseReg();
1280  // It may happen that AP will be absent even HasAlloca && HasExtraAlign
1281  // is true. HasExtraAlign may be set because of vector spills, without
1282  // aligned locals or aligned outgoing function arguments. Since vector
1283  // spills will ultimately be "unaligned", it is safe to use FP as the
1284  // base register.
1285  // In fact, in such a scenario the stack is actually not required to be
1286  // aligned, although it may end up being aligned anyway, since this
1287  // particular case is not easily detectable. The alignment will be
1288  // unnecessary, but not incorrect.
1289  // Unfortunately there is no quick way to verify that the above is
1290  // indeed the case (and that it's not a result of an error), so just
1291  // assume that missing AP will be replaced by FP.
1292  // (A better fix would be to rematerialize AP from FP and always align
1293  // vector spills.)
1294  bool UseFP = false, UseAP = false; // Default: use SP (except at -O0).
1295  // Use FP at -O0, except when there are objects with extra alignment.
1296  // That additional alignment requirement may cause a pad to be inserted,
1297  // which will make it impossible to use FP to access objects located
1298  // past the pad.
1299  if (NoOpt && !HasExtraAlign)
1300  UseFP = true;
1301  if (MFI.isFixedObjectIndex(FI) || MFI.isObjectPreAllocated(FI)) {
1302  // Fixed and preallocated objects will be located before any padding
1303  // so FP must be used to access them.
1304  UseFP |= (HasAlloca || HasExtraAlign);
1305  } else {
1306  if (HasAlloca) {
1307  if (HasExtraAlign)
1308  UseAP = true;
1309  else
1310  UseFP = true;
1311  }
1312  }
1313 
1314  // If FP was picked, then there had better be FP.
1315  bool HasFP = hasFP(MF);
1316  assert((HasFP || !UseFP) && "This function must have frame pointer");
1317 
1318  // Having FP implies allocframe. Allocframe will store extra 8 bytes:
1319  // FP/LR. If the base register is used to access an object across these
1320  // 8 bytes, then the offset will need to be adjusted by 8.
1321  //
1322  // After allocframe:
1323  // HexagonISelLowering adds 8 to ---+
1324  // the offsets of all stack-based |
1325  // arguments (*) |
1326  // |
1327  // getObjectOffset < 0 0 8 getObjectOffset >= 8
1328  // ------------------------+-----+------------------------> increasing
1329  // <local objects> |FP/LR| <input arguments> addresses
1330  // -----------------+------+-----+------------------------>
1331  // | |
1332  // SP/AP point --+ +-- FP points here (**)
1333  // somewhere on
1334  // this side of FP/LR
1335  //
1336  // (*) See LowerFormalArguments. The FP/LR is assumed to be present.
1337  // (**) *FP == old-FP. FP+0..7 are the bytes of FP/LR.
1338 
1339  // The lowering assumes that FP/LR is present, and so the offsets of
1340  // the formal arguments start at 8. If FP/LR is not there we need to
1341  // reduce the offset by 8.
1342  if (Offset > 0 && !HasFP)
1343  Offset -= 8;
1344 
1345  if (UseFP)
1346  FrameReg = FP;
1347  else if (UseAP)
1348  FrameReg = AP;
1349  else
1350  FrameReg = SP;
1351 
1352  // Calculate the actual offset in the instruction. If there is no FP
1353  // (in other words, no allocframe), then SP will not be adjusted (i.e.
1354  // there will be no SP -= FrameSize), so the frame size should not be
1355  // added to the calculated offset.
1356  int RealOffset = Offset;
1357  if (!UseFP && !UseAP)
1358  RealOffset = FrameSize+Offset;
1359  return StackOffset::getFixed(RealOffset);
1360 }
1361 
1362 bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
1363  const CSIVect &CSI, const HexagonRegisterInfo &HRI,
1364  bool &PrologueStubs) const {
1365  if (CSI.empty())
1366  return true;
1367 
1369  PrologueStubs = false;
1370  MachineFunction &MF = *MBB.getParent();
1371  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1372  auto &HII = *HST.getInstrInfo();
1373 
1374  if (useSpillFunction(MF, CSI)) {
1375  PrologueStubs = true;
1376  Register MaxReg = getMaxCalleeSavedReg(CSI, HRI);
1377  bool StkOvrFlowEnabled = EnableStackOVFSanitizer;
1378  const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem,
1379  StkOvrFlowEnabled);
1380  auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1381  bool IsPIC = HTM.isPositionIndependent();
1382  bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1383 
1384  // Call spill function.
1385  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1386  unsigned SpillOpc;
1387  if (StkOvrFlowEnabled) {
1388  if (LongCalls)
1389  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC
1390  : Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT;
1391  else
1392  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC
1393  : Hexagon::SAVE_REGISTERS_CALL_V4STK;
1394  } else {
1395  if (LongCalls)
1396  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC
1397  : Hexagon::SAVE_REGISTERS_CALL_V4_EXT;
1398  else
1399  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_PIC
1400  : Hexagon::SAVE_REGISTERS_CALL_V4;
1401  }
1402 
1403  MachineInstr *SaveRegsCall =
1404  BuildMI(MBB, MI, DL, HII.get(SpillOpc))
1405  .addExternalSymbol(SpillFun);
1406 
1407  // Add callee-saved registers as use.
1408  addCalleeSaveRegistersAsImpOperand(SaveRegsCall, CSI, false, true);
1409  // Add live in registers.
1410  for (const CalleeSavedInfo &I : CSI)
1411  MBB.addLiveIn(I.getReg());
1412  return true;
1413  }
1414 
1415  for (const CalleeSavedInfo &I : CSI) {
1416  Register Reg = I.getReg();
1417  // Add live in registers. We treat eh_return callee saved register r0 - r3
1418  // specially. They are not really callee saved registers as they are not
1419  // supposed to be killed.
1420  bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);
1421  int FI = I.getFrameIdx();
1422  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1423  HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
1424  if (IsKill)
1425  MBB.addLiveIn(Reg);
1426  }
1427  return true;
1428 }
1429 
1430 bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
1431  const CSIVect &CSI, const HexagonRegisterInfo &HRI) const {
1432  if (CSI.empty())
1433  return false;
1434 
1436  MachineFunction &MF = *MBB.getParent();
1437  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1438  auto &HII = *HST.getInstrInfo();
1439 
1440  if (useRestoreFunction(MF, CSI)) {
1441  bool HasTC = hasTailCall(MBB) || !hasReturn(MBB);
1442  Register MaxR = getMaxCalleeSavedReg(CSI, HRI);
1444  const char *RestoreFn = getSpillFunctionFor(MaxR, Kind);
1445  auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1446  bool IsPIC = HTM.isPositionIndependent();
1447  bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1448 
1449  // Call spill function.
1450  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc()
1451  : MBB.findDebugLoc(MBB.end());
1452  MachineInstr *DeallocCall = nullptr;
1453 
1454  if (HasTC) {
1455  unsigned RetOpc;
1456  if (LongCalls)
1457  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
1458  : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT;
1459  else
1460  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
1461  : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
1462  DeallocCall = BuildMI(MBB, MI, DL, HII.get(RetOpc))
1463  .addExternalSymbol(RestoreFn);
1464  } else {
1465  // The block has a return.
1467  assert(It->isReturn() && std::next(It) == MBB.end());
1468  unsigned RetOpc;
1469  if (LongCalls)
1470  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
1471  : Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT;
1472  else
1473  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC
1474  : Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
1475  DeallocCall = BuildMI(MBB, It, DL, HII.get(RetOpc))
1476  .addExternalSymbol(RestoreFn);
1477  // Transfer the function live-out registers.
1478  DeallocCall->copyImplicitOps(MF, *It);
1479  }
1480  addCalleeSaveRegistersAsImpOperand(DeallocCall, CSI, true, false);
1481  return true;
1482  }
1483 
1484  for (const CalleeSavedInfo &I : CSI) {
1485  Register Reg = I.getReg();
1486  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1487  int FI = I.getFrameIdx();
1488  HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI);
1489  }
1490 
1491  return true;
1492 }
1493 
1497  MachineInstr &MI = *I;
1498  unsigned Opc = MI.getOpcode();
1499  (void)Opc; // Silence compiler warning.
1500  assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
1501  "Cannot handle this call frame pseudo instruction");
1502  return MBB.erase(I);
1503 }
1504 
1506  MachineFunction &MF, RegScavenger *RS) const {
1507  // If this function has uses aligned stack and also has variable sized stack
1508  // objects, then we need to map all spill slots to fixed positions, so that
1509  // they can be accessed through FP. Otherwise they would have to be accessed
1510  // via AP, which may not be available at the particular place in the program.
1511  MachineFrameInfo &MFI = MF.getFrameInfo();
1512  bool HasAlloca = MFI.hasVarSizedObjects();
1513  bool NeedsAlign = (MFI.getMaxAlign() > getStackAlign());
1514 
1515  if (!HasAlloca || !NeedsAlign)
1516  return;
1517 
1518  // Set the physical aligned-stack base address register.
1519  Register AP = 0;
1520  if (const MachineInstr *AI = getAlignaInstr(MF))
1521  AP = AI->getOperand(0).getReg();
1522  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1523  assert(!AP.isValid() || AP.isPhysical());
1524  HMFI.setStackAlignBaseReg(AP);
1525 }
1526 
1527 /// Returns true if there are no caller-saved registers available in class RC.
1529  const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
1531 
1532  auto IsUsed = [&HRI,&MRI] (Register Reg) -> bool {
1533  for (MCRegAliasIterator AI(Reg, &HRI, true); AI.isValid(); ++AI)
1534  if (MRI.isPhysRegUsed(*AI))
1535  return true;
1536  return false;
1537  };
1538 
1539  // Check for an unused caller-saved register. Callee-saved registers
1540  // have become pristine by now.
1541  for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)
1542  if (!IsUsed(*P))
1543  return false;
1544 
1545  // All caller-saved registers are used.
1546  return true;
1547 }
1548 
1549 #ifndef NDEBUG
1550 static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
1551  dbgs() << '{';
1552  for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
1553  Register R = x;
1554  dbgs() << ' ' << printReg(R, &TRI);
1555  }
1556  dbgs() << " }";
1557 }
1558 #endif
1559 
1561  const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
1562  LLVM_DEBUG(dbgs() << __func__ << " on " << MF.getName() << '\n');
1563  MachineFrameInfo &MFI = MF.getFrameInfo();
1564  BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1565 
1566  // Generate a set of unique, callee-saved registers (SRegs), where each
1567  // register in the set is maximal in terms of sub-/super-register relation,
1568  // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
1569 
1570  // (1) For each callee-saved register, add that register and all of its
1571  // sub-registers to SRegs.
1572  LLVM_DEBUG(dbgs() << "Initial CS registers: {");
1573  for (const CalleeSavedInfo &I : CSI) {
1574  Register R = I.getReg();
1575  LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));
1576  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1577  SRegs[*SR] = true;
1578  }
1579  LLVM_DEBUG(dbgs() << " }\n");
1580  LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI);
1581  dbgs() << "\n");
1582 
1583  // (2) For each reserved register, remove that register and all of its
1584  // sub- and super-registers from SRegs.
1586  // Unreserve the stack align register: it is reserved for this function
1587  // only, it still needs to be saved/restored.
1588  Register AP =
1589  MF.getInfo<HexagonMachineFunctionInfo>()->getStackAlignBaseReg();
1590  if (AP.isValid()) {
1591  Reserved[AP] = false;
1592  // Unreserve super-regs if no other subregisters are reserved.
1593  for (MCSuperRegIterator SP(AP, TRI, false); SP.isValid(); ++SP) {
1594  bool HasResSub = false;
1595  for (MCSubRegIterator SB(*SP, TRI, false); SB.isValid(); ++SB) {
1596  if (!Reserved[*SB])
1597  continue;
1598  HasResSub = true;
1599  break;
1600  }
1601  if (!HasResSub)
1602  Reserved[*SP] = false;
1603  }
1604  }
1605 
1606  for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
1607  Register R = x;
1608  for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1609  SRegs[*SR] = false;
1610  }
1611  LLVM_DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI);
1612  dbgs() << "\n");
1613  LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI);
1614  dbgs() << "\n");
1615 
1616  // (3) Collect all registers that have at least one sub-register in SRegs,
1617  // and also have no sub-registers that are reserved. These will be the can-
1618  // didates for saving as a whole instead of their individual sub-registers.
1619  // (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)
1620  BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
1621  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1622  Register R = x;
1623  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
1624  TmpSup[*SR] = true;
1625  }
1626  for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
1627  Register R = x;
1628  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) {
1629  if (!Reserved[*SR])
1630  continue;
1631  TmpSup[R] = false;
1632  break;
1633  }
1634  }
1635  LLVM_DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI);
1636  dbgs() << "\n");
1637 
1638  // (4) Include all super-registers found in (3) into SRegs.
1639  SRegs |= TmpSup;
1640  LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI);
1641  dbgs() << "\n");
1642 
1643  // (5) For each register R in SRegs, if any super-register of R is in SRegs,
1644  // remove R from SRegs.
1645  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1646  Register R = x;
1647  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {
1648  if (!SRegs[*SR])
1649  continue;
1650  SRegs[R] = false;
1651  break;
1652  }
1653  }
1654  LLVM_DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI);
1655  dbgs() << "\n");
1656 
1657  // Now, for each register that has a fixed stack slot, create the stack
1658  // object for it.
1659  CSI.clear();
1660 
1662 
1663  unsigned NumFixed;
1664  int MinOffset = 0; // CS offsets are negative.
1665  const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
1666  for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
1667  if (!SRegs[S->Reg])
1668  continue;
1669  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1670  int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset);
1671  MinOffset = std::min(MinOffset, S->Offset);
1672  CSI.push_back(CalleeSavedInfo(S->Reg, FI));
1673  SRegs[S->Reg] = false;
1674  }
1675 
1676  // There can be some registers that don't have fixed slots. For example,
1677  // we need to store R0-R3 in functions with exception handling. For each
1678  // such register, create a non-fixed stack object.
1679  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1680  Register R = x;
1682  unsigned Size = TRI->getSpillSize(*RC);
1683  int Off = MinOffset - Size;
1684  Align Alignment = std::min(TRI->getSpillAlign(*RC), getStackAlign());
1685  Off &= -Alignment.value();
1686  int FI = MFI.CreateFixedSpillStackObject(Size, Off);
1687  MinOffset = std::min(MinOffset, Off);
1688  CSI.push_back(CalleeSavedInfo(R, FI));
1689  SRegs[R] = false;
1690  }
1691 
1692  LLVM_DEBUG({
1693  dbgs() << "CS information: {";
1694  for (const CalleeSavedInfo &I : CSI) {
1695  int FI = I.getFrameIdx();
1696  int Off = MFI.getObjectOffset(FI);
1697  dbgs() << ' ' << printReg(I.getReg(), TRI) << ":fi#" << FI << ":sp";
1698  if (Off >= 0)
1699  dbgs() << '+';
1700  dbgs() << Off;
1701  }
1702  dbgs() << " }\n";
1703  });
1704 
1705 #ifndef NDEBUG
1706  // Verify that all registers were handled.
1707  bool MissedReg = false;
1708  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1709  Register R = x;
1710  dbgs() << printReg(R, TRI) << ' ';
1711  MissedReg = true;
1712  }
1713  if (MissedReg)
1714  llvm_unreachable("...there are unhandled callee-saved registers!");
1715 #endif
1716 
1717  return true;
1718 }
1719 
1720 bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B,
1722  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1723  MachineInstr *MI = &*It;
1724  DebugLoc DL = MI->getDebugLoc();
1725  Register DstR = MI->getOperand(0).getReg();
1726  Register SrcR = MI->getOperand(1).getReg();
1727  if (!Hexagon::ModRegsRegClass.contains(DstR) ||
1728  !Hexagon::ModRegsRegClass.contains(SrcR))
1729  return false;
1730 
1731  Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1732  BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));
1733  BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR)
1734  .addReg(TmpR, RegState::Kill);
1735 
1736  NewRegs.push_back(TmpR);
1737  B.erase(It);
1738  return true;
1739 }
1740 
1741 bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B,
1743  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1744  MachineInstr *MI = &*It;
1745  if (!MI->getOperand(0).isFI())
1746  return false;
1747 
1748  DebugLoc DL = MI->getDebugLoc();
1749  unsigned Opc = MI->getOpcode();
1750  Register SrcR = MI->getOperand(2).getReg();
1751  bool IsKill = MI->getOperand(2).isKill();
1752  int FI = MI->getOperand(0).getIndex();
1753 
1754  // TmpR = C2_tfrpr SrcR if SrcR is a predicate register
1755  // TmpR = A2_tfrcrr SrcR if SrcR is a modifier register
1756  Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1757  unsigned TfrOpc = (Opc == Hexagon::STriw_pred) ? Hexagon::C2_tfrpr
1758  : Hexagon::A2_tfrcrr;
1759  BuildMI(B, It, DL, HII.get(TfrOpc), TmpR)
1760  .addReg(SrcR, getKillRegState(IsKill));
1761 
1762  // S2_storeri_io FI, 0, TmpR
1763  BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io))
1764  .addFrameIndex(FI)
1765  .addImm(0)
1766  .addReg(TmpR, RegState::Kill)
1767  .cloneMemRefs(*MI);
1768 
1769  NewRegs.push_back(TmpR);
1770  B.erase(It);
1771  return true;
1772 }
1773 
1774 bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B,
1776  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1777  MachineInstr *MI = &*It;
1778  if (!MI->getOperand(1).isFI())
1779  return false;
1780 
1781  DebugLoc DL = MI->getDebugLoc();
1782  unsigned Opc = MI->getOpcode();
1783  Register DstR = MI->getOperand(0).getReg();
1784  int FI = MI->getOperand(1).getIndex();
1785 
1786  // TmpR = L2_loadri_io FI, 0
1787  Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1788  BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)
1789  .addFrameIndex(FI)
1790  .addImm(0)
1791  .cloneMemRefs(*MI);
1792 
1793  // DstR = C2_tfrrp TmpR if DstR is a predicate register
1794  // DstR = A2_tfrrcr TmpR if DstR is a modifier register
1795  unsigned TfrOpc = (Opc == Hexagon::LDriw_pred) ? Hexagon::C2_tfrrp
1796  : Hexagon::A2_tfrrcr;
1797  BuildMI(B, It, DL, HII.get(TfrOpc), DstR)
1798  .addReg(TmpR, RegState::Kill);
1799 
1800  NewRegs.push_back(TmpR);
1801  B.erase(It);
1802  return true;
1803 }
1804 
1805 bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
1807  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1808  MachineInstr *MI = &*It;
1809  if (!MI->getOperand(0).isFI())
1810  return false;
1811 
1812  DebugLoc DL = MI->getDebugLoc();
1813  Register SrcR = MI->getOperand(2).getReg();
1814  bool IsKill = MI->getOperand(2).isKill();
1815  int FI = MI->getOperand(0).getIndex();
1816  auto *RC = &Hexagon::HvxVRRegClass;
1817 
1818  // Insert transfer to general vector register.
1819  // TmpR0 = A2_tfrsi 0x01010101
1820  // TmpR1 = V6_vandqrt Qx, TmpR0
1821  // store FI, 0, TmpR1
1822  Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1823  Register TmpR1 = MRI.createVirtualRegister(RC);
1824 
1825  BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1826  .addImm(0x01010101);
1827 
1828  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1)
1829  .addReg(SrcR, getKillRegState(IsKill))
1830  .addReg(TmpR0, RegState::Kill);
1831 
1832  auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo();
1833  HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI);
1834  expandStoreVec(B, std::prev(It), MRI, HII, NewRegs);
1835 
1836  NewRegs.push_back(TmpR0);
1837  NewRegs.push_back(TmpR1);
1838  B.erase(It);
1839  return true;
1840 }
1841 
1842 bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
1844  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1845  MachineInstr *MI = &*It;
1846  if (!MI->getOperand(1).isFI())
1847  return false;
1848 
1849  DebugLoc DL = MI->getDebugLoc();
1850  Register DstR = MI->getOperand(0).getReg();
1851  int FI = MI->getOperand(1).getIndex();
1852  auto *RC = &Hexagon::HvxVRRegClass;
1853 
1854  // TmpR0 = A2_tfrsi 0x01010101
1855  // TmpR1 = load FI, 0
1856  // DstR = V6_vandvrt TmpR1, TmpR0
1857  Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1858  Register TmpR1 = MRI.createVirtualRegister(RC);
1859 
1860  BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1861  .addImm(0x01010101);
1862  MachineFunction &MF = *B.getParent();
1863  auto *HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1864  HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI);
1865  expandLoadVec(B, std::prev(It), MRI, HII, NewRegs);
1866 
1867  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)
1868  .addReg(TmpR1, RegState::Kill)
1869  .addReg(TmpR0, RegState::Kill);
1870 
1871  NewRegs.push_back(TmpR0);
1872  NewRegs.push_back(TmpR1);
1873  B.erase(It);
1874  return true;
1875 }
1876 
1877 bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
1879  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1880  MachineFunction &MF = *B.getParent();
1881  auto &MFI = MF.getFrameInfo();
1882  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1883  MachineInstr *MI = &*It;
1884  if (!MI->getOperand(0).isFI())
1885  return false;
1886 
1887  // It is possible that the double vector being stored is only partially
1888  // defined. From the point of view of the liveness tracking, it is ok to
1889  // store it as a whole, but if we break it up we may end up storing a
1890  // register that is entirely undefined.
1891  LivePhysRegs LPR(HRI);
1892  LPR.addLiveIns(B);
1894  for (auto R = B.begin(); R != It; ++R) {
1895  Clobbers.clear();
1896  LPR.stepForward(*R, Clobbers);
1897  }
1898 
1899  DebugLoc DL = MI->getDebugLoc();
1900  Register SrcR = MI->getOperand(2).getReg();
1901  Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);
1902  Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
1903  bool IsKill = MI->getOperand(2).isKill();
1904  int FI = MI->getOperand(0).getIndex();
1905 
1906  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1907  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1908  Align HasAlign = MFI.getObjectAlign(FI);
1909  unsigned StoreOpc;
1910 
1911  // Store low part.
1912  if (LPR.contains(SrcLo)) {
1913  StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
1914  : Hexagon::V6_vS32Ub_ai;
1915  BuildMI(B, It, DL, HII.get(StoreOpc))
1916  .addFrameIndex(FI)
1917  .addImm(0)
1918  .addReg(SrcLo, getKillRegState(IsKill))
1919  .cloneMemRefs(*MI);
1920  }
1921 
1922  // Store high part.
1923  if (LPR.contains(SrcHi)) {
1924  StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
1925  : Hexagon::V6_vS32Ub_ai;
1926  BuildMI(B, It, DL, HII.get(StoreOpc))
1927  .addFrameIndex(FI)
1928  .addImm(Size)
1929  .addReg(SrcHi, getKillRegState(IsKill))
1930  .cloneMemRefs(*MI);
1931  }
1932 
1933  B.erase(It);
1934  return true;
1935 }
1936 
1937 bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,
1939  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1940  MachineFunction &MF = *B.getParent();
1941  auto &MFI = MF.getFrameInfo();
1942  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1943  MachineInstr *MI = &*It;
1944  if (!MI->getOperand(1).isFI())
1945  return false;
1946 
1947  DebugLoc DL = MI->getDebugLoc();
1948  Register DstR = MI->getOperand(0).getReg();
1949  Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
1950  Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
1951  int FI = MI->getOperand(1).getIndex();
1952 
1953  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1954  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1955  Align HasAlign = MFI.getObjectAlign(FI);
1956  unsigned LoadOpc;
1957 
1958  // Load low part.
1959  LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
1960  : Hexagon::V6_vL32Ub_ai;
1961  BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)
1962  .addFrameIndex(FI)
1963  .addImm(0)
1964  .cloneMemRefs(*MI);
1965 
1966  // Load high part.
1967  LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
1968  : Hexagon::V6_vL32Ub_ai;
1969  BuildMI(B, It, DL, HII.get(LoadOpc), DstHi)
1970  .addFrameIndex(FI)
1971  .addImm(Size)
1972  .cloneMemRefs(*MI);
1973 
1974  B.erase(It);
1975  return true;
1976 }
1977 
1978 bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B,
1980  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1981  MachineFunction &MF = *B.getParent();
1982  auto &MFI = MF.getFrameInfo();
1983  MachineInstr *MI = &*It;
1984  if (!MI->getOperand(0).isFI())
1985  return false;
1986 
1987  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1988  DebugLoc DL = MI->getDebugLoc();
1989  Register SrcR = MI->getOperand(2).getReg();
1990  bool IsKill = MI->getOperand(2).isKill();
1991  int FI = MI->getOperand(0).getIndex();
1992 
1993  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1994  Align HasAlign = MFI.getObjectAlign(FI);
1995  unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
1996  : Hexagon::V6_vS32Ub_ai;
1997  BuildMI(B, It, DL, HII.get(StoreOpc))
1998  .addFrameIndex(FI)
1999  .addImm(0)
2000  .addReg(SrcR, getKillRegState(IsKill))
2001  .cloneMemRefs(*MI);
2002 
2003  B.erase(It);
2004  return true;
2005 }
2006 
2007 bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,
2009  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
2010  MachineFunction &MF = *B.getParent();
2011  auto &MFI = MF.getFrameInfo();
2012  MachineInstr *MI = &*It;
2013  if (!MI->getOperand(1).isFI())
2014  return false;
2015 
2016  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2017  DebugLoc DL = MI->getDebugLoc();
2018  Register DstR = MI->getOperand(0).getReg();
2019  int FI = MI->getOperand(1).getIndex();
2020 
2021  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
2022  Align HasAlign = MFI.getObjectAlign(FI);
2023  unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
2024  : Hexagon::V6_vL32Ub_ai;
2025  BuildMI(B, It, DL, HII.get(LoadOpc), DstR)
2026  .addFrameIndex(FI)
2027  .addImm(0)
2028  .cloneMemRefs(*MI);
2029 
2030  B.erase(It);
2031  return true;
2032 }
2033 
2034 bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
2035  SmallVectorImpl<Register> &NewRegs) const {
2036  auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
2038  bool Changed = false;
2039 
2040  for (auto &B : MF) {
2041  // Traverse the basic block.
2043  for (auto I = B.begin(), E = B.end(); I != E; I = NextI) {
2044  MachineInstr *MI = &*I;
2045  NextI = std::next(I);
2046  unsigned Opc = MI->getOpcode();
2047 
2048  switch (Opc) {
2049  case TargetOpcode::COPY:
2050  Changed |= expandCopy(B, I, MRI, HII, NewRegs);
2051  break;
2052  case Hexagon::STriw_pred:
2053  case Hexagon::STriw_ctr:
2054  Changed |= expandStoreInt(B, I, MRI, HII, NewRegs);
2055  break;
2056  case Hexagon::LDriw_pred:
2057  case Hexagon::LDriw_ctr:
2058  Changed |= expandLoadInt(B, I, MRI, HII, NewRegs);
2059  break;
2060  case Hexagon::PS_vstorerq_ai:
2061  Changed |= expandStoreVecPred(B, I, MRI, HII, NewRegs);
2062  break;
2063  case Hexagon::PS_vloadrq_ai:
2064  Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs);
2065  break;
2066  case Hexagon::PS_vloadrw_ai:
2067  Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs);
2068  break;
2069  case Hexagon::PS_vstorerw_ai:
2070  Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs);
2071  break;
2072  }
2073  }
2074  }
2075 
2076  return Changed;
2077 }
2078 
2080  BitVector &SavedRegs,
2081  RegScavenger *RS) const {
2082  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2083 
2084  SavedRegs.resize(HRI.getNumRegs());
2085 
2086  // If we have a function containing __builtin_eh_return we want to spill and
2087  // restore all callee saved registers. Pretend that they are used.
2089  for (const MCPhysReg *R = HRI.getCalleeSavedRegs(&MF); *R; ++R)
2090  SavedRegs.set(*R);
2091 
2092  // Replace predicate register pseudo spill code.
2093  SmallVector<Register,8> NewRegs;
2094  expandSpillMacros(MF, NewRegs);
2095  if (OptimizeSpillSlots && !isOptNone(MF))
2096  optimizeSpillSlots(MF, NewRegs);
2097 
2098  // We need to reserve a spill slot if scavenging could potentially require
2099  // spilling a scavenged register.
2100  if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {
2101  MachineFrameInfo &MFI = MF.getFrameInfo();
2104  // Reserve an int register in any case, because it could be used to hold
2105  // the stack offset in case it does not fit into a spill instruction.
2106  SpillRCs.insert(&Hexagon::IntRegsRegClass);
2107 
2108  for (Register VR : NewRegs)
2109  SpillRCs.insert(MRI.getRegClass(VR));
2110 
2111  for (const auto *RC : SpillRCs) {
2112  if (!needToReserveScavengingSpillSlots(MF, HRI, RC))
2113  continue;
2114  unsigned Num = 1;
2115  switch (RC->getID()) {
2116  case Hexagon::IntRegsRegClassID:
2117  Num = NumberScavengerSlots;
2118  break;
2119  case Hexagon::HvxQRRegClassID:
2120  Num = 2; // Vector predicate spills also need a vector register.
2121  break;
2122  }
2123  unsigned S = HRI.getSpillSize(*RC);
2124  Align A = HRI.getSpillAlign(*RC);
2125  for (unsigned i = 0; i < Num; i++) {
2126  int NewFI = MFI.CreateSpillStackObject(S, A);
2127  RS->addScavengingFrameIndex(NewFI);
2128  }
2129  }
2130  }
2131 
2132  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2133 }
2134 
2135 Register HexagonFrameLowering::findPhysReg(MachineFunction &MF,
2139  const TargetRegisterClass *RC) const {
2140  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2141  auto &MRI = MF.getRegInfo();
2142 
2143  auto isDead = [&FIR,&DeadMap] (Register Reg) -> bool {
2144  auto F = DeadMap.find({Reg,0});
2145  if (F == DeadMap.end())
2146  return false;
2147  for (auto &DR : F->second)
2148  if (DR.contains(FIR))
2149  return true;
2150  return false;
2151  };
2152 
2153  for (Register Reg : RC->getRawAllocationOrder(MF)) {
2154  bool Dead = true;
2155  for (auto R : HexagonBlockRanges::expandToSubRegs({Reg,0}, MRI, HRI)) {
2156  if (isDead(R.Reg))
2157  continue;
2158  Dead = false;
2159  break;
2160  }
2161  if (Dead)
2162  return Reg;
2163  }
2164  return 0;
2165 }
2166 
2167 void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
2168  SmallVectorImpl<Register> &VRegs) const {
2169  auto &HST = MF.getSubtarget<HexagonSubtarget>();
2170  auto &HII = *HST.getInstrInfo();
2171  auto &HRI = *HST.getRegisterInfo();
2172  auto &MRI = MF.getRegInfo();
2173  HexagonBlockRanges HBR(MF);
2174 
2175  using BlockIndexMap =
2176  std::map<MachineBasicBlock *, HexagonBlockRanges::InstrIndexMap>;
2177  using BlockRangeMap =
2178  std::map<MachineBasicBlock *, HexagonBlockRanges::RangeList>;
2179  using IndexType = HexagonBlockRanges::IndexType;
2180 
2181  struct SlotInfo {
2182  BlockRangeMap Map;
2183  unsigned Size = 0;
2184  const TargetRegisterClass *RC = nullptr;
2185 
2186  SlotInfo() = default;
2187  };
2188 
2189  BlockIndexMap BlockIndexes;
2190  SmallSet<int,4> BadFIs;
2191  std::map<int,SlotInfo> FIRangeMap;
2192 
2193  // Accumulate register classes: get a common class for a pre-existing
2194  // class HaveRC and a new class NewRC. Return nullptr if a common class
2195  // cannot be found, otherwise return the resulting class. If HaveRC is
2196  // nullptr, assume that it is still unset.
2197  auto getCommonRC =
2198  [](const TargetRegisterClass *HaveRC,
2199  const TargetRegisterClass *NewRC) -> const TargetRegisterClass * {
2200  if (HaveRC == nullptr || HaveRC == NewRC)
2201  return NewRC;
2202  // Different classes, both non-null. Pick the more general one.
2203  if (HaveRC->hasSubClassEq(NewRC))
2204  return HaveRC;
2205  if (NewRC->hasSubClassEq(HaveRC))
2206  return NewRC;
2207  return nullptr;
2208  };
2209 
2210  // Scan all blocks in the function. Check all occurrences of frame indexes,
2211  // and collect relevant information.
2212  for (auto &B : MF) {
2213  std::map<int,IndexType> LastStore, LastLoad;
2214  // Emplace appears not to be supported in gcc 4.7.2-4.
2215  //auto P = BlockIndexes.emplace(&B, HexagonBlockRanges::InstrIndexMap(B));
2216  auto P = BlockIndexes.insert(
2217  std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B)));
2218  auto &IndexMap = P.first->second;
2219  LLVM_DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n"
2220  << IndexMap << '\n');
2221 
2222  for (auto &In : B) {
2223  int LFI, SFI;
2224  bool Load = HII.isLoadFromStackSlot(In, LFI) && !HII.isPredicated(In);
2225  bool Store = HII.isStoreToStackSlot(In, SFI) && !HII.isPredicated(In);
2226  if (Load && Store) {
2227  // If it's both a load and a store, then we won't handle it.
2228  BadFIs.insert(LFI);
2229  BadFIs.insert(SFI);
2230  continue;
2231  }
2232  // Check for register classes of the register used as the source for
2233  // the store, and the register used as the destination for the load.
2234  // Also, only accept base+imm_offset addressing modes. Other addressing
2235  // modes can have side-effects (post-increments, etc.). For stack
2236  // slots they are very unlikely, so there is not much loss due to
2237  // this restriction.
2238  if (Load || Store) {
2239  int TFI = Load ? LFI : SFI;
2240  unsigned AM = HII.getAddrMode(In);
2241  SlotInfo &SI = FIRangeMap[TFI];
2242  bool Bad = (AM != HexagonII::BaseImmOffset);
2243  if (!Bad) {
2244  // If the addressing mode is ok, check the register class.
2245  unsigned OpNum = Load ? 0 : 2;
2246  auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF);
2247  RC = getCommonRC(SI.RC, RC);
2248  if (RC == nullptr)
2249  Bad = true;
2250  else
2251  SI.RC = RC;
2252  }
2253  if (!Bad) {
2254  // Check sizes.
2255  unsigned S = HII.getMemAccessSize(In);
2256  if (SI.Size != 0 && SI.Size != S)
2257  Bad = true;
2258  else
2259  SI.Size = S;
2260  }
2261  if (!Bad) {
2262  for (auto *Mo : In.memoperands()) {
2263  if (!Mo->isVolatile() && !Mo->isAtomic())
2264  continue;
2265  Bad = true;
2266  break;
2267  }
2268  }
2269  if (Bad)
2270  BadFIs.insert(TFI);
2271  }
2272 
2273  // Locate uses of frame indices.
2274  for (unsigned i = 0, n = In.getNumOperands(); i < n; ++i) {
2275  const MachineOperand &Op = In.getOperand(i);
2276  if (!Op.isFI())
2277  continue;
2278  int FI = Op.getIndex();
2279  // Make sure that the following operand is an immediate and that
2280  // it is 0. This is the offset in the stack object.
2281  if (i+1 >= n || !In.getOperand(i+1).isImm() ||
2282  In.getOperand(i+1).getImm() != 0)
2283  BadFIs.insert(FI);
2284  if (BadFIs.count(FI))
2285  continue;
2286 
2287  IndexType Index = IndexMap.getIndex(&In);
2288  if (Load) {
2289  if (LastStore[FI] == IndexType::None)
2290  LastStore[FI] = IndexType::Entry;
2291  LastLoad[FI] = Index;
2292  } else if (Store) {
2293  HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2294  if (LastStore[FI] != IndexType::None)
2295  RL.add(LastStore[FI], LastLoad[FI], false, false);
2296  else if (LastLoad[FI] != IndexType::None)
2297  RL.add(IndexType::Entry, LastLoad[FI], false, false);
2298  LastLoad[FI] = IndexType::None;
2299  LastStore[FI] = Index;
2300  } else {
2301  BadFIs.insert(FI);
2302  }
2303  }
2304  }
2305 
2306  for (auto &I : LastLoad) {
2307  IndexType LL = I.second;
2308  if (LL == IndexType::None)
2309  continue;
2310  auto &RL = FIRangeMap[I.first].Map[&B];
2311  IndexType &LS = LastStore[I.first];
2312  if (LS != IndexType::None)
2313  RL.add(LS, LL, false, false);
2314  else
2315  RL.add(IndexType::Entry, LL, false, false);
2316  LS = IndexType::None;
2317  }
2318  for (auto &I : LastStore) {
2319  IndexType LS = I.second;
2320  if (LS == IndexType::None)
2321  continue;
2322  auto &RL = FIRangeMap[I.first].Map[&B];
2323  RL.add(LS, IndexType::None, false, false);
2324  }
2325  }
2326 
2327  LLVM_DEBUG({
2328  for (auto &P : FIRangeMap) {
2329  dbgs() << "fi#" << P.first;
2330  if (BadFIs.count(P.first))
2331  dbgs() << " (bad)";
2332  dbgs() << " RC: ";
2333  if (P.second.RC != nullptr)
2334  dbgs() << HRI.getRegClassName(P.second.RC) << '\n';
2335  else
2336  dbgs() << "<null>\n";
2337  for (auto &R : P.second.Map)
2338  dbgs() << " " << printMBBReference(*R.first) << " { " << R.second
2339  << "}\n";
2340  }
2341  });
2342 
2343  // When a slot is loaded from in a block without being stored to in the
2344  // same block, it is live-on-entry to this block. To avoid CFG analysis,
2345  // consider this slot to be live-on-exit from all blocks.
2346  SmallSet<int,4> LoxFIs;
2347 
2348  std::map<MachineBasicBlock*,std::vector<int>> BlockFIMap;
2349 
2350  for (auto &P : FIRangeMap) {
2351  // P = pair(FI, map: BB->RangeList)
2352  if (BadFIs.count(P.first))
2353  continue;
2354  for (auto &B : MF) {
2355  auto F = P.second.Map.find(&B);
2356  // F = pair(BB, RangeList)
2357  if (F == P.second.Map.end() || F->second.empty())
2358  continue;
2359  HexagonBlockRanges::IndexRange &IR = F->second.front();
2360  if (IR.start() == IndexType::Entry)
2361  LoxFIs.insert(P.first);
2362  BlockFIMap[&B].push_back(P.first);
2363  }
2364  }
2365 
2366  LLVM_DEBUG({
2367  dbgs() << "Block-to-FI map (* -- live-on-exit):\n";
2368  for (auto &P : BlockFIMap) {
2369  auto &FIs = P.second;
2370  if (FIs.empty())
2371  continue;
2372  dbgs() << " " << printMBBReference(*P.first) << ": {";
2373  for (auto I : FIs) {
2374  dbgs() << " fi#" << I;
2375  if (LoxFIs.count(I))
2376  dbgs() << '*';
2377  }
2378  dbgs() << " }\n";
2379  }
2380  });
2381 
2382 #ifndef NDEBUG
2383  bool HasOptLimit = SpillOptMax.getPosition();
2384 #endif
2385 
2386  // eliminate loads, when all loads eliminated, eliminate all stores.
2387  for (auto &B : MF) {
2388  auto F = BlockIndexes.find(&B);
2389  assert(F != BlockIndexes.end());
2390  HexagonBlockRanges::InstrIndexMap &IM = F->second;
2391  HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM);
2392  HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM);
2393  LLVM_DEBUG(dbgs() << printMBBReference(B) << " dead map\n"
2395 
2396  for (auto FI : BlockFIMap[&B]) {
2397  if (BadFIs.count(FI))
2398  continue;
2399  LLVM_DEBUG(dbgs() << "Working on fi#" << FI << '\n');
2400  HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2401  for (auto &Range : RL) {
2402  LLVM_DEBUG(dbgs() << "--Examining range:" << RL << '\n');
2403  if (!IndexType::isInstr(Range.start()) ||
2404  !IndexType::isInstr(Range.end()))
2405  continue;
2406  MachineInstr &SI = *IM.getInstr(Range.start());
2407  MachineInstr &EI = *IM.getInstr(Range.end());
2408  assert(SI.mayStore() && "Unexpected start instruction");
2409  assert(EI.mayLoad() && "Unexpected end instruction");
2410  MachineOperand &SrcOp = SI.getOperand(2);
2411 
2413  SrcOp.getSubReg() };
2414  auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
2415  // The this-> is needed to unconfuse MSVC.
2416  Register FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
2417  LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI)
2418  << '\n');
2419  if (FoundR == 0)
2420  continue;
2421 #ifndef NDEBUG
2422  if (HasOptLimit) {
2423  if (SpillOptCount >= SpillOptMax)
2424  return;
2425  SpillOptCount++;
2426  }
2427 #endif
2428 
2429  // Generate the copy-in: "FoundR = COPY SrcR" at the store location.
2430  MachineBasicBlock::iterator StartIt = SI.getIterator(), NextIt;
2431  MachineInstr *CopyIn = nullptr;
2432  if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) {
2433  const DebugLoc &DL = SI.getDebugLoc();
2434  CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)
2435  .add(SrcOp);
2436  }
2437 
2438  ++StartIt;
2439  // Check if this is a last store and the FI is live-on-exit.
2440  if (LoxFIs.count(FI) && (&Range == &RL.back())) {
2441  // Update store's source register.
2442  if (unsigned SR = SrcOp.getSubReg())
2443  SrcOp.setReg(HRI.getSubReg(FoundR, SR));
2444  else
2445  SrcOp.setReg(FoundR);
2446  SrcOp.setSubReg(0);
2447  // We are keeping this register live.
2448  SrcOp.setIsKill(false);
2449  } else {
2450  B.erase(&SI);
2451  IM.replaceInstr(&SI, CopyIn);
2452  }
2453 
2454  auto EndIt = std::next(EI.getIterator());
2455  for (auto It = StartIt; It != EndIt; It = NextIt) {
2456  MachineInstr &MI = *It;
2457  NextIt = std::next(It);
2458  int TFI;
2459  if (!HII.isLoadFromStackSlot(MI, TFI) || TFI != FI)
2460  continue;
2461  Register DstR = MI.getOperand(0).getReg();
2462  assert(MI.getOperand(0).getSubReg() == 0);
2463  MachineInstr *CopyOut = nullptr;
2464  if (DstR != FoundR) {
2465  DebugLoc DL = MI.getDebugLoc();
2466  unsigned MemSize = HII.getMemAccessSize(MI);
2467  assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
2468  unsigned CopyOpc = TargetOpcode::COPY;
2469  if (HII.isSignExtendingLoad(MI))
2470  CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;
2471  else if (HII.isZeroExtendingLoad(MI))
2472  CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;
2473  CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)
2474  .addReg(FoundR, getKillRegState(&MI == &EI));
2475  }
2476  IM.replaceInstr(&MI, CopyOut);
2477  B.erase(It);
2478  }
2479 
2480  // Update the dead map.
2481  HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 };
2482  for (auto RR : HexagonBlockRanges::expandToSubRegs(FoundRR, MRI, HRI))
2483  DM[RR].subtract(Range);
2484  } // for Range in range list
2485  }
2486  }
2487 }
2488 
2489 void HexagonFrameLowering::expandAlloca(MachineInstr *AI,
2490  const HexagonInstrInfo &HII, Register SP, unsigned CF) const {
2491  MachineBasicBlock &MB = *AI->getParent();
2492  DebugLoc DL = AI->getDebugLoc();
2493  unsigned A = AI->getOperand(2).getImm();
2494 
2495  // Have
2496  // Rd = alloca Rs, #A
2497  //
2498  // If Rs and Rd are different registers, use this sequence:
2499  // Rd = sub(r29, Rs)
2500  // r29 = sub(r29, Rs)
2501  // Rd = and(Rd, #-A) ; if necessary
2502  // r29 = and(r29, #-A) ; if necessary
2503  // Rd = add(Rd, #CF) ; CF size aligned to at most A
2504  // otherwise, do
2505  // Rd = sub(r29, Rs)
2506  // Rd = and(Rd, #-A) ; if necessary
2507  // r29 = Rd
2508  // Rd = add(Rd, #CF) ; CF size aligned to at most A
2509 
2510  MachineOperand &RdOp = AI->getOperand(0);
2511  MachineOperand &RsOp = AI->getOperand(1);
2512  Register Rd = RdOp.getReg(), Rs = RsOp.getReg();
2513 
2514  // Rd = sub(r29, Rs)
2515  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
2516  .addReg(SP)
2517  .addReg(Rs);
2518  if (Rs != Rd) {
2519  // r29 = sub(r29, Rs)
2520  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)
2521  .addReg(SP)
2522  .addReg(Rs);
2523  }
2524  if (A > 8) {
2525  // Rd = and(Rd, #-A)
2526  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
2527  .addReg(Rd)
2528  .addImm(-int64_t(A));
2529  if (Rs != Rd)
2530  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)
2531  .addReg(SP)
2532  .addImm(-int64_t(A));
2533  }
2534  if (Rs == Rd) {
2535  // r29 = Rd
2536  BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)
2537  .addReg(Rd);
2538  }
2539  if (CF > 0) {
2540  // Rd = add(Rd, #CF)
2541  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
2542  .addReg(Rd)
2543  .addImm(CF);
2544  }
2545 }
2546 
2548  const MachineFrameInfo &MFI = MF.getFrameInfo();
2549  if (!MFI.hasVarSizedObjects())
2550  return false;
2551  // Do not check for max stack object alignment here, because the stack
2552  // may not be complete yet. Assume that we will need PS_aligna if there
2553  // are variable-sized objects.
2554  return true;
2555 }
2556 
2558  const MachineFunction &MF) const {
2559  for (auto &B : MF)
2560  for (auto &I : B)
2561  if (I.getOpcode() == Hexagon::PS_aligna)
2562  return &I;
2563  return nullptr;
2564 }
2565 
2566 /// Adds all callee-saved registers as implicit uses or defs to the
2567 /// instruction.
2568 void HexagonFrameLowering::addCalleeSaveRegistersAsImpOperand(MachineInstr *MI,
2569  const CSIVect &CSI, bool IsDef, bool IsKill) const {
2570  // Add the callee-saved registers as implicit uses.
2571  for (auto &R : CSI)
2572  MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
2573 }
2574 
2575 /// Determine whether the callee-saved register saves and restores should
2576 /// be generated via inline code. If this function returns "true", inline
2577 /// code will be generated. If this function returns "false", additional
2578 /// checks are performed, which may still lead to the inline code.
2579 bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF,
2580  const CSIVect &CSI) const {
2582  return true;
2584  return true;
2585  if (!hasFP(MF))
2586  return true;
2587  if (!isOptSize(MF) && !isMinSize(MF))
2589  return true;
2590 
2591  // Check if CSI only has double registers, and if the registers form
2592  // a contiguous block starting from D8.
2593  BitVector Regs(Hexagon::NUM_TARGET_REGS);
2594  for (const CalleeSavedInfo &I : CSI) {
2595  Register R = I.getReg();
2596  if (!Hexagon::DoubleRegsRegClass.contains(R))
2597  return true;
2598  Regs[R] = true;
2599  }
2600  int F = Regs.find_first();
2601  if (F != Hexagon::D8)
2602  return true;
2603  while (F >= 0) {
2604  int N = Regs.find_next(F);
2605  if (N >= 0 && N != F+1)
2606  return true;
2607  F = N;
2608  }
2609 
2610  return false;
2611 }
2612 
2613 bool HexagonFrameLowering::useSpillFunction(const MachineFunction &MF,
2614  const CSIVect &CSI) const {
2615  if (shouldInlineCSR(MF, CSI))
2616  return false;
2617  unsigned NumCSI = CSI.size();
2618  if (NumCSI <= 1)
2619  return false;
2620 
2621  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs
2623  return Threshold < NumCSI;
2624 }
2625 
2626 bool HexagonFrameLowering::useRestoreFunction(const MachineFunction &MF,
2627  const CSIVect &CSI) const {
2628  if (shouldInlineCSR(MF, CSI))
2629  return false;
2630  // The restore functions do a bit more than just restoring registers.
2631  // The non-returning versions will go back directly to the caller's
2632  // caller, others will clean up the stack frame in preparation for
2633  // a tail call. Using them can still save code size even if only one
2634  // register is getting restores. Make the decision based on -Oz:
2635  // using -Os will use inline restore for a single register.
2636  if (isMinSize(MF))
2637  return true;
2638  unsigned NumCSI = CSI.size();
2639  if (NumCSI <= 1)
2640  return false;
2641 
2642  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs-1
2644  return Threshold < NumCSI;
2645 }
2646 
2647 bool HexagonFrameLowering::mayOverflowFrameOffset(MachineFunction &MF) const {
2648  unsigned StackSize = MF.getFrameInfo().estimateStackSize(MF);
2649  auto &HST = MF.getSubtarget<HexagonSubtarget>();
2650  // A fairly simplistic guess as to whether a potential load/store to a
2651  // stack location could require an extra register.
2652  if (HST.useHVXOps() && StackSize > 256)
2653  return true;
2654 
2655  // Check if the function has store-immediate instructions that access
2656  // the stack. Since the offset field is not extendable, if the stack
2657  // size exceeds the offset limit (6 bits, shifted), the stores will
2658  // require a new base register.
2659  bool HasImmStack = false;
2660  unsigned MinLS = ~0u; // Log_2 of the memory access size.
2661 
2662  for (const MachineBasicBlock &B : MF) {
2663  for (const MachineInstr &MI : B) {
2664  unsigned LS = 0;
2665  switch (MI.getOpcode()) {
2666  case Hexagon::S4_storeirit_io:
2667  case Hexagon::S4_storeirif_io:
2668  case Hexagon::S4_storeiri_io:
2669  ++LS;
2670  [[fallthrough]];
2671  case Hexagon::S4_storeirht_io:
2672  case Hexagon::S4_storeirhf_io:
2673  case Hexagon::S4_storeirh_io:
2674  ++LS;
2675  [[fallthrough]];
2676  case Hexagon::S4_storeirbt_io:
2677  case Hexagon::S4_storeirbf_io:
2678  case Hexagon::S4_storeirb_io:
2679  if (MI.getOperand(0).isFI())
2680  HasImmStack = true;
2681  MinLS = std::min(MinLS, LS);
2682  break;
2683  }
2684  }
2685  }
2686 
2687  if (HasImmStack)
2688  return !isUInt<6>(StackSize >> MinLS);
2689 
2690  return false;
2691 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
llvm::MachineDominatorTree::findNearestCommonDominator
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B.
Definition: MachineDominators.h:160
i
i
Definition: README.txt:29
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:156
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:182
CmpMode::FP
@ FP
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:355
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:75
llvm::MachineFrameInfo::estimateStackSize
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
Definition: MachineFrameInfo.cpp:137
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MachineRegisterInfo::isPhysRegUsed
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:587
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::HexagonRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: HexagonRegisterInfo.cpp:119
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:591
Optional.h
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
llvm::AArch64PACKey::ID
ID
Definition: AArch64BaseInfo.h:818
llvm::createHexagonCallFrameInformation
FunctionPass * createHexagonCallFrameInformation()
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MachineModuleInfo::getContext
const MCContext & getContext() const
Definition: MachineModuleInfo.h:143
llvm::Function::hasOptNone
bool hasOptNone() const
Do not optimize this function (-O0).
Definition: Function.h:639
getMax32BitSubRegister
static Register getMax32BitSubRegister(Register Reg, const TargetRegisterInfo &TRI, bool hireg=true)
Map a register pair Reg to the subregister that has the greater "number", i.e.
Definition: HexagonFrameLowering.cpp:250
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
T
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
Pass.h
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
DM
static RegisterPass< DebugifyModulePass > DM("debugify", "Attach debug info to everything")
llvm::SetVector::size
size_type size() const
Determine the number of elements in the SetVector.
Definition: SetVector.h:77
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1056
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:117
llvm::HexagonFrameLowering::getFrameIndexReference
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: HexagonFrameLowering.cpp:1265
HexagonSubtarget.h
llvm::HexagonTargetMachine
Definition: HexagonTargetMachine.h:25
ErrorHandling.h
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::HexagonBlockRanges::IndexRange
Definition: HexagonBlockRanges.h:81
RPO
rpo function Deduce function attributes in RPO
Definition: FunctionAttrs.cpp:1903
dump_registers
static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI)
Definition: HexagonFrameLowering.cpp:1550
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
MachineBasicBlock.h
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::MachineFunction::getNumBlockIDs
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
Definition: MachineFunction.h:799
llvm::MachineBasicBlock::findDebugLoc
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
Definition: MachineBasicBlock.cpp:1388
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
EnableStackOVFSanitizer
static cl::opt< bool > EnableStackOVFSanitizer("enable-stackovf-sanitizer", cl::Hidden, cl::desc("Enable runtime checks for stack overflow."), cl::init(false))
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
DenseMap.h
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:334
llvm::MachineFrameInfo::setStackSize
void setStackSize(uint64_t Size)
Set the size of the stack.
Definition: MachineFrameInfo.h:588
llvm::MachineFrameInfo::isObjectPreAllocated
bool isObjectPreAllocated(int ObjectIdx) const
Return true if the object was pre-allocated into the local block.
Definition: MachineFrameInfo.h:463
llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
Definition: HexagonFrameLowering.cpp:1560
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:127
llvm::MachineFrameInfo::setMaxCallFrameSize
void setMaxCallFrameSize(unsigned S)
Definition: MachineFrameInfo.h:664
HexagonFrameLowering.h
SpillOptMax
static cl::opt< unsigned > SpillOptMax("spill-opt-max", cl::Hidden, cl::init(std::numeric_limits< unsigned >::max()))
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::MachineDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachineDominators.h:114
llvm::MachineBasicBlock::back
MachineInstr & back()
Definition: MachineBasicBlock.h:285
llvm::HexagonRegisterInfo::isEHReturnCalleeSaveReg
bool isEHReturnCalleeSaveReg(Register Reg) const
Definition: HexagonRegisterInfo.cpp:61
llvm::MachineBasicBlock::terminators
iterator_range< iterator > terminators()
Definition: MachineBasicBlock.h:325
HexagonTargetMachine.h
isMinSize
static bool isMinSize(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:391
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineDominatorTree::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: MachineDominators.cpp:54
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:654
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
HexagonBaseInfo.h
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:265
llvm::HexagonRegisterInfo::getCallerSavedRegs
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
Definition: HexagonRegisterInfo.cpp:67
MachineRegisterInfo.h
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1314
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::HexagonFrameLowering::insertCFIInstructions
void insertCFIInstructions(MachineFunction &MF) const
Definition: HexagonFrameLowering.cpp:1024
llvm::HexagonSubtarget::isEnvironmentMusl
bool isEnvironmentMusl() const
Definition: HexagonSubtarget.h:115
CommandLine.h
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
SK_ToMem
@ SK_ToMem
Definition: HexagonFrameLowering.cpp:1188
R2
#define R2(n)
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:866
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
SpillOptCount
static unsigned SpillOptCount
Definition: HexagonFrameLowering.cpp:198
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::HexagonBlockRanges::RegisterRef::Reg
llvm::Register Reg
Definition: HexagonBlockRanges.h:36
llvm::msgpack::Type::Map
@ Map
llvm::HexagonMachineFunctionInfo
Hexagon target-specific information for each MachineFunction.
Definition: HexagonMachineFunctionInfo.h:25
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:517
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1476
isOptSize
static bool isOptSize(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:386
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::ARM_PROC::A
@ A
Definition: ARMBaseInfo.h:34
hasTailCall
static bool hasTailCall(const MachineBasicBlock &MBB)
Returns true if MBB has a machine instructions that indicates a tail call in the block.
Definition: HexagonFrameLowering.cpp:341
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:203
llvm::HexagonFrameLowering::enableCalleeSaveSkip
bool enableCalleeSaveSkip(const MachineFunction &MF) const override
Returns true if the target can safely skip saving callee-saved registers for noreturn nounwind functi...
Definition: HexagonFrameLowering.cpp:561
getSpillFunctionFor
static const char * getSpillFunctionFor(Register MaxReg, SpillKind SpillType, bool Stkchk=false)
Definition: HexagonFrameLowering.cpp:1193
SI
@ SI
Definition: SIInstrInfo.cpp:7966
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::HexagonFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: HexagonFrameLowering.cpp:1146
llvm::HexagonBlockRanges::RegisterRef
Definition: HexagonBlockRanges.h:35
PseudoSourceValue.h
llvm::HexagonBlockRanges::PrintRangeMap
Definition: HexagonBlockRanges.h:152
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:196
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:74
llvm::HexagonFrameLowering::needsAligna
bool needsAligna(const MachineFunction &MF) const
Definition: HexagonFrameLowering.cpp:2547
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
BitVector.h
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:585
needsStackFrame
static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR, const HexagonRegisterInfo &HRI)
Checks if the basic block contains any instruction that needs a stack frame to be already in place.
Definition: HexagonFrameLowering.cpp:288
DebugLoc.h
IR
Statically lint checks LLVM IR
Definition: Lint.cpp:746
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:526
llvm::BitVector
Definition: BitVector.h:75
getMaxCalleeSavedReg
static Register getMaxCalleeSavedReg(ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo &TRI)
Returns the callee saved register with the largest id in the vector.
Definition: HexagonFrameLowering.cpp:270
HexagonInstrInfo.h
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:688
llvm::pdb::PDB_ColorItem::Path
@ Path
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::HexagonBlockRanges::RegisterRef::Sub
unsigned Sub
Definition: HexagonBlockRanges.h:37
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
findCFILocation
static std::optional< MachineBasicBlock::iterator > findCFILocation(MachineBasicBlock &B)
Definition: HexagonFrameLowering.cpp:994
EnableShrinkWrapping
static cl::opt< bool > EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden, cl::desc("Enable stack frame shrink wrapping"))
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::HexagonMachineFunctionInfo::hasEHReturn
bool hasEHReturn() const
Definition: HexagonMachineFunctionInfo.h:81
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:41
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::MachineFrameInfo::CreateSpillStackObject
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
Definition: MachineFrameInfo.cpp:66
llvm::HexagonBlockRanges::RangeList
Definition: HexagonBlockRanges.h:108
needToReserveScavengingSpillSlots
static bool needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC)
Returns true if there are no caller-saved registers available in class RC.
Definition: HexagonFrameLowering.cpp:1528
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:647
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:124
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:608
llvm::MachineInstrBundleIterator::getInstrIterator
instr_iterator getInstrIterator() const
Definition: MachineInstrBundleIterator.h:274
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:292
SpillFuncThreshold
static cl::opt< int > SpillFuncThreshold("spill-func-threshold", cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"), cl::init(6))
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
DisableDeallocRet
static cl::opt< bool > DisableDeallocRet("disable-hexagon-dealloc-ret", cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"))
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:629
llvm::cl::opt< bool >
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:445
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:286
llvm::MachineFrameInfo::CreateFixedSpillStackObject
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:102
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:165
llvm::CodeGenOpt::Default
@ Default
Definition: CodeGen.h:55
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::initializeHexagonCallFrameInformationPass
void initializeHexagonCallFrameInformationPass(PassRegistry &)
llvm::HexagonBlockRanges::InstrIndexMap::replaceInstr
void replaceInstr(MachineInstr *OldMI, MachineInstr *NewMI)
Definition: HexagonBlockRanges.cpp:206
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:470
EliminateFramePointer
static cl::opt< bool > EliminateFramePointer("hexagon-fp-elim", cl::init(true), cl::Hidden, cl::desc("Refrain from using FP whenever possible"))
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:955
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::HexagonBlockRanges::RangeList::add
void add(IndexType Start, IndexType End, bool Fixed, bool TiedEnd)
Definition: HexagonBlockRanges.h:110
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:484
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
MCRegisterInfo.h
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:264
MachineFunctionPass.h
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:567
HexagonRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::RegScavenger::addScavengingFrameIndex
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Definition: RegisterScavenging.h:143
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:644
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:532
MachineModuleInfo.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
MachinePostDominators.h
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
HexagonBlockRanges.h
R6
#define R6(n)
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:862
llvm::HexagonII::BaseImmOffset
@ BaseImmOffset
Definition: HexagonBaseInfo.h:34
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::SetVector::insert
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:787
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:239
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
None.h
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:1115
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:180
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:392
llvm::logicalview::LVAttributeKind::Range
@ Range
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:1000
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
llvm::HexagonBlockRanges::expandToSubRegs
static RegisterSet expandToSubRegs(RegisterRef R, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
Definition: HexagonBlockRanges.cpp:261
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
enableAllocFrameElim
static bool enableAllocFrameElim(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:578
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
Compiler.h
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
ShrinkLimit
static cl::opt< unsigned > ShrinkLimit("shrink-frame-limit", cl::init(std::numeric_limits< unsigned >::max()), cl::Hidden, cl::desc("Max count of stack frame shrink-wraps"))
OptimizeSpillSlots
static cl::opt< bool > OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden, cl::init(true), cl::desc("Optimize spill slots"))
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
SpillFuncThresholdOs
static cl::opt< int > SpillFuncThresholdOs("spill-func-threshold-Os", cl::Hidden, cl::desc("Specify Os spill func threshold"), cl::init(1))
NumberScavengerSlots
static cl::opt< unsigned > NumberScavengerSlots("number-scavenger-slots", cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2))
llvm::M68kBeads::Term
@ Term
Definition: M68kBaseInfo.h:71
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:313
llvm::MCContext::createTempSymbol
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:318
SK_FromMemTailcall
@ SK_FromMemTailcall
Definition: HexagonFrameLowering.cpp:1190
llvm::StackOffset::getFixed
static StackOffset getFixed(ScalarTy Fixed)
Definition: TypeSize.h:143
llvm::MachinePostDominatorTree
MachinePostDominatorTree - an analysis pass wrapper for DominatorTree used to compute the post-domina...
Definition: MachinePostDominators.h:27
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:601
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineFunction::addFrameInst
unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:310
getReturn
static MachineInstr * getReturn(MachineBasicBlock &MBB)
Returns the "return" instruction from this block, or nullptr if there isn't any.
Definition: HexagonFrameLowering.cpp:359
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:404
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1761
hasReturn
static bool hasReturn(const MachineBasicBlock &MBB)
Returns true if MBB contains an instruction that returns.
Definition: HexagonFrameLowering.cpp:350
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:613
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::MachinePostDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachinePostDominators.h:54
j
return j(j<< 16)
llvm::MachineFunction::getBlockNumbered
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
Definition: MachineFunction.h:789
llvm::HexagonFrameLowering::getCalleeSavedSpillSlots
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
Definition: HexagonFrameLowering.h:90
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::HexagonBlockRanges::RegToRangeMap
std::map< RegisterRef, RangeList > RegToRangeMap
Definition: HexagonBlockRanges.h:145
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
llvm::MachineFunction::needsFrameMoves
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
Definition: MachineFunction.cpp:613
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:653
llvm::HexagonFrameLowering::getAlignaInstr
const MachineInstr * getAlignaInstr(const MachineFunction &MF) const
Definition: HexagonFrameLowering.cpp:2557
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::AArch64CC::LS
@ LS
Definition: AArch64BaseInfo.h:264
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
Function.h
llvm::HexagonBlockRanges::InstrIndexMap
Definition: HexagonBlockRanges.h:125
llvm::HexagonFrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: HexagonFrameLowering.cpp:1494
x
TODO unsigned x
Definition: README.txt:10
llvm::HexagonBlockRanges::InstrIndexMap::getIndex
IndexType getIndex(MachineInstr *MI) const
Definition: HexagonBlockRanges.cpp:176
llvm::HexagonBlockRanges::IndexType
Definition: HexagonBlockRanges.h:47
isRestoreCall
static bool isRestoreCall(unsigned Opc)
Definition: HexagonFrameLowering.cpp:366
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:614
llvm::BitVector::find_next
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:301
llvm::SmallSet::insert
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:178
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::ReversePostOrderTraversal
Definition: PostOrderIterator.h:291
llvm::MachinePostDominatorTree::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: MachinePostDominators.cpp:40
CodeGen.h
llvm::MCSubRegIterator
MCSubRegIterator enumerates all sub-registers of Reg.
Definition: MCRegisterInfo.h:597
llvm::Function::isVarArg
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:188
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
PostOrderIterator.h
llvm::HexagonFrameLowering::determineCalleeSaves
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: HexagonFrameLowering.cpp:2079
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
MachineInstrBuilder.h
llvm::HexagonFrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Perform most of the PEI work here:
Definition: HexagonFrameLowering.cpp:510
llvm::Register::isValid
bool isValid() const
Definition: Register.h:126
N
#define N
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::BitVector::find_first
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:293
llvm::PseudoProbeAttributes::Reserved
@ Reserved
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:192
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
SpillKind
SpillKind
Definition: HexagonFrameLowering.cpp:1187
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:277
llvm::HexagonBlockRanges
Definition: HexagonBlockRanges.h:31
llvm::HexagonBlockRanges::InstrIndexMap::getInstr
MachineInstr * getInstr(IndexType Idx) const
Definition: HexagonBlockRanges.cpp:171
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
isOptNone
static bool isOptNone(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:381
HexagonMachineFunctionInfo.h
MachineOperand.h
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:642
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:570
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:130
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::TargetFrameLowering::determineCalleeSaves
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: TargetFrameLoweringImpl.cpp:83
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachinePostDominatorTree::findNearestCommonDominator
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B) const
Definition: MachinePostDominators.h:77
llvm::cl::desc
Definition: CommandLine.h:413
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
RegisterScavenging.h
raw_ostream.h
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:51
n
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Definition: README.txt:685
llvm::SetVector
A vector that has set insertion semantics.
Definition: SetVector.h:40
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
EnableSaveRestoreLong
static cl::opt< bool > EnableSaveRestoreLong("enable-save-restore-long", cl::Hidden, cl::desc("Enable long calls for save-restore stubs."), cl::init(false))
llvm::MachineInstrBundleIterator< const MachineInstr >
llvm::TargetFrameLowering::SpillSlot
Definition: TargetFrameLowering.h:51
SK_FromMem
@ SK_FromMem
Definition: HexagonFrameLowering.cpp:1189
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1032
TargetRegisterInfo.h
INITIALIZE_PASS
INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi", "Hexagon call frame information", false, false) FunctionPass *llvm
Definition: HexagonFrameLowering.cpp:241
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
llvm::SrcOp
Definition: MachineIRBuilder.h:128
SetVector.h
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
MachineDominators.h
llvm::HexagonFrameLowering::FirstVarArgSavedReg
int FirstVarArgSavedReg
Definition: HexagonFrameLowering.h:34
SmallSet.h
LivePhysRegs.h
llvm::HexagonFrameLowering::processFunctionBeforeFrameFinalized
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: HexagonFrameLowering.cpp:1505