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21 #define GET_INSTRINFO_CTOR_DTOR
22 #include "SPIRVGenInstrInfo.inc"
29 switch (
MI.getOpcode()) {
30 case SPIRV::OpConstantTrue:
31 case SPIRV::OpConstantFalse:
32 case SPIRV::OpConstantI:
33 case SPIRV::OpConstantF:
34 case SPIRV::OpConstantComposite:
35 case SPIRV::OpConstantSampler:
36 case SPIRV::OpConstantNull:
37 case SPIRV::OpSpecConstantTrue:
38 case SPIRV::OpSpecConstantFalse:
39 case SPIRV::OpSpecConstant:
40 case SPIRV::OpSpecConstantComposite:
41 case SPIRV::OpSpecConstantOp:
50 auto &
MRI =
MI.getMF()->getRegInfo();
51 if (
MI.getNumDefs() >= 1 &&
MI.getOperand(0).isReg()) {
53 return DefRegClass && DefRegClass->
getID() == SPIRV::TYPERegClass.getID();
55 return MI.getOpcode() == SPIRV::OpTypeForwardPointer;
60 switch (
MI.getOpcode()) {
61 case SPIRV::OpDecorate:
62 case SPIRV::OpDecorateId:
63 case SPIRV::OpDecorateString:
64 case SPIRV::OpMemberDecorate:
65 case SPIRV::OpMemberDecorateString:
73 switch (
MI.getOpcode()) {
74 case SPIRV::OpCapability:
75 case SPIRV::OpExtension:
76 case SPIRV::OpExtInstImport:
77 case SPIRV::OpMemoryModel:
78 case SPIRV::OpEntryPoint:
79 case SPIRV::OpExecutionMode:
80 case SPIRV::OpExecutionModeId:
82 case SPIRV::OpSourceExtension:
84 case SPIRV::OpSourceContinued:
86 case SPIRV::OpMemberName:
87 case SPIRV::OpModuleProcessed:
95 switch (
MI.getOpcode()) {
114 switch (
MI.getOpcode()) {
121 case SPIRV::OpShiftLeftLogicalS:
122 case SPIRV::OpShiftLeftLogicalV:
123 case SPIRV::OpSNegate:
131 switch (
MI.getOpcode()) {
175 bool AllowModify)
const {
183 if (
MI->getOpcode() == SPIRV::OpBranch) {
184 TBB =
MI->getOperand(0).getMBB();
186 }
else if (
MI->getOpcode() == SPIRV::OpBranchConditional) {
187 Cond.push_back(
MI->getOperand(0));
188 TBB =
MI->getOperand(1).getMBB();
189 if (
MI->getNumOperands() == 3) {
190 FBB =
MI->getOperand(2).getMBB();
204 int *BytesRemoved)
const {
206 " to OpPhi instructions. Try using -O0 instead.");
226 "propagated to OpPhi instructions. Try using "
238 assert(
I->isCopy() &&
"Copy instruction is expected");
239 auto DstOp =
I->getOperand(0);
240 auto SrcOp =
I->getOperand(1);
242 "Register operands are expected in COPY");
243 auto &
MRI =
I->getMF()->getRegInfo();
248 if (
MI.getOpcode() == SPIRV::GET_ID ||
MI.getOpcode() == SPIRV::GET_fID ||
249 MI.getOpcode() == SPIRV::GET_pID ||
MI.getOpcode() == SPIRV::GET_vfID ||
250 MI.getOpcode() == SPIRV::GET_vID) {
251 auto &
MRI =
MI.getMF()->getRegInfo();
253 MI.eraseFromParent();
unsigned getID() const
Return the register class ID number.
This is an optimization pass for GlobalISel generic memory operations.
bool isDecorationInstr(const MachineInstr &MI) const
bool canUseNUW(const MachineInstr &MI) const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool isConstantInstr(const MachineInstr &MI) const
bool isTypeDeclInstr(const MachineInstr &MI) const
bool canUseFastMathFlags(const MachineInstr &MI) const
bool isHeaderInstr(const MachineInstr &MI) const
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
bool canUseNSW(const MachineInstr &MI) const
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Representation of each machine instruction.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SmallVector< MachineOperand, 4 > Cond
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
unsigned const MachineRegisterInfo * MRI
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool expandPostRAPseudo(MachineInstr &MI) const override
Wrapper class representing physical registers. Should be passed by value.