LLVM 20.0.0git
WebAssemblyInstrInfo.cpp
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1//===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file contains the WebAssembly implementation of the
11/// TargetInstrInfo class.
12///
13//===----------------------------------------------------------------------===//
14
17#include "WebAssembly.h"
25using namespace llvm;
26
27#define DEBUG_TYPE "wasm-instr-info"
28
29#define GET_INSTRINFO_CTOR_DTOR
30#include "WebAssemblyGenInstrInfo.inc"
31
32// defines WebAssembly::getNamedOperandIdx
33#define GET_INSTRINFO_NAMED_OPS
34#include "WebAssemblyGenInstrInfo.inc"
35
37 : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
38 WebAssembly::ADJCALLSTACKUP,
39 WebAssembly::CATCHRET),
40 RI(STI.getTargetTriple()) {}
41
43 const MachineInstr &MI) const {
44 switch (MI.getOpcode()) {
45 case WebAssembly::CONST_I32:
46 case WebAssembly::CONST_I64:
47 case WebAssembly::CONST_F32:
48 case WebAssembly::CONST_F64:
49 // TargetInstrInfo::isReallyTriviallyReMaterializable misses these
50 // because of the ARGUMENTS implicit def, so we manualy override it here.
51 return true;
52 default:
54 }
55}
56
59 const DebugLoc &DL, MCRegister DestReg,
60 MCRegister SrcReg, bool KillSrc) const {
61 // This method is called by post-RA expansion, which expects only pregs to
62 // exist. However we need to handle both here.
63 auto &MRI = MBB.getParent()->getRegInfo();
64 const TargetRegisterClass *RC =
66 ? MRI.getRegClass(DestReg)
67 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
68
69 unsigned CopyOpcode = WebAssembly::getCopyOpcodeForRegClass(RC);
70
71 BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
72 .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
73}
74
76 MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
77 // If the operands are stackified, we can't reorder them.
79 *MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
80 if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
81 MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
82 return nullptr;
83
84 // Otherwise use the default implementation.
85 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
86}
87
88// Branch analysis.
93 bool /*AllowModify*/) const {
94 const auto &MFI = *MBB.getParent()->getInfo<WebAssemblyFunctionInfo>();
95 // WebAssembly has control flow that doesn't have explicit branches or direct
96 // fallthrough (e.g. try/catch), which can't be modeled by analyzeBranch. It
97 // is created after CFGStackify.
98 if (MFI.isCFGStackified())
99 return true;
100
101 bool HaveCond = false;
102 for (MachineInstr &MI : MBB.terminators()) {
103 switch (MI.getOpcode()) {
104 default:
105 // Unhandled instruction; bail out.
106 return true;
107 case WebAssembly::BR_IF:
108 if (HaveCond)
109 return true;
110 Cond.push_back(MachineOperand::CreateImm(true));
111 Cond.push_back(MI.getOperand(1));
112 TBB = MI.getOperand(0).getMBB();
113 HaveCond = true;
114 break;
115 case WebAssembly::BR_UNLESS:
116 if (HaveCond)
117 return true;
118 Cond.push_back(MachineOperand::CreateImm(false));
119 Cond.push_back(MI.getOperand(1));
120 TBB = MI.getOperand(0).getMBB();
121 HaveCond = true;
122 break;
123 case WebAssembly::BR:
124 if (!HaveCond)
125 TBB = MI.getOperand(0).getMBB();
126 else
127 FBB = MI.getOperand(0).getMBB();
128 break;
129 }
130 if (MI.isBarrier())
131 break;
132 }
133
134 return false;
135}
136
138 int *BytesRemoved) const {
139 assert(!BytesRemoved && "code size not handled");
140
142 unsigned Count = 0;
143
144 while (I != MBB.instr_begin()) {
145 --I;
146 if (I->isDebugInstr())
147 continue;
148 if (!I->isTerminator())
149 break;
150 // Remove the branch.
151 I->eraseFromParent();
152 I = MBB.instr_end();
153 ++Count;
154 }
155
156 return Count;
157}
158
161 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
162 assert(!BytesAdded && "code size not handled");
163
164 if (Cond.empty()) {
165 if (!TBB)
166 return 0;
167
168 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
169 return 1;
170 }
171
172 assert(Cond.size() == 2 && "Expected a flag and a successor block");
173
174 if (Cond[0].getImm())
175 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
176 else
177 BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
178 if (!FBB)
179 return 1;
180
181 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
182 return 2;
183}
184
187 assert(Cond.size() == 2 && "Expected a flag and a condition expression");
188 Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
189 return false;
190}
191
194 static const std::pair<int, const char *> TargetIndices[] = {
195 {WebAssembly::TI_LOCAL, "wasm-local"},
196 {WebAssembly::TI_GLOBAL_FIXED, "wasm-global-fixed"},
197 {WebAssembly::TI_OPERAND_STACK, "wasm-operand-stack"},
198 {WebAssembly::TI_GLOBAL_RELOC, "wasm-global-reloc"},
199 {WebAssembly::TI_LOCAL_INDIRECT, "wasm-local-indirect"}};
200 return ArrayRef(TargetIndices);
201}
202
203const MachineOperand &
206}
207
208// This returns true when the instruction defines a value of a TargetIndex
209// operand that can be tracked by offsets. For Wasm, this returns true for only
210// local.set/local.tees. This is currently used by LiveDebugValues analysis.
211//
212// These are not included:
213// - In theory we need to add global.set here too, but we don't have global
214// indices at this point because they are relocatable and we address them by
215// names until linking, so we don't have 'offsets' (which are used to store
216// local/global indices) to deal with in LiveDebugValues. And we don't
217// associate debug info in values in globals anyway.
218// - All other value-producing instructions, i.e. instructions with defs, can
219// define values in the Wasm stack, which is represented by TI_OPERAND_STACK
220// TargetIndex. But they don't have offset info within the instruction itself,
221// and debug info analysis for them is handled separately in
222// WebAssemblyDebugFixup pass, so we don't worry about them here.
224 int &Index,
225 int64_t &Offset) const {
226 unsigned Opc = MI.getOpcode();
229 Offset = MI.explicit_uses().begin()->getImm();
230 return true;
231 }
232 return false;
233}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains the WebAssembly implementation of the TargetInstrInfo class.
This file provides WebAssembly-specific target descriptions.
This file declares WebAssembly-specific per-machine-function information.
This file declares the WebAssembly-specific subclass of TargetSubtarget.
This file contains the declaration of the WebAssembly-specific utility functions.
This file contains the entry points for global functions defined in the LLVM WebAssembly back-end.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
instr_iterator instr_begin()
Instructions::iterator instr_iterator
instr_iterator instr_end()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< iterator > terminators()
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateImm(int64_t Val)
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
const MachineOperand & getCalleeOperand(const MachineInstr &MI) const override
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
bool isExplicitTargetIndexDef(const MachineInstr &MI, int &Index, int64_t &Offset) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
@ Kill
The last use of a register.
bool isLocalTee(unsigned Opc)
unsigned getCopyOpcodeForRegClass(const TargetRegisterClass *RC)
Returns the appropriate copy opcode for the given register class.
const MachineOperand & getCalleeOp(const MachineInstr &MI)
Returns the operand number of a callee, assuming the argument is a call instruction.
bool isLocalSet(unsigned Opc)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)