32#define DEBUG_TYPE "x86-suppress-apx-for-relocation"
35 "x86-enable-apx-for-relocation",
36 cl::desc(
"Enable APX features (EGPR, NDD and NF) for instructions with "
37 "relocations on x86-64 ELF"),
46 return "X86 Suppress APX features for relocation";
55char X86SuppressAPXForRelocationPass::ID = 0;
58 "X86 Suppress APX features for relocation",
false,
false)
63 return new X86SuppressAPXForRelocationPass();
69 if (!Reg.isVirtual()) {
76 MRI->setRegClass(Reg, NewRC);
93 if (
Use.getOpcode() == X86::PHI)
110 LLVM_DEBUG(
dbgs() <<
"Transform instruction with relocation type:\n "
112 for (
unsigned OpNo : OpNoArray)
120 unsigned Opcode =
MI.getOpcode();
127 case X86::TEST64mr: {
128 suppressEGPRInInstrWithReloc(
MI, {5});
135 suppressEGPRInInstrWithReloc(
MI, {0});
152 suppressEGPRInInstrWithReloc(
MI, {0, 1});
163 if (!ST.hasNDD() && !ST.hasNF())
170 unsigned Opcode =
MI.getOpcode();
172 case X86::ADD64rm_NF:
173 case X86::ADD64mr_NF_ND:
174 case X86::ADD64rm_NF_ND: {
182 case X86::ADD64rm_ND: {
188 LLVM_DEBUG(
dbgs() <<
"Transform instruction with relocation type:\n "
190 Register Reg =
MRI->createVirtualRegister(&X86::GR64_NOREX2RegClass);
195 MI.getOperand(1).setReg(Reg);
199 MI.tieOperands(0, 1);
205 case X86::ADD64mr_ND: {
209 LLVM_DEBUG(
dbgs() <<
"Transform instruction with relocation type:\n "
212 Register Reg =
MRI->createVirtualRegister(&X86::GR64_NOREX2RegClass);
219 MI.getOperand(0).getReg())
224 .
add(
MI.getOperand(4))
227 MI.findRegisterDefOperand(X86::EFLAGS,
nullptr);
228 if (FlagDef && FlagDef->
isDead()) {
234 MI.eraseFromParent();
246bool X86SuppressAPXForRelocationPass::runOnMachineFunction(
unsigned const MachineRegisterInfo * MRI
for(const MachineOperand &MO :llvm::drop_begin(OldMI.operands(), Desc.getNumOperands()))
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
const HexagonInstrInfo * TII
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
static bool handleInstructionWithEGPR(MachineFunction &MF, const X86Subtarget &ST)
cl::opt< bool > X86EnableAPXForRelocation("x86-enable-apx-for-relocation", cl::desc("Enable APX features (EGPR, NDD and NF) for instructions with " "relocations on x86-64 ELF"), cl::init(false))
static void suppressEGPRRegClass(MachineRegisterInfo *MRI, MachineInstr &MI, const X86Subtarget &ST, unsigned int OpNum)
static void suppressEGPRRegClassInRegAndUses(MachineRegisterInfo *MRI, MachineInstr &MI, const X86Subtarget &ST, unsigned int OpNum)
X86 Suppress APX features for relocation
static bool handleNDDOrNFInstructions(MachineFunction &MF, const X86Subtarget &ST)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
FunctionPass class - This class is used to implement most global optimizations.
Describe properties that are true of each instruction in the target description file.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
MachineOperand class - Representation of each machine instruction operand.
void setIsDead(bool Val=true)
unsigned getTargetFlags() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
A Use represents the edge between a Value definition and its users.
const TargetRegisterClass * constrainRegClassToNonRex2(const TargetRegisterClass *RC) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ MO_GOTTPOFF
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
int getMemoryOperandNo(uint64_t TSFlags)
bool isApxExtendedReg(MCRegister Reg)
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createX86SuppressAPXForRelocationPass()
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.