LLVM 19.0.0git
HexagonMCTargetDesc.cpp
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1//===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Hexagon specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
14#include "HexagonDepArch.h"
22#include "llvm/ADT/StringRef.h"
25#include "llvm/MC/MCAssembler.h"
27#include "llvm/MC/MCContext.h"
28#include "llvm/MC/MCDwarf.h"
31#include "llvm/MC/MCInstrInfo.h"
34#include "llvm/MC/MCStreamer.h"
40#include <cassert>
41#include <cstdint>
42#include <mutex>
43#include <new>
44#include <string>
45#include <unordered_map>
46
47using namespace llvm;
48
49#define GET_INSTRINFO_MC_DESC
50#define ENABLE_INSTR_PREDICATE_VERIFIER
51#include "HexagonGenInstrInfo.inc"
52
53#define GET_SUBTARGETINFO_MC_DESC
54#include "HexagonGenSubtargetInfo.inc"
55
56#define GET_REGINFO_MC_DESC
57#include "HexagonGenRegisterInfo.inc"
58
60 ("mno-compound",
61 cl::desc("Disable looking for compound instructions for Hexagon"));
62
64 ("mno-pairing",
65 cl::desc("Disable looking for duplex instructions for Hexagon"));
66
67namespace { // These flags are to be deprecated
68cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
69 cl::init(false));
70cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
71 cl::init(false));
72cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
73 cl::init(false));
74cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
75 cl::init(false));
76cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
77 cl::init(false));
78cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
79 cl::init(false));
80cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"),
81 cl::init(false));
82cl::opt<bool> MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"),
83 cl::init(false));
84cl::opt<bool> MV68("mv68", cl::Hidden, cl::desc("Build for Hexagon V68"),
85 cl::init(false));
86cl::opt<bool> MV69("mv69", cl::Hidden, cl::desc("Build for Hexagon V69"),
87 cl::init(false));
88cl::opt<bool> MV71("mv71", cl::Hidden, cl::desc("Build for Hexagon V71"),
89 cl::init(false));
90cl::opt<bool> MV71T("mv71t", cl::Hidden, cl::desc("Build for Hexagon V71T"),
91 cl::init(false));
92cl::opt<bool> MV73("mv73", cl::Hidden, cl::desc("Build for Hexagon V73"),
93 cl::init(false));
94} // namespace
95
97 "mhvx", cl::desc("Enable Hexagon Vector eXtensions"),
98 cl::values(clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
99 clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
100 clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
101 clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
102 clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"),
103 clEnumValN(Hexagon::ArchEnum::V68, "v68", "Build for HVX v68"),
104 clEnumValN(Hexagon::ArchEnum::V69, "v69", "Build for HVX v69"),
105 clEnumValN(Hexagon::ArchEnum::V71, "v71", "Build for HVX v71"),
106 clEnumValN(Hexagon::ArchEnum::V73, "v73", "Build for HVX v73"),
107 // Sentinel for no value specified.
108 clEnumValN(Hexagon::ArchEnum::Generic, "", "")),
109 // Sentinel for flag not present.
110 cl::init(Hexagon::ArchEnum::NoArch), cl::ValueOptional);
111
112static cl::opt<bool>
114 cl::desc("Disable Hexagon Vector eXtensions"));
115
116static cl::opt<bool>
118 cl::desc("Enable HVX IEEE floating point extensions"));
120 ("mcabac", cl::desc("tbd"), cl::init(false));
121
122static StringRef DefaultArch = "hexagonv60";
123
125 if (MV5)
126 return "hexagonv5";
127 if (MV55)
128 return "hexagonv55";
129 if (MV60)
130 return "hexagonv60";
131 if (MV62)
132 return "hexagonv62";
133 if (MV65)
134 return "hexagonv65";
135 if (MV66)
136 return "hexagonv66";
137 if (MV67)
138 return "hexagonv67";
139 if (MV67T)
140 return "hexagonv67t";
141 if (MV68)
142 return "hexagonv68";
143 if (MV69)
144 return "hexagonv69";
145 if (MV71)
146 return "hexagonv71";
147 if (MV71T)
148 return "hexagonv71t";
149 if (MV73)
150 return "hexagonv73";
151 return "";
152}
153
156 if (!ArchV.empty() && !CPU.empty()) {
157 // Tiny cores have a "t" suffix that is discarded when creating a secondary
158 // non-tiny subtarget. See: addArchSubtarget
159 std::pair<StringRef, StringRef> ArchP = ArchV.split('t');
160 std::pair<StringRef, StringRef> CPUP = CPU.split('t');
161 if (ArchP.first != CPUP.first)
162 report_fatal_error("conflicting architectures specified.");
163 return CPU;
164 }
165 if (ArchV.empty()) {
166 if (CPU.empty())
167 CPU = DefaultArch;
168 return CPU;
169 }
170 return ArchV;
171}
172
173unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; }
174
175unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) {
176 enum {
177 CVI_NONE = 0,
178 CVI_XLANE = 1 << 0,
179 CVI_SHIFT = 1 << 1,
180 CVI_MPY0 = 1 << 2,
181 CVI_MPY1 = 1 << 3,
182 CVI_ZW = 1 << 4
183 };
184
185 if (ItinUnits == HexagonItinerariesV62FU::CVI_ALL ||
186 ItinUnits == HexagonItinerariesV62FU::CVI_ALL_NOMEM)
187 return (*Lanes = 4, CVI_XLANE);
188 else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01 &&
189 ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
190 return (*Lanes = 2, CVI_XLANE | CVI_MPY0);
191 else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01)
192 return (*Lanes = 2, CVI_MPY0);
193 else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
194 return (*Lanes = 2, CVI_XLANE);
195 else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
196 ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT &&
197 ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
198 ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
199 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1);
200 else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
201 ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT)
202 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT);
203 else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
204 ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
205 return (*Lanes = 1, CVI_MPY0 | CVI_MPY1);
206 else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW)
207 return (*Lanes = 1, CVI_ZW);
208 else if (ItinUnits == HexagonItinerariesV62FU::CVI_XLANE)
209 return (*Lanes = 1, CVI_XLANE);
210 else if (ItinUnits == HexagonItinerariesV62FU::CVI_SHIFT)
211 return (*Lanes = 1, CVI_SHIFT);
212
213 return (*Lanes = 0, CVI_NONE);
214}
215
216
217namespace llvm {
218namespace HexagonFUnits {
219bool isSlot0Only(unsigned units) {
220 return HexagonItinerariesV62FU::SLOT0 == units;
221}
222} // namespace HexagonFUnits
223} // namespace llvm
224
225namespace {
226
227class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
229 bool IsVerboseAsm;
230
231public:
232 HexagonTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS,
233 bool IsVerboseAsm, MCInstPrinter &IP)
234 : HexagonTargetStreamer(S), OS(OS), IsVerboseAsm(IsVerboseAsm) {}
235
236 void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address,
237 const MCInst &Inst, const MCSubtargetInfo &STI,
238 raw_ostream &OS) override {
241 std::string Buffer;
242 {
243 raw_string_ostream TempStream(Buffer);
244 InstPrinter.printInst(&Inst, Address, "", STI, TempStream);
245 }
246 StringRef Contents(Buffer);
247 auto PacketBundle = Contents.rsplit('\n');
248 auto HeadTail = PacketBundle.first.split('\n');
249 StringRef Separator = "\n";
250 StringRef Indent = "\t";
251 OS << "\t{\n";
252 while (!HeadTail.first.empty()) {
253 StringRef InstTxt;
254 auto Duplex = HeadTail.first.split('\v');
255 if (!Duplex.second.empty()) {
256 OS << Indent << Duplex.first << Separator;
257 InstTxt = Duplex.second;
258 } else if (!HeadTail.first.trim().starts_with("immext")) {
259 InstTxt = Duplex.first;
260 }
261 if (!InstTxt.empty())
262 OS << Indent << InstTxt << Separator;
263 HeadTail = HeadTail.second.split('\n');
264 }
265
267 OS << "\n\t} :mem_noshuf" << PacketBundle.second;
268 else
269 OS << "\t}" << PacketBundle.second;
270 }
271
272 void finish() override { finishAttributeSection(); }
273
274 void finishAttributeSection() override {}
275
276 void emitAttribute(unsigned Attribute, unsigned Value) override {
277 OS << "\t.attribute\t" << Attribute << ", " << Twine(Value);
278 if (IsVerboseAsm) {
281 if (!Name.empty())
282 OS << "\t// " << Name;
283 }
284 OS << "\n";
285 }
286};
287
288class HexagonTargetELFStreamer : public HexagonTargetStreamer {
289public:
291 return static_cast<MCELFStreamer &>(Streamer);
292 }
293 HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
295 MCAssembler &MCA = getStreamer().getAssembler();
297 }
298
300 unsigned ByteAlignment,
301 unsigned AccessSize) override {
302 HexagonMCELFStreamer &HexagonELFStreamer =
303 static_cast<HexagonMCELFStreamer &>(getStreamer());
304 HexagonELFStreamer.HexagonMCEmitCommonSymbol(
305 Symbol, Size, Align(ByteAlignment), AccessSize);
306 }
307
309 unsigned ByteAlignment,
310 unsigned AccessSize) override {
311 HexagonMCELFStreamer &HexagonELFStreamer =
312 static_cast<HexagonMCELFStreamer &>(getStreamer());
313 HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
314 Symbol, Size, Align(ByteAlignment), AccessSize);
315 }
316
317 void finish() override { finishAttributeSection(); }
318
319 void reset() override { AttributeSection = nullptr; }
320
321private:
322 MCSection *AttributeSection = nullptr;
323
324 void finishAttributeSection() override {
326 if (S.Contents.empty())
327 return;
328
329 S.emitAttributesSection("hexagon", ".hexagon.attributes",
330 ELF::SHT_HEXAGON_ATTRIBUTES, AttributeSection);
331 }
332
334 getStreamer().setAttributeItem(Attribute, Value,
335 /*OverwriteExisting=*/true);
336 }
337};
338
339} // end anonymous namespace
340
342 MCInstrInfo *X = new MCInstrInfo();
343 InitHexagonMCInstrInfo(X);
344 return X;
345}
346
349 InitHexagonMCRegisterInfo(X, Hexagon::R31, /*DwarfFlavour=*/0,
350 /*EHFlavour=*/0, /*PC=*/Hexagon::PC);
351 return X;
352}
353
355 const Triple &TT,
356 const MCTargetOptions &Options) {
357 MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
358
359 // VirtualFP = (R30 + #0).
361 nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0);
362 MAI->addInitialFrameState(Inst);
363
364 return MAI;
365}
366
368 unsigned SyntaxVariant,
369 const MCAsmInfo &MAI,
370 const MCInstrInfo &MII,
371 const MCRegisterInfo &MRI)
372{
373 if (SyntaxVariant == 0)
374 return new HexagonInstPrinter(MAI, MII, MRI);
375 else
376 return nullptr;
377}
378
379static MCTargetStreamer *
381 MCInstPrinter *IP, bool IsVerboseAsm) {
382 return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
383}
384
386 std::unique_ptr<MCAsmBackend> &&MAB,
387 std::unique_ptr<MCObjectWriter> &&OW,
388 std::unique_ptr<MCCodeEmitter> &&Emitter) {
389 return createHexagonELFStreamer(T, Context, std::move(MAB), std::move(OW),
390 std::move(Emitter));
391}
392
393static MCTargetStreamer *
395 return new HexagonTargetELFStreamer(S, STI);
396}
397
399 return new HexagonTargetStreamer(S);
400}
401
403 if (STI->hasFeature(F))
404 STI->ToggleFeature(F);
405}
406
408 return STI->hasFeature(F);
409}
410
411namespace {
412std::string selectHexagonFS(StringRef CPU, StringRef FS) {
414 if (!FS.empty())
415 Result.push_back(FS);
416
417 switch (EnableHVX) {
418 case Hexagon::ArchEnum::V5:
419 case Hexagon::ArchEnum::V55:
420 break;
421 case Hexagon::ArchEnum::V60:
422 Result.push_back("+hvxv60");
423 break;
424 case Hexagon::ArchEnum::V62:
425 Result.push_back("+hvxv62");
426 break;
427 case Hexagon::ArchEnum::V65:
428 Result.push_back("+hvxv65");
429 break;
430 case Hexagon::ArchEnum::V66:
431 Result.push_back("+hvxv66");
432 break;
433 case Hexagon::ArchEnum::V67:
434 Result.push_back("+hvxv67");
435 break;
436 case Hexagon::ArchEnum::V68:
437 Result.push_back("+hvxv68");
438 break;
439 case Hexagon::ArchEnum::V69:
440 Result.push_back("+hvxv69");
441 break;
442 case Hexagon::ArchEnum::V71:
443 Result.push_back("+hvxv71");
444 break;
445 case Hexagon::ArchEnum::V73:
446 Result.push_back("+hvxv73");
447 break;
448 case Hexagon::ArchEnum::Generic:{
449 Result.push_back(StringSwitch<StringRef>(CPU)
450 .Case("hexagonv60", "+hvxv60")
451 .Case("hexagonv62", "+hvxv62")
452 .Case("hexagonv65", "+hvxv65")
453 .Case("hexagonv66", "+hvxv66")
454 .Case("hexagonv67", "+hvxv67")
455 .Case("hexagonv67t", "+hvxv67")
456 .Case("hexagonv68", "+hvxv68")
457 .Case("hexagonv69", "+hvxv69")
458 .Case("hexagonv71", "+hvxv71")
459 .Case("hexagonv71t", "+hvxv71")
460 .Case("hexagonv73", "+hvxv73"));
461 break;
462 }
463 case Hexagon::ArchEnum::NoArch:
464 // Sentinel if -mhvx isn't specified
465 break;
466 }
467 if (EnableHvxIeeeFp)
468 Result.push_back("+hvx-ieee-fp");
470 Result.push_back("+cabac");
471
472 return join(Result.begin(), Result.end(), ",");
473}
474}
475
476static bool isCPUValid(StringRef CPU) {
477 return Hexagon::getCpu(CPU).has_value();
478}
479
480namespace {
481std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
482 StringRef FS) {
483 std::pair<std::string, std::string> Result;
484 Result.first = std::string(Hexagon_MC::selectHexagonCPU(CPU));
485 Result.second = selectHexagonFS(Result.first, FS);
486 return Result;
487}
488std::mutex ArchSubtargetMutex;
489std::unordered_map<std::string, std::unique_ptr<MCSubtargetInfo const>>
490 ArchSubtarget;
491} // namespace
492
493MCSubtargetInfo const *
495 std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
496 auto Existing = ArchSubtarget.find(std::string(STI->getCPU()));
497 if (Existing == ArchSubtarget.end())
498 return nullptr;
499 return Existing->second.get();
500}
501
503 using namespace Hexagon;
504 // Make sure that +hvx-length turns hvx on, and that "hvx" alone
505 // turns on hvxvNN, corresponding to the existing ArchVNN.
506 FeatureBitset FB = S;
507 unsigned CpuArch = ArchV5;
508 for (unsigned F : {ArchV73, ArchV71, ArchV69, ArchV68, ArchV67, ArchV66,
509 ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) {
510 if (!FB.test(F))
511 continue;
512 CpuArch = F;
513 break;
514 }
515 bool UseHvx = false;
516 for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
517 if (!FB.test(F))
518 continue;
519 UseHvx = true;
520 break;
521 }
522 bool HasHvxVer = false;
523 for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
524 ExtensionHVXV66, ExtensionHVXV67, ExtensionHVXV68,
525 ExtensionHVXV69, ExtensionHVXV71, ExtensionHVXV73}) {
526 if (!FB.test(F))
527 continue;
528 HasHvxVer = true;
529 UseHvx = true;
530 break;
531 }
532
533 if (!UseHvx || HasHvxVer)
534 return FB;
535
536 // HasHvxVer is false, and UseHvx is true.
537 switch (CpuArch) {
538 case ArchV73:
539 FB.set(ExtensionHVXV73);
540 [[fallthrough]];
541 case ArchV71:
542 FB.set(ExtensionHVXV71);
543 [[fallthrough]];
544 case ArchV69:
545 FB.set(ExtensionHVXV69);
546 [[fallthrough]];
547 case ArchV68:
548 FB.set(ExtensionHVXV68);
549 [[fallthrough]];
550 case ArchV67:
551 FB.set(ExtensionHVXV67);
552 [[fallthrough]];
553 case ArchV66:
554 FB.set(ExtensionHVXV66);
555 [[fallthrough]];
556 case ArchV65:
557 FB.set(ExtensionHVXV65);
558 [[fallthrough]];
559 case ArchV62:
560 FB.set(ExtensionHVXV62);
561 [[fallthrough]];
562 case ArchV60:
563 FB.set(ExtensionHVXV60);
564 break;
565 }
566 return FB;
567}
568
570 StringRef CPU,
571 StringRef FS) {
572 std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
573 StringRef CPUName = Features.first;
574 StringRef ArchFS = Features.second;
575
576 MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(
577 TT, CPUName, /*TuneCPU*/ CPUName, ArchFS);
578 if (X != nullptr && (CPUName == "hexagonv67t" || CPUName == "hexagon71t"))
579 addArchSubtarget(X, ArchFS);
580
581 if (CPU == "help")
582 exit(0);
583
584 if (!isCPUValid(CPUName.str())) {
585 errs() << "error: invalid CPU \"" << CPUName.str().c_str()
586 << "\" specified\n";
587 return nullptr;
588 }
589
590 // Add qfloat subtarget feature by default to v68 and above
591 // unless explicitely disabled
592 if (checkFeature(X, Hexagon::ExtensionHVXV68) &&
593 !ArchFS.contains("-hvx-qfloat")) {
594 llvm::FeatureBitset Features = X->getFeatureBits();
595 X->setFeatureBits(Features.set(Hexagon::ExtensionHVXQFloat));
596 }
597
599 llvm::FeatureBitset Features = X->getFeatureBits();
600 X->setFeatureBits(Features.reset(Hexagon::FeatureDuplex));
601 }
602
603 X->setFeatureBits(completeHVXFeatures(X->getFeatureBits()));
604
605 // The Z-buffer instructions are grandfathered in for current
606 // architectures but omitted for new ones. Future instruction
607 // sets may introduce new/conflicting z-buffer instructions.
608 const bool ZRegOnDefault =
609 (CPUName == "hexagonv67") || (CPUName == "hexagonv66");
610 if (ZRegOnDefault) {
611 llvm::FeatureBitset Features = X->getFeatureBits();
612 X->setFeatureBits(Features.set(Hexagon::ExtensionZReg));
613 }
614
615 return X;
616}
617
619 assert(STI != nullptr);
620 if (STI->getCPU().contains("t")) {
621 auto ArchSTI = createHexagonMCSubtargetInfo(
622 STI->getTargetTriple(),
623 STI->getCPU().substr(0, STI->getCPU().size() - 1), FS);
624 std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
625 ArchSubtarget[std::string(STI->getCPU())] =
626 std::unique_ptr<MCSubtargetInfo const>(ArchSTI);
627 }
628}
629
630std::optional<unsigned>
632 for (auto Arch : {Hexagon::ExtensionHVXV73, Hexagon::ExtensionHVXV71,
633 Hexagon::ExtensionHVXV69, Hexagon::ExtensionHVXV68,
634 Hexagon::ExtensionHVXV67, Hexagon::ExtensionHVXV66,
635 Hexagon::ExtensionHVXV65, Hexagon::ExtensionHVXV62,
636 Hexagon::ExtensionHVXV60})
637 if (Features.test(Arch))
638 return Arch;
639 return {};
640}
641
642unsigned Hexagon_MC::getArchVersion(const FeatureBitset &Features) {
643 for (auto Arch :
644 {Hexagon::ArchV73, Hexagon::ArchV71, Hexagon::ArchV69, Hexagon::ArchV68,
645 Hexagon::ArchV67, Hexagon::ArchV66, Hexagon::ArchV65, Hexagon::ArchV62,
646 Hexagon::ArchV60, Hexagon::ArchV55, Hexagon::ArchV5})
647 if (Features.test(Arch))
648 return Arch;
649 llvm_unreachable("Expected arch v5-v73");
650 return 0;
651}
652
654 return StringSwitch<unsigned>(STI.getCPU())
668 .Case("hexagonv73", llvm::ELF::EF_HEXAGON_MACH_V73);
669}
670
672 return ArrayRef(VectRegRev);
673}
674
675namespace {
676class HexagonMCInstrAnalysis : public MCInstrAnalysis {
677public:
678 HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
679
680 bool isUnconditionalBranch(MCInst const &Inst) const override {
681 //assert(!HexagonMCInstrInfo::isBundle(Inst));
683 }
684
685 bool isConditionalBranch(MCInst const &Inst) const override {
686 //assert(!HexagonMCInstrInfo::isBundle(Inst));
688 }
689
690 bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
691 uint64_t Size, uint64_t &Target) const override {
692 if (!(isCall(Inst) || isUnconditionalBranch(Inst) ||
693 isConditionalBranch(Inst)))
694 return false;
695
696 //assert(!HexagonMCInstrInfo::isBundle(Inst));
697 if (!HexagonMCInstrInfo::isExtendable(*Info, Inst))
698 return false;
699 auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(*Info, Inst));
700 assert(Extended.isExpr());
701 int64_t Value;
702 if (!Extended.getExpr()->evaluateAsAbsolute(Value))
703 return false;
704 Target = Value;
705 return true;
706 }
707};
708}
709
711 return new HexagonMCInstrAnalysis(Info);
712}
713
714// Force static initialization.
716 // Register the MC asm info.
718
719 // Register the MC instruction info.
722
723 // Register the MC register info.
726
727 // Register the MC subtarget info.
730
731 // Register the MC Code Emitter
734
735 // Register the asm backend
738
739 // Register the MC instruction analyzer.
742
743 // Register the obj streamer
745
746 // Register the obj target streamer
749
750 // Register the asm streamer
753
754 // Register the null streamer
757
758 // Register the MC Inst Printer
761}
unsigned const MachineRegisterInfo * MRI
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dxil DXContainer Global Emitter
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static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableHexagonCabac("mcabac", cl::desc("tbd"), cl::init(false))
static MCTargetStreamer * createHexagonNullTargetStreamer(MCStreamer &S)
static MCTargetStreamer * createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
cl::opt< Hexagon::ArchEnum > EnableHVX("mhvx", cl::desc("Enable Hexagon Vector eXtensions"), cl::values(clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"), clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"), clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"), clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"), clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"), clEnumValN(Hexagon::ArchEnum::V68, "v68", "Build for HVX v68"), clEnumValN(Hexagon::ArchEnum::V69, "v69", "Build for HVX v69"), clEnumValN(Hexagon::ArchEnum::V71, "v71", "Build for HVX v71"), clEnumValN(Hexagon::ArchEnum::V73, "v73", "Build for HVX v73"), clEnumValN(Hexagon::ArchEnum::Generic, "", "")), cl::init(Hexagon::ArchEnum::NoArch), cl::ValueOptional)
static MCInstrAnalysis * createHexagonMCInstrAnalysis(const MCInstrInfo *Info)
static MCInstPrinter * createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo *STI, uint64_t F)
static MCTargetStreamer * createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *IP, bool IsVerboseAsm)
static cl::opt< bool > DisableHVX("mno-hvx", cl::Hidden, cl::desc("Disable Hexagon Vector eXtensions"))
static MCStreamer * createMCStreamer(Triple const &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter)
static bool isCPUValid(StringRef CPU)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTargetMC()
static MCRegisterInfo * createHexagonMCRegisterInfo(const Triple &TT)
static StringRef DefaultArch
static cl::opt< bool > EnableHvxIeeeFp("mhvx-ieee-fp", cl::Hidden, cl::desc("Enable HVX IEEE floating point extensions"))
static MCAsmInfo * createHexagonMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
static StringRef HexagonGetArchVariant()
static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo *STI, uint64_t F)
#define HEXAGON_PACKET_SIZE
static LVOptions Options
Definition: LVOptions.cpp:25
#define F(x, y, z)
Definition: MD5.cpp:55
LLVMContext & Context
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file contains some functions that are useful when dealing with strings.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Container class for subtarget features.
constexpr FeatureBitset & reset(unsigned I)
constexpr bool test(unsigned I) const
FeatureBitset & set()
Prints bundles as a newline separated list of individual instructions Duplexes are separated by a ver...
void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, Align ByteAlignment, unsigned AccessSize)
void HexagonMCEmitCommonSymbol(MCSymbol *Symbol, uint64_t Size, Align ByteAlignment, unsigned AccessSize)
virtual void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessGranularity)
virtual void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlign, unsigned AccessGranularity)
virtual void emitAttribute(unsigned Attribute, unsigned Value)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:75
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:282
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:541
Context object for machine code objects.
Definition: MCContext.h:81
SmallVector< AttributeItem, 64 > Contents
void emitAttributesSection(StringRef Vendor, const Twine &Section, unsigned Type, MCSection *&AttributeSection)
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:45
virtual void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS)=0
Print the specified MCInst to the specified raw_ostream.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
virtual bool isCall(const MCInst &Inst) const
virtual bool isUnconditionalBranch(const MCInst &Inst) const
virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const
Given a branch instruction try to get the address the branch targets.
virtual bool isConditionalBranch(const MCInst &Inst) const
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Instances of this class represent a uniqued identifier for a section in the current translation unit.
Definition: MCSection.h:39
Streaming machine code generation interface.
Definition: MCStreamer.h:212
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
StringRef getCPU() const
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
Target specific streamer interface.
Definition: MCStreamer.h:93
virtual void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address, const MCInst &Inst, const MCSubtargetInfo &STI, raw_ostream &OS)
MCStreamer & getStreamer()
Definition: MCStreamer.h:101
MCStreamer & Streamer
Definition: MCStreamer.h:95
bool empty() const
Definition: SmallVector.h:94
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:693
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:223
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:564
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
bool contains(StringRef Other) const
Return true if the given string is a substring of *this, and false otherwise.
Definition: StringRef.h:417
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
LLVM Value Representation.
Definition: Value.h:74
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:660
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
StringRef attrTypeAsString(unsigned attr, TagNameMap tagNameMap, bool hasTagPrefix=true)
@ EF_HEXAGON_MACH_V5
Definition: ELF.h:616
@ EF_HEXAGON_MACH_V71T
Definition: ELF.h:627
@ EF_HEXAGON_MACH_V67T
Definition: ELF.h:623
@ EF_HEXAGON_MACH_V65
Definition: ELF.h:620
@ EF_HEXAGON_MACH_V67
Definition: ELF.h:622
@ EF_HEXAGON_MACH_V62
Definition: ELF.h:619
@ EF_HEXAGON_MACH_V73
Definition: ELF.h:628
@ EF_HEXAGON_MACH_V71
Definition: ELF.h:626
@ EF_HEXAGON_MACH_V68
Definition: ELF.h:624
@ EF_HEXAGON_MACH_V66
Definition: ELF.h:621
@ EF_HEXAGON_MACH_V55
Definition: ELF.h:617
@ EF_HEXAGON_MACH_V60
Definition: ELF.h:618
@ EF_HEXAGON_MACH_V69
Definition: ELF.h:625
@ SHT_HEXAGON_ATTRIBUTES
Definition: ELF.h:1146
const TagNameMap & getHexagonAttributeTags()
bool isSlot0Only(unsigned units)
size_t bundleSize(MCInst const &MCI)
bool isMemReorderDisabled(MCInst const &MCI)
bool isBundle(MCInst const &MCI)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
llvm::ArrayRef< MCPhysReg > GetVectRegRev()
unsigned getArchVersion(const FeatureBitset &Features)
unsigned GetELFFlags(const MCSubtargetInfo &STI)
std::optional< unsigned > getHVXVersion(const FeatureBitset &Features)
MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)
StringRef selectHexagonCPU(StringRef CPU)
void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a Hexagon MCSubtargetInfo instance.
std::optional< Hexagon::ArchEnum > getCpu(StringRef CPU)
@ FS
Definition: X86.h:206
@ ValueOptional
Definition: CommandLine.h:131
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:718
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes)
cl::opt< bool > HexagonDisableCompound
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, MCContext &MCT)
unsigned HexagonGetLastSlot()
Target & getTheHexagonTarget()
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:159
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MCInstrInfo * createHexagonMCInstrInfo()
MCStreamer * createHexagonELFStreamer(Triple const &TT, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > CE)
cl::opt< bool > HexagonDisableDuplex
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)