LLVM  14.0.0git
HexagonMCTargetDesc.cpp
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1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Hexagon specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "HexagonArch.h"
15 #include "HexagonTargetStreamer.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/BinaryFormat/ELF.h"
24 #include "llvm/MC/MCAsmBackend.h"
25 #include "llvm/MC/MCCodeEmitter.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCDwarf.h"
28 #include "llvm/MC/MCELFStreamer.h"
30 #include "llvm/MC/MCInstrInfo.h"
31 #include "llvm/MC/MCObjectWriter.h"
32 #include "llvm/MC/MCRegisterInfo.h"
33 #include "llvm/MC/MCStreamer.h"
35 #include "llvm/MC/TargetRegistry.h"
38 #include <cassert>
39 #include <cstdint>
40 #include <mutex>
41 #include <new>
42 #include <string>
43 #include <unordered_map>
44 
45 using namespace llvm;
46 
47 #define GET_INSTRINFO_MC_DESC
48 #include "HexagonGenInstrInfo.inc"
49 
50 #define GET_SUBTARGETINFO_MC_DESC
51 #include "HexagonGenSubtargetInfo.inc"
52 
53 #define GET_REGINFO_MC_DESC
54 #include "HexagonGenRegisterInfo.inc"
55 
57  ("mno-compound",
58  cl::desc("Disable looking for compound instructions for Hexagon"));
59 
61  ("mno-pairing",
62  cl::desc("Disable looking for duplex instructions for Hexagon"));
63 
64 namespace { // These flags are to be deprecated
65 cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
66  cl::init(false));
67 cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
68  cl::init(false));
69 cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
70  cl::init(false));
71 cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
72  cl::init(false));
73 cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
74  cl::init(false));
75 cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
76  cl::init(false));
77 cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"),
78  cl::init(false));
79 cl::opt<bool> MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"),
80  cl::init(false));
81 cl::opt<bool> MV68("mv68", cl::Hidden, cl::desc("Build for Hexagon V68"),
82  cl::init(false));
83 cl::opt<bool> MV69("mv69", cl::Hidden, cl::desc("Build for Hexagon V69"),
84  cl::init(false));
85 
87  EnableHVX("mhvx",
88  cl::desc("Enable Hexagon Vector eXtensions"),
89  cl::values(
90  clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
91  clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
92  clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
93  clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
94  clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"),
95  clEnumValN(Hexagon::ArchEnum::V68, "v68", "Build for HVX v68"),
96  clEnumValN(Hexagon::ArchEnum::V69, "v69", "Build for HVX v69"),
97  // Sentinel for no value specified.
99  // Sentinel for flag not present.
101 } // namespace
102 
103 static cl::opt<bool>
104  DisableHVX("mno-hvx", cl::Hidden,
105  cl::desc("Disable Hexagon Vector eXtensions"));
106 
107 static cl::opt<bool>
108  EnableHvxIeeeFp("mhvx-ieee-fp", cl::Hidden,
109  cl::desc("Enable HVX IEEE floating point extensions"));
111  ("mcabac", cl::desc("tbd"), cl::init(false));
112 
113 static StringRef DefaultArch = "hexagonv60";
114 
116  if (MV5)
117  return "hexagonv5";
118  if (MV55)
119  return "hexagonv55";
120  if (MV60)
121  return "hexagonv60";
122  if (MV62)
123  return "hexagonv62";
124  if (MV65)
125  return "hexagonv65";
126  if (MV66)
127  return "hexagonv66";
128  if (MV67)
129  return "hexagonv67";
130  if (MV67T)
131  return "hexagonv67t";
132  if (MV68)
133  return "hexagonv68";
134  if (MV69)
135  return "hexagonv69";
136  return "";
137 }
138 
141  if (!ArchV.empty() && !CPU.empty()) {
142  // Tiny cores have a "t" suffix that is discarded when creating a secondary
143  // non-tiny subtarget. See: addArchSubtarget
144  std::pair<StringRef,StringRef> ArchP = ArchV.split('t');
145  std::pair<StringRef,StringRef> CPUP = CPU.split('t');
146  if (!ArchP.first.equals(CPUP.first))
147  report_fatal_error("conflicting architectures specified.");
148  return CPU;
149  }
150  if (ArchV.empty()) {
151  if (CPU.empty())
152  CPU = DefaultArch;
153  return CPU;
154  }
155  return ArchV;
156 }
157 
158 unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; }
159 
160 unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) {
161  enum {
162  CVI_NONE = 0,
163  CVI_XLANE = 1 << 0,
164  CVI_SHIFT = 1 << 1,
165  CVI_MPY0 = 1 << 2,
166  CVI_MPY1 = 1 << 3,
167  CVI_ZW = 1 << 4
168  };
169 
170  if (ItinUnits == HexagonItinerariesV62FU::CVI_ALL ||
171  ItinUnits == HexagonItinerariesV62FU::CVI_ALL_NOMEM)
172  return (*Lanes = 4, CVI_XLANE);
173  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01 &&
174  ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
175  return (*Lanes = 2, CVI_XLANE | CVI_MPY0);
176  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01)
177  return (*Lanes = 2, CVI_MPY0);
178  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
179  return (*Lanes = 2, CVI_XLANE);
180  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
181  ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT &&
182  ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
183  ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
184  return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1);
185  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
186  ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT)
187  return (*Lanes = 1, CVI_XLANE | CVI_SHIFT);
188  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
189  ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
190  return (*Lanes = 1, CVI_MPY0 | CVI_MPY1);
191  else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW)
192  return (*Lanes = 1, CVI_ZW);
193  else if (ItinUnits == HexagonItinerariesV62FU::CVI_XLANE)
194  return (*Lanes = 1, CVI_XLANE);
195  else if (ItinUnits == HexagonItinerariesV62FU::CVI_SHIFT)
196  return (*Lanes = 1, CVI_SHIFT);
197 
198  return (*Lanes = 0, CVI_NONE);
199 }
200 
201 
202 namespace llvm {
203 namespace HexagonFUnits {
204 bool isSlot0Only(unsigned units) {
205  return HexagonItinerariesV62FU::SLOT0 == units;
206 }
207 } // namespace HexagonFUnits
208 } // namespace llvm
209 
210 namespace {
211 
212 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
213 public:
214  HexagonTargetAsmStreamer(MCStreamer &S,
216  bool isVerboseAsm,
217  MCInstPrinter &IP)
219 
220  void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address,
221  const MCInst &Inst, const MCSubtargetInfo &STI,
222  raw_ostream &OS) override {
225  std::string Buffer;
226  {
227  raw_string_ostream TempStream(Buffer);
228  InstPrinter.printInst(&Inst, Address, "", STI, TempStream);
229  }
230  StringRef Contents(Buffer);
231  auto PacketBundle = Contents.rsplit('\n');
232  auto HeadTail = PacketBundle.first.split('\n');
233  StringRef Separator = "\n";
234  StringRef Indent = "\t";
235  OS << "\t{\n";
236  while (!HeadTail.first.empty()) {
237  StringRef InstTxt;
238  auto Duplex = HeadTail.first.split('\v');
239  if (!Duplex.second.empty()) {
240  OS << Indent << Duplex.first << Separator;
241  InstTxt = Duplex.second;
242  } else if (!HeadTail.first.trim().startswith("immext")) {
243  InstTxt = Duplex.first;
244  }
245  if (!InstTxt.empty())
246  OS << Indent << InstTxt << Separator;
247  HeadTail = HeadTail.second.split('\n');
248  }
249 
251  OS << "\n\t} :mem_noshuf" << PacketBundle.second;
252  else
253  OS << "\t}" << PacketBundle.second;
254  }
255 };
256 
257 class HexagonTargetELFStreamer : public HexagonTargetStreamer {
258 public:
259  MCELFStreamer &getStreamer() {
260  return static_cast<MCELFStreamer &>(Streamer);
261  }
262  HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
264  MCAssembler &MCA = getStreamer().getAssembler();
266  }
267 
268 
269  void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
270  unsigned ByteAlignment,
271  unsigned AccessSize) override {
272  HexagonMCELFStreamer &HexagonELFStreamer =
273  static_cast<HexagonMCELFStreamer &>(getStreamer());
274  HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
275  AccessSize);
276  }
277 
278  void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
279  unsigned ByteAlignment,
280  unsigned AccessSize) override {
281  HexagonMCELFStreamer &HexagonELFStreamer =
282  static_cast<HexagonMCELFStreamer &>(getStreamer());
283  HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
284  Symbol, Size, ByteAlignment, AccessSize);
285  }
286 };
287 
288 } // end anonymous namespace
289 
291  MCInstrInfo *X = new MCInstrInfo();
292  InitHexagonMCInstrInfo(X);
293  return X;
294 }
295 
298  InitHexagonMCRegisterInfo(X, Hexagon::R31);
299  return X;
300 }
301 
303  const Triple &TT,
304  const MCTargetOptions &Options) {
305  MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
306 
307  // VirtualFP = (R30 + #0).
309  nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0);
310  MAI->addInitialFrameState(Inst);
311 
312  return MAI;
313 }
314 
316  unsigned SyntaxVariant,
317  const MCAsmInfo &MAI,
318  const MCInstrInfo &MII,
319  const MCRegisterInfo &MRI)
320 {
321  if (SyntaxVariant == 0)
322  return new HexagonInstPrinter(MAI, MII, MRI);
323  else
324  return nullptr;
325 }
326 
327 static MCTargetStreamer *
329  MCInstPrinter *IP, bool IsVerboseAsm) {
330  return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
331 }
332 
334  std::unique_ptr<MCAsmBackend> &&MAB,
335  std::unique_ptr<MCObjectWriter> &&OW,
336  std::unique_ptr<MCCodeEmitter> &&Emitter,
337  bool RelaxAll) {
339  std::move(Emitter));
340 }
341 
342 static MCTargetStreamer *
344  return new HexagonTargetELFStreamer(S, STI);
345 }
346 
348  if (STI->getFeatureBits()[F])
349  STI->ToggleFeature(F);
350 }
351 
353  return STI->getFeatureBits()[F];
354 }
355 
356 namespace {
357 std::string selectHexagonFS(StringRef CPU, StringRef FS) {
359  if (!FS.empty())
360  Result.push_back(FS);
361 
362  switch (EnableHVX) {
365  break;
367  Result.push_back("+hvxv60");
368  break;
370  Result.push_back("+hvxv62");
371  break;
373  Result.push_back("+hvxv65");
374  break;
376  Result.push_back("+hvxv66");
377  break;
379  Result.push_back("+hvxv67");
380  break;
382  Result.push_back("+hvxv68");
383  break;
385  Result.push_back("+hvxv69");
386  break;
388  Result.push_back(StringSwitch<StringRef>(CPU)
389  .Case("hexagonv60", "+hvxv60")
390  .Case("hexagonv62", "+hvxv62")
391  .Case("hexagonv65", "+hvxv65")
392  .Case("hexagonv66", "+hvxv66")
393  .Case("hexagonv67", "+hvxv67")
394  .Case("hexagonv67t", "+hvxv67")
395  .Case("hexagonv68", "+hvxv68")
396  .Case("hexagonv69", "+hvxv69"));
397  break;
398  }
400  // Sentinel if -mhvx isn't specified
401  break;
402  }
403  if (EnableHvxIeeeFp)
404  Result.push_back("+hvx-ieee-fp");
405  if (EnableHexagonCabac)
406  Result.push_back("+cabac");
407 
408  return join(Result.begin(), Result.end(), ",");
409 }
410 }
411 
412 static bool isCPUValid(const std::string &CPU) {
413  return Hexagon::CpuTable.find(CPU) != Hexagon::CpuTable.cend();
414 }
415 
416 namespace {
417 std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
418  StringRef FS) {
419  std::pair<std::string, std::string> Result;
420  Result.first = std::string(Hexagon_MC::selectHexagonCPU(CPU));
421  Result.second = selectHexagonFS(Result.first, FS);
422  return Result;
423 }
424 std::mutex ArchSubtargetMutex;
425 std::unordered_map<std::string, std::unique_ptr<MCSubtargetInfo const>>
426  ArchSubtarget;
427 } // namespace
428 
429 MCSubtargetInfo const *
431  std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
432  auto Existing = ArchSubtarget.find(std::string(STI->getCPU()));
433  if (Existing == ArchSubtarget.end())
434  return nullptr;
435  return Existing->second.get();
436 }
437 
439  using namespace Hexagon;
440  // Make sure that +hvx-length turns hvx on, and that "hvx" alone
441  // turns on hvxvNN, corresponding to the existing ArchVNN.
442  FeatureBitset FB = S;
443  unsigned CpuArch = ArchV5;
444  for (unsigned F : {ArchV69, ArchV68, ArchV67, ArchV66, ArchV65, ArchV62,
445  ArchV60, ArchV55, ArchV5}) {
446  if (!FB.test(F))
447  continue;
448  CpuArch = F;
449  break;
450  }
451  bool UseHvx = false;
452  for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
453  if (!FB.test(F))
454  continue;
455  UseHvx = true;
456  break;
457  }
458  bool HasHvxVer = false;
459  for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
460  ExtensionHVXV66, ExtensionHVXV67, ExtensionHVXV68,
461  ExtensionHVXV69}) {
462  if (!FB.test(F))
463  continue;
464  HasHvxVer = true;
465  UseHvx = true;
466  break;
467  }
468 
469  if (!UseHvx || HasHvxVer)
470  return FB;
471 
472  // HasHvxVer is false, and UseHvx is true.
473  switch (CpuArch) {
474  case ArchV69:
475  FB.set(ExtensionHVXV69);
477  case ArchV68:
478  FB.set(ExtensionHVXV68);
480  case ArchV67:
481  FB.set(ExtensionHVXV67);
483  case ArchV66:
484  FB.set(ExtensionHVXV66);
486  case ArchV65:
487  FB.set(ExtensionHVXV65);
489  case ArchV62:
490  FB.set(ExtensionHVXV62);
492  case ArchV60:
493  FB.set(ExtensionHVXV60);
494  break;
495  }
496  return FB;
497 }
498 
500  StringRef CPU,
501  StringRef FS) {
502  std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
503  StringRef CPUName = Features.first;
504  StringRef ArchFS = Features.second;
505 
506  MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(
507  TT, CPUName, /*TuneCPU*/ CPUName, ArchFS);
508  if (X != nullptr && (CPUName == "hexagonv67t"))
509  addArchSubtarget(X, ArchFS);
510 
511  if (CPU.equals("help"))
512  exit(0);
513 
514  if (!isCPUValid(CPUName.str())) {
515  errs() << "error: invalid CPU \"" << CPUName.str().c_str()
516  << "\" specified\n";
517  return nullptr;
518  }
519 
520  // Add qfloat subtarget feature by default to v68 and above
521  // unless explicitely disabled
522  if (checkFeature(X, Hexagon::ExtensionHVXV68) &&
523  ArchFS.find("-hvx-qfloat", 0) == std::string::npos) {
524  llvm::FeatureBitset Features = X->getFeatureBits();
525  X->setFeatureBits(Features.set(Hexagon::ExtensionHVXQFloat));
526  }
527 
528  if (HexagonDisableDuplex) {
529  llvm::FeatureBitset Features = X->getFeatureBits();
530  X->setFeatureBits(Features.reset(Hexagon::FeatureDuplex));
531  }
532 
533  X->setFeatureBits(completeHVXFeatures(X->getFeatureBits()));
534 
535  // The Z-buffer instructions are grandfathered in for current
536  // architectures but omitted for new ones. Future instruction
537  // sets may introduce new/conflicting z-buffer instructions.
538  const bool ZRegOnDefault =
539  (CPUName == "hexagonv67") || (CPUName == "hexagonv66");
540  if (ZRegOnDefault) {
541  llvm::FeatureBitset Features = X->getFeatureBits();
542  X->setFeatureBits(Features.set(Hexagon::ExtensionZReg));
543  }
544 
545  return X;
546 }
547 
549  StringRef FS) {
550  assert(STI != nullptr);
551  if (STI->getCPU().contains("t")) {
552  auto ArchSTI = createHexagonMCSubtargetInfo(
553  STI->getTargetTriple(),
554  STI->getCPU().substr(0, STI->getCPU().size() - 1), FS);
555  std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
556  ArchSubtarget[std::string(STI->getCPU())] =
557  std::unique_ptr<MCSubtargetInfo const>(ArchSTI);
558  }
559 }
560 
563 
564  const std::string CPU(STI.getCPU().str());
565  auto F = ElfFlagsByCpuStr.find(CPU);
566  assert(F != ElfFlagsByCpuStr.end() && "Unrecognized Architecture");
567  return F->second;
568 }
569 
571  return makeArrayRef(VectRegRev);
572 }
573 
574 namespace {
575 class HexagonMCInstrAnalysis : public MCInstrAnalysis {
576 public:
577  HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
578 
579  bool isUnconditionalBranch(MCInst const &Inst) const override {
580  //assert(!HexagonMCInstrInfo::isBundle(Inst));
582  }
583 
584  bool isConditionalBranch(MCInst const &Inst) const override {
585  //assert(!HexagonMCInstrInfo::isBundle(Inst));
587  }
588 
589  bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
590  uint64_t Size, uint64_t &Target) const override {
591  if (!(isCall(Inst) || isUnconditionalBranch(Inst) ||
592  isConditionalBranch(Inst)))
593  return false;
594 
595  //assert(!HexagonMCInstrInfo::isBundle(Inst));
597  return false;
598  auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(*Info, Inst));
599  assert(Extended.isExpr());
600  int64_t Value;
601  if(!Extended.getExpr()->evaluateAsAbsolute(Value))
602  return false;
603  Target = Value;
604  return true;
605  }
606 };
607 }
608 
610  return new HexagonMCInstrAnalysis(Info);
611 }
612 
613 // Force static initialization.
615  // Register the MC asm info.
617 
618  // Register the MC instruction info.
621 
622  // Register the MC register info.
625 
626  // Register the MC subtarget info.
629 
630  // Register the MC Code Emitter
633 
634  // Register the asm backend
637 
638 
639  // Register the MC instruction analyzer.
642 
643  // Register the obj streamer
646 
647  // Register the obj target streamer
650 
651  // Register the asm streamer
654 
655  // Register the MC Inst Printer
658 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
HexagonTargetInfo.h
HexagonMCTargetDesc.h
HexagonInstPrinter.h
EnableHvxIeeeFp
static cl::opt< bool > EnableHvxIeeeFp("mhvx-ieee-fp", cl::Hidden, cl::desc("Enable HVX IEEE floating point extensions"))
MCDwarf.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:22
llvm::Hexagon::ArchEnum::NoArch
@ NoArch
llvm::HexagonConvertUnits
unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes)
Definition: HexagonMCTargetDesc.cpp:160
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::Hexagon::ArchEnum::V65
@ V65
HexagonGetArchVariant
static StringRef HexagonGetArchVariant()
Definition: HexagonMCTargetDesc.cpp:115
createMCStreamer
static MCStreamer * createMCStreamer(Triple const &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll)
Definition: HexagonMCTargetDesc.cpp:333
llvm::HexagonDisableCompound
cl::opt< bool > HexagonDisableCompound
llvm::createHexagonMCCodeEmitter
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
Definition: HexagonMCCodeEmitter.cpp:791
T
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
StringRef.h
MCCodeEmitter.h
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:632
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::StringRef::find
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:315
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1176
ErrorHandling.h
llvm::cl::ValueOptional
@ ValueOptional
Definition: CommandLine.h:136
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unsigned GetELFFlags(const MCSubtargetInfo &STI)
Definition: HexagonMCTargetDesc.cpp:561
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static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:972
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static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:823
createHexagonMCInstPrinter
static MCInstPrinter * createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: HexagonMCTargetDesc.cpp:315
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::Hexagon_MC::addArchSubtarget
void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)
Definition: HexagonMCTargetDesc.cpp:548
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
isCPUValid
static bool isCPUValid(const std::string &CPU)
Definition: HexagonMCTargetDesc.cpp:412
llvm::HexagonInstPrinter
Prints bundles as a newline separated list of individual instructions Duplexes are separated by a ver...
Definition: HexagonInstPrinter.h:25
llvm::Hexagon::ArchEnum::V5
@ V5
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:41
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
HexagonArch.h
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:189
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:930
llvm::Hexagon_MC::getArchSubtarget
const MCSubtargetInfo * getArchSubtarget(MCSubtargetInfo const *STI)
Definition: HexagonMCTargetDesc.cpp:430
llvm::MCInstPrinter::printInst
virtual void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS)=0
Print the specified MCInst to the specified raw_ostream.
MCELFStreamer.h
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::Hexagon::ArchEnum::V66
@ V66
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::FeatureBitset::set
FeatureBitset & set()
Definition: SubtargetFeature.h:60
llvm::Lock
static sys::Mutex Lock
Definition: NVPTXUtilities.cpp:39
llvm::StringRef::substr
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:611
llvm::HexagonMCInstrInfo::isMemReorderDisabled
bool isMemReorderDisabled(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:795
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:199
llvm::createHexagonELFStreamer
MCStreamer * createHexagonELFStreamer(Triple const &TT, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > CE)
Definition: HexagonMCELFStreamer.cpp:153
ELF.h
llvm::MCELFStreamer
Definition: MCELFStreamer.h:24
llvm::Hexagon::ElfFlagsByCpuStr
static const std::map< std::string, unsigned > ElfFlagsByCpuStr
Definition: HexagonDepArch.h:52
MCAsmBackend.h
llvm::HexagonDisableDuplex
cl::opt< bool > HexagonDisableDuplex
HexagonMCInstrInfo.h
llvm::StringRef::split
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:749
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
MCContext.h
llvm::HexagonMCInstrInfo::isBundle
bool isBundle(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:539
MCInstrInfo.h
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::Hexagon::ArchEnum::Generic
@ Generic
IP
Definition: NVPTXLowerArgs.cpp:166
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:27
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::MCInstrAnalysis::isUnconditionalBranch
virtual bool isUnconditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:45
llvm::HexagonTargetStreamer
Definition: HexagonTargetStreamer.h:15
llvm::StringRef::contains
LLVM_NODISCARD bool contains(StringRef Other) const
Return true if the given string is a substring of *this, and false otherwise.
Definition: StringRef.h:462
llvm::Hexagon::ArchEnum::V62
@ V62
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:91
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:1097
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
llvm::MCCFIInstruction
Definition: MCDwarf.h:470
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::StringRef::equals
LLVM_NODISCARD bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:187
llvm::MCSubtargetInfo::ToggleFeature
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
Definition: MCSubtargetInfo.cpp:240
llvm::Hexagon::ArchEnum::V67
@ V67
llvm::cl::opt< bool >
llvm::Hexagon_MC::GetVectRegRev
llvm::ArrayRef< MCPhysReg > GetVectRegRev()
Definition: HexagonMCTargetDesc.cpp:570
llvm::MCAssembler
Definition: MCAssembler.h:60
llvm::cl::values
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:697
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:877
HexagonMCELFStreamer.h
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::createHexagonMCInstrInfo
MCInstrInfo * createHexagonMCInstrInfo()
Definition: HexagonMCTargetDesc.cpp:290
uint64_t
llvm::MCInstrAnalysis::isConditionalBranch
virtual bool isConditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:41
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:133
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
createHexagonMCAsmInfo
static MCAsmInfo * createHexagonMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
Definition: HexagonMCTargetDesc.cpp:302
llvm::createHexagonMCRegisterInfo
MCRegisterInfo * createHexagonMCRegisterInfo(StringRef TT)
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
checkFeature
static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo *STI, uint64_t F)
Definition: HexagonMCTargetDesc.cpp:352
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:108
StringExtras.h
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:978
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
MCRegisterInfo.h
llvm::HexagonGetLastSlot
unsigned HexagonGetLastSlot()
Definition: HexagonMCTargetDesc.cpp:158
llvm::MCAssembler::setELFHeaderEFlags
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:264
llvm::formatted_raw_ostream
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Definition: FormattedStream.h:30
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::Hexagon::ArchEnum::V55
@ V55
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:524
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:86
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:850
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::getTheHexagonTarget
Target & getTheHexagonTarget()
Definition: HexagonTargetInfo.cpp:13
EnableHexagonCabac
static cl::opt< bool > EnableHexagonCabac("mcabac", cl::desc("tbd"), cl::init(false))
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
MCInstrAnalysis.h
llvm::Hexagon::CpuTable
static const std::map< std::string, ArchEnum > CpuTable
Definition: HexagonDepArch.h:38
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
clEnumValN
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:672
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::HexagonMCAsmInfo
Definition: HexagonMCAsmInfo.h:21
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:287
llvm::FeatureBitset::reset
constexpr FeatureBitset & reset(unsigned I)
Definition: SubtargetFeature.h:72
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
isUnconditionalBranch
static bool isUnconditionalBranch(Instruction *Term)
Definition: ADCE.cpp:211
llvm::HexagonMCELFStreamer
Definition: HexagonMCELFStreamer.h:20
llvm::HexagonFUnits::isSlot0Only
bool isSlot0Only(unsigned units)
Definition: HexagonMCTargetDesc.cpp:204
llvm::StringRef::size
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
MCObjectWriter.h
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:817
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:943
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
LLVMInitializeHexagonTargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTargetMC()
Definition: HexagonMCTargetDesc.cpp:614
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:837
DisableHVX
static cl::opt< bool > DisableHVX("mno-hvx", cl::Hidden, cl::desc("Disable Hexagon Vector eXtensions"))
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition: TargetRegistry.h:955
llvm::Hexagon::ArchEnum::V69
@ V69
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::HexagonMCInstrInfo::getExtendableOperand
const MCOperand & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:323
llvm::LCOMM::ByteAlignment
@ ByteAlignment
Definition: MCAsmInfo.h:50
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:474
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::Hexagon_MC::createHexagonMCSubtargetInfo
MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a Hexagon MCSubtargetInfo instance.
Definition: HexagonMCTargetDesc.cpp:499
createHexagonMCInstrAnalysis
static MCInstrAnalysis * createHexagonMCInstrAnalysis(const MCInstrInfo *Info)
Definition: HexagonMCTargetDesc.cpp:609
llvm::FeatureBitset::test
constexpr bool test(unsigned I) const
Definition: SubtargetFeature.h:91
llvm::Hexagon_MC::selectHexagonCPU
StringRef selectHexagonCPU(StringRef CPU)
Definition: HexagonMCTargetDesc.cpp:139
createMCAsmTargetStreamer
static MCTargetStreamer * createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *IP, bool IsVerboseAsm)
Definition: HexagonMCTargetDesc.cpp:328
clearFeature
static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo *STI, uint64_t F)
Definition: HexagonMCTargetDesc.cpp:347
DefaultArch
static StringRef DefaultArch
Definition: HexagonMCTargetDesc.cpp:113
exit
declare void exit(i32) noreturn nounwind This compiles into
Definition: README.txt:1072
MCStreamer.h
llvm::Hexagon::ArchEnum::V68
@ V68
createHexagonObjectTargetStreamer
static MCTargetStreamer * createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: HexagonMCTargetDesc.cpp:343
HexagonMCAsmInfo.h
llvm::Hexagon::ArchEnum::V60
@ V60
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:43
llvm::Hexagon_MC::completeHVXFeatures
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
Definition: HexagonMCTargetDesc.cpp:438
llvm::HexagonMCELFStreamer::HexagonMCEmitLocalCommonSymbol
void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
Definition: HexagonMCELFStreamer.cpp:140
llvm::cl::desc
Definition: CommandLine.h:412
raw_ostream.h
HEXAGON_PACKET_SIZE
#define HEXAGON_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
TargetRegistry.h
llvm::createHexagonAsmBackend
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: HexagonAsmBackend.cpp:773
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
HexagonTargetStreamer.h
llvm::HexagonMCELFStreamer::HexagonMCEmitCommonSymbol
void HexagonMCEmitCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
Definition: HexagonMCELFStreamer.cpp:88
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:620