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HexagonMCTargetDesc.cpp
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1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Hexagon specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "HexagonDepArch.h"
15 #include "HexagonTargetStreamer.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/BinaryFormat/ELF.h"
24 #include "llvm/MC/MCAsmBackend.h"
25 #include "llvm/MC/MCAssembler.h"
26 #include "llvm/MC/MCCodeEmitter.h"
27 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCDwarf.h"
29 #include "llvm/MC/MCELFStreamer.h"
31 #include "llvm/MC/MCInstrInfo.h"
32 #include "llvm/MC/MCObjectWriter.h"
33 #include "llvm/MC/MCRegisterInfo.h"
34 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/TargetRegistry.h"
39 #include <cassert>
40 #include <cstdint>
41 #include <mutex>
42 #include <new>
43 #include <string>
44 #include <unordered_map>
45 
46 using namespace llvm;
47 
48 #define GET_INSTRINFO_MC_DESC
49 #define ENABLE_INSTR_PREDICATE_VERIFIER
50 #include "HexagonGenInstrInfo.inc"
51 
52 #define GET_SUBTARGETINFO_MC_DESC
53 #include "HexagonGenSubtargetInfo.inc"
54 
55 #define GET_REGINFO_MC_DESC
56 #include "HexagonGenRegisterInfo.inc"
57 
59  ("mno-compound",
60  cl::desc("Disable looking for compound instructions for Hexagon"));
61 
63  ("mno-pairing",
64  cl::desc("Disable looking for duplex instructions for Hexagon"));
65 
66 namespace { // These flags are to be deprecated
67 cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
68  cl::init(false));
69 cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
70  cl::init(false));
71 cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
72  cl::init(false));
73 cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
74  cl::init(false));
75 cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
76  cl::init(false));
77 cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
78  cl::init(false));
79 cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"),
80  cl::init(false));
81 cl::opt<bool> MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"),
82  cl::init(false));
83 cl::opt<bool> MV68("mv68", cl::Hidden, cl::desc("Build for Hexagon V68"),
84  cl::init(false));
85 cl::opt<bool> MV69("mv69", cl::Hidden, cl::desc("Build for Hexagon V69"),
86  cl::init(false));
87 cl::opt<bool> MV71("mv71", cl::Hidden, cl::desc("Build for Hexagon V71"),
88  cl::init(false));
89 cl::opt<bool> MV71T("mv71t", cl::Hidden, cl::desc("Build for Hexagon V71T"),
90  cl::init(false));
91 cl::opt<bool> MV73("mv73", cl::Hidden, cl::desc("Build for Hexagon V73"),
92  cl::init(false));
93 } // namespace
94 
96  "mhvx", cl::desc("Enable Hexagon Vector eXtensions"),
97  cl::values(clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
98  clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
99  clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
100  clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
101  clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"),
102  clEnumValN(Hexagon::ArchEnum::V68, "v68", "Build for HVX v68"),
103  clEnumValN(Hexagon::ArchEnum::V69, "v69", "Build for HVX v69"),
104  clEnumValN(Hexagon::ArchEnum::V71, "v71", "Build for HVX v71"),
105  clEnumValN(Hexagon::ArchEnum::V73, "v73", "Build for HVX v73"),
106  // Sentinel for no value specified.
108  // Sentinel for flag not present.
110 
111 static cl::opt<bool>
112  DisableHVX("mno-hvx", cl::Hidden,
113  cl::desc("Disable Hexagon Vector eXtensions"));
114 
115 static cl::opt<bool>
116  EnableHvxIeeeFp("mhvx-ieee-fp", cl::Hidden,
117  cl::desc("Enable HVX IEEE floating point extensions"));
119  ("mcabac", cl::desc("tbd"), cl::init(false));
120 
121 static StringRef DefaultArch = "hexagonv60";
122 
124  if (MV5)
125  return "hexagonv5";
126  if (MV55)
127  return "hexagonv55";
128  if (MV60)
129  return "hexagonv60";
130  if (MV62)
131  return "hexagonv62";
132  if (MV65)
133  return "hexagonv65";
134  if (MV66)
135  return "hexagonv66";
136  if (MV67)
137  return "hexagonv67";
138  if (MV67T)
139  return "hexagonv67t";
140  if (MV68)
141  return "hexagonv68";
142  if (MV69)
143  return "hexagonv69";
144  if (MV71)
145  return "hexagonv71";
146  if (MV71T)
147  return "hexagonv71t";
148  if (MV73)
149  return "hexagonv73";
150  return "";
151 }
152 
155  if (!ArchV.empty() && !CPU.empty()) {
156  // Tiny cores have a "t" suffix that is discarded when creating a secondary
157  // non-tiny subtarget. See: addArchSubtarget
158  std::pair<StringRef, StringRef> ArchP = ArchV.split('t');
159  std::pair<StringRef, StringRef> CPUP = CPU.split('t');
160  if (!ArchP.first.equals(CPUP.first))
161  report_fatal_error("conflicting architectures specified.");
162  return CPU;
163  }
164  if (ArchV.empty()) {
165  if (CPU.empty())
166  CPU = DefaultArch;
167  return CPU;
168  }
169  return ArchV;
170 }
171 
172 unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; }
173 
174 unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) {
175  enum {
176  CVI_NONE = 0,
177  CVI_XLANE = 1 << 0,
178  CVI_SHIFT = 1 << 1,
179  CVI_MPY0 = 1 << 2,
180  CVI_MPY1 = 1 << 3,
181  CVI_ZW = 1 << 4
182  };
183 
184  if (ItinUnits == HexagonItinerariesV62FU::CVI_ALL ||
185  ItinUnits == HexagonItinerariesV62FU::CVI_ALL_NOMEM)
186  return (*Lanes = 4, CVI_XLANE);
187  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01 &&
188  ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
189  return (*Lanes = 2, CVI_XLANE | CVI_MPY0);
190  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01)
191  return (*Lanes = 2, CVI_MPY0);
192  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
193  return (*Lanes = 2, CVI_XLANE);
194  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
195  ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT &&
196  ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
197  ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
198  return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1);
199  else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
200  ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT)
201  return (*Lanes = 1, CVI_XLANE | CVI_SHIFT);
202  else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
203  ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
204  return (*Lanes = 1, CVI_MPY0 | CVI_MPY1);
205  else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW)
206  return (*Lanes = 1, CVI_ZW);
207  else if (ItinUnits == HexagonItinerariesV62FU::CVI_XLANE)
208  return (*Lanes = 1, CVI_XLANE);
209  else if (ItinUnits == HexagonItinerariesV62FU::CVI_SHIFT)
210  return (*Lanes = 1, CVI_SHIFT);
211 
212  return (*Lanes = 0, CVI_NONE);
213 }
214 
215 
216 namespace llvm {
217 namespace HexagonFUnits {
218 bool isSlot0Only(unsigned units) {
219  return HexagonItinerariesV62FU::SLOT0 == units;
220 }
221 } // namespace HexagonFUnits
222 } // namespace llvm
223 
224 namespace {
225 
226 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
227 public:
228  HexagonTargetAsmStreamer(MCStreamer &S,
230  bool isVerboseAsm,
231  MCInstPrinter &IP)
233 
234  void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address,
235  const MCInst &Inst, const MCSubtargetInfo &STI,
236  raw_ostream &OS) override {
239  std::string Buffer;
240  {
241  raw_string_ostream TempStream(Buffer);
242  InstPrinter.printInst(&Inst, Address, "", STI, TempStream);
243  }
244  StringRef Contents(Buffer);
245  auto PacketBundle = Contents.rsplit('\n');
246  auto HeadTail = PacketBundle.first.split('\n');
247  StringRef Separator = "\n";
248  StringRef Indent = "\t";
249  OS << "\t{\n";
250  while (!HeadTail.first.empty()) {
251  StringRef InstTxt;
252  auto Duplex = HeadTail.first.split('\v');
253  if (!Duplex.second.empty()) {
254  OS << Indent << Duplex.first << Separator;
255  InstTxt = Duplex.second;
256  } else if (!HeadTail.first.trim().startswith("immext")) {
257  InstTxt = Duplex.first;
258  }
259  if (!InstTxt.empty())
260  OS << Indent << InstTxt << Separator;
261  HeadTail = HeadTail.second.split('\n');
262  }
263 
265  OS << "\n\t} :mem_noshuf" << PacketBundle.second;
266  else
267  OS << "\t}" << PacketBundle.second;
268  }
269 };
270 
271 class HexagonTargetELFStreamer : public HexagonTargetStreamer {
272 public:
273  MCELFStreamer &getStreamer() {
274  return static_cast<MCELFStreamer &>(Streamer);
275  }
276  HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
278  MCAssembler &MCA = getStreamer().getAssembler();
280  }
281 
282 
283  void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
284  unsigned ByteAlignment,
285  unsigned AccessSize) override {
286  HexagonMCELFStreamer &HexagonELFStreamer =
287  static_cast<HexagonMCELFStreamer &>(getStreamer());
288  HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
289  AccessSize);
290  }
291 
292  void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
293  unsigned ByteAlignment,
294  unsigned AccessSize) override {
295  HexagonMCELFStreamer &HexagonELFStreamer =
296  static_cast<HexagonMCELFStreamer &>(getStreamer());
297  HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
298  Symbol, Size, ByteAlignment, AccessSize);
299  }
300 };
301 
302 } // end anonymous namespace
303 
305  MCInstrInfo *X = new MCInstrInfo();
306  InitHexagonMCInstrInfo(X);
307  return X;
308 }
309 
312  InitHexagonMCRegisterInfo(X, Hexagon::R31, /*DwarfFlavour=*/0,
313  /*EHFlavour=*/0, /*PC=*/Hexagon::PC);
314  return X;
315 }
316 
318  const Triple &TT,
319  const MCTargetOptions &Options) {
320  MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
321 
322  // VirtualFP = (R30 + #0).
324  nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0);
325  MAI->addInitialFrameState(Inst);
326 
327  return MAI;
328 }
329 
331  unsigned SyntaxVariant,
332  const MCAsmInfo &MAI,
333  const MCInstrInfo &MII,
334  const MCRegisterInfo &MRI)
335 {
336  if (SyntaxVariant == 0)
337  return new HexagonInstPrinter(MAI, MII, MRI);
338  else
339  return nullptr;
340 }
341 
342 static MCTargetStreamer *
344  MCInstPrinter *IP, bool IsVerboseAsm) {
345  return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
346 }
347 
349  std::unique_ptr<MCAsmBackend> &&MAB,
350  std::unique_ptr<MCObjectWriter> &&OW,
351  std::unique_ptr<MCCodeEmitter> &&Emitter,
352  bool RelaxAll) {
354  std::move(Emitter));
355 }
356 
357 static MCTargetStreamer *
359  return new HexagonTargetELFStreamer(S, STI);
360 }
361 
363  return new HexagonTargetStreamer(S);
364 }
365 
367  if (STI->getFeatureBits()[F])
368  STI->ToggleFeature(F);
369 }
370 
372  return STI->getFeatureBits()[F];
373 }
374 
375 namespace {
376 std::string selectHexagonFS(StringRef CPU, StringRef FS) {
378  if (!FS.empty())
379  Result.push_back(FS);
380 
381  switch (EnableHVX) {
384  break;
386  Result.push_back("+hvxv60");
387  break;
389  Result.push_back("+hvxv62");
390  break;
392  Result.push_back("+hvxv65");
393  break;
395  Result.push_back("+hvxv66");
396  break;
398  Result.push_back("+hvxv67");
399  break;
401  Result.push_back("+hvxv68");
402  break;
404  Result.push_back("+hvxv69");
405  break;
407  Result.push_back("+hvxv71");
408  break;
410  Result.push_back("+hvxv73");
411  break;
413  Result.push_back(StringSwitch<StringRef>(CPU)
414  .Case("hexagonv60", "+hvxv60")
415  .Case("hexagonv62", "+hvxv62")
416  .Case("hexagonv65", "+hvxv65")
417  .Case("hexagonv66", "+hvxv66")
418  .Case("hexagonv67", "+hvxv67")
419  .Case("hexagonv67t", "+hvxv67")
420  .Case("hexagonv68", "+hvxv68")
421  .Case("hexagonv69", "+hvxv69")
422  .Case("hexagonv71", "+hvxv71")
423  .Case("hexagonv71t", "+hvxv71")
424  .Case("hexagonv73", "+hvxv73"));
425  break;
426  }
428  // Sentinel if -mhvx isn't specified
429  break;
430  }
431  if (EnableHvxIeeeFp)
432  Result.push_back("+hvx-ieee-fp");
433  if (EnableHexagonCabac)
434  Result.push_back("+cabac");
435 
436  return join(Result.begin(), Result.end(), ",");
437 }
438 }
439 
440 static bool isCPUValid(StringRef CPU) {
441  return Hexagon::getCpu(CPU).has_value();
442 }
443 
444 namespace {
445 std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
446  StringRef FS) {
447  std::pair<std::string, std::string> Result;
448  Result.first = std::string(Hexagon_MC::selectHexagonCPU(CPU));
449  Result.second = selectHexagonFS(Result.first, FS);
450  return Result;
451 }
452 std::mutex ArchSubtargetMutex;
453 std::unordered_map<std::string, std::unique_ptr<MCSubtargetInfo const>>
454  ArchSubtarget;
455 } // namespace
456 
457 MCSubtargetInfo const *
459  std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
460  auto Existing = ArchSubtarget.find(std::string(STI->getCPU()));
461  if (Existing == ArchSubtarget.end())
462  return nullptr;
463  return Existing->second.get();
464 }
465 
467  using namespace Hexagon;
468  // Make sure that +hvx-length turns hvx on, and that "hvx" alone
469  // turns on hvxvNN, corresponding to the existing ArchVNN.
470  FeatureBitset FB = S;
471  unsigned CpuArch = ArchV5;
472  for (unsigned F : {ArchV73, ArchV71, ArchV69, ArchV68, ArchV67, ArchV66,
473  ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) {
474  if (!FB.test(F))
475  continue;
476  CpuArch = F;
477  break;
478  }
479  bool UseHvx = false;
480  for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
481  if (!FB.test(F))
482  continue;
483  UseHvx = true;
484  break;
485  }
486  bool HasHvxVer = false;
487  for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
488  ExtensionHVXV66, ExtensionHVXV67, ExtensionHVXV68,
489  ExtensionHVXV69, ExtensionHVXV71, ExtensionHVXV73}) {
490  if (!FB.test(F))
491  continue;
492  HasHvxVer = true;
493  UseHvx = true;
494  break;
495  }
496 
497  if (!UseHvx || HasHvxVer)
498  return FB;
499 
500  // HasHvxVer is false, and UseHvx is true.
501  switch (CpuArch) {
502  case ArchV73:
503  FB.set(ExtensionHVXV73);
504  [[fallthrough]];
505  case ArchV71:
506  FB.set(ExtensionHVXV71);
507  [[fallthrough]];
508  case ArchV69:
509  FB.set(ExtensionHVXV69);
510  [[fallthrough]];
511  case ArchV68:
512  FB.set(ExtensionHVXV68);
513  [[fallthrough]];
514  case ArchV67:
515  FB.set(ExtensionHVXV67);
516  [[fallthrough]];
517  case ArchV66:
518  FB.set(ExtensionHVXV66);
519  [[fallthrough]];
520  case ArchV65:
521  FB.set(ExtensionHVXV65);
522  [[fallthrough]];
523  case ArchV62:
524  FB.set(ExtensionHVXV62);
525  [[fallthrough]];
526  case ArchV60:
527  FB.set(ExtensionHVXV60);
528  break;
529  }
530  return FB;
531 }
532 
534  StringRef CPU,
535  StringRef FS) {
536  std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
537  StringRef CPUName = Features.first;
538  StringRef ArchFS = Features.second;
539 
540  MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(
541  TT, CPUName, /*TuneCPU*/ CPUName, ArchFS);
542  if (X != nullptr && (CPUName == "hexagonv67t" || CPUName == "hexagon71t"))
543  addArchSubtarget(X, ArchFS);
544 
545  if (CPU.equals("help"))
546  exit(0);
547 
548  if (!isCPUValid(CPUName.str())) {
549  errs() << "error: invalid CPU \"" << CPUName.str().c_str()
550  << "\" specified\n";
551  return nullptr;
552  }
553 
554  // Add qfloat subtarget feature by default to v68 and above
555  // unless explicitely disabled
556  if (checkFeature(X, Hexagon::ExtensionHVXV68) &&
557  ArchFS.find("-hvx-qfloat", 0) == std::string::npos) {
558  llvm::FeatureBitset Features = X->getFeatureBits();
559  X->setFeatureBits(Features.set(Hexagon::ExtensionHVXQFloat));
560  }
561 
562  if (HexagonDisableDuplex) {
563  llvm::FeatureBitset Features = X->getFeatureBits();
564  X->setFeatureBits(Features.reset(Hexagon::FeatureDuplex));
565  }
566 
567  X->setFeatureBits(completeHVXFeatures(X->getFeatureBits()));
568 
569  // The Z-buffer instructions are grandfathered in for current
570  // architectures but omitted for new ones. Future instruction
571  // sets may introduce new/conflicting z-buffer instructions.
572  const bool ZRegOnDefault =
573  (CPUName == "hexagonv67") || (CPUName == "hexagonv66");
574  if (ZRegOnDefault) {
575  llvm::FeatureBitset Features = X->getFeatureBits();
576  X->setFeatureBits(Features.set(Hexagon::ExtensionZReg));
577  }
578 
579  return X;
580 }
581 
583  assert(STI != nullptr);
584  if (STI->getCPU().contains("t")) {
585  auto ArchSTI = createHexagonMCSubtargetInfo(
586  STI->getTargetTriple(),
587  STI->getCPU().substr(0, STI->getCPU().size() - 1), FS);
588  std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
589  ArchSubtarget[std::string(STI->getCPU())] =
590  std::unique_ptr<MCSubtargetInfo const>(ArchSTI);
591  }
592 }
593 
595  return StringSwitch<unsigned>(STI.getCPU())
597  .Case("hexagonv5", llvm::ELF::EF_HEXAGON_MACH_V5)
598  .Case("hexagonv55", llvm::ELF::EF_HEXAGON_MACH_V55)
599  .Case("hexagonv60", llvm::ELF::EF_HEXAGON_MACH_V60)
600  .Case("hexagonv62", llvm::ELF::EF_HEXAGON_MACH_V62)
601  .Case("hexagonv65", llvm::ELF::EF_HEXAGON_MACH_V65)
602  .Case("hexagonv66", llvm::ELF::EF_HEXAGON_MACH_V66)
603  .Case("hexagonv67", llvm::ELF::EF_HEXAGON_MACH_V67)
604  .Case("hexagonv67t", llvm::ELF::EF_HEXAGON_MACH_V67T)
605  .Case("hexagonv68", llvm::ELF::EF_HEXAGON_MACH_V68)
606  .Case("hexagonv69", llvm::ELF::EF_HEXAGON_MACH_V69)
607  .Case("hexagonv71", llvm::ELF::EF_HEXAGON_MACH_V71)
608  .Case("hexagonv71t", llvm::ELF::EF_HEXAGON_MACH_V71T)
609  .Case("hexagonv73", llvm::ELF::EF_HEXAGON_MACH_V73);
610 }
611 
613  return makeArrayRef(VectRegRev);
614 }
615 
616 namespace {
617 class HexagonMCInstrAnalysis : public MCInstrAnalysis {
618 public:
619  HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
620 
621  bool isUnconditionalBranch(MCInst const &Inst) const override {
622  //assert(!HexagonMCInstrInfo::isBundle(Inst));
624  }
625 
626  bool isConditionalBranch(MCInst const &Inst) const override {
627  //assert(!HexagonMCInstrInfo::isBundle(Inst));
629  }
630 
631  bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
632  uint64_t Size, uint64_t &Target) const override {
633  if (!(isCall(Inst) || isUnconditionalBranch(Inst) ||
634  isConditionalBranch(Inst)))
635  return false;
636 
637  //assert(!HexagonMCInstrInfo::isBundle(Inst));
639  return false;
641  assert(Extended.isExpr());
642  int64_t Value;
643  if (!Extended.getExpr()->evaluateAsAbsolute(Value))
644  return false;
645  Target = Value;
646  return true;
647  }
648 };
649 }
650 
652  return new HexagonMCInstrAnalysis(Info);
653 }
654 
655 // Force static initialization.
657  // Register the MC asm info.
659 
660  // Register the MC instruction info.
663 
664  // Register the MC register info.
667 
668  // Register the MC subtarget info.
671 
672  // Register the MC Code Emitter
675 
676  // Register the asm backend
679 
680  // Register the MC instruction analyzer.
683 
684  // Register the obj streamer
686 
687  // Register the obj target streamer
690 
691  // Register the asm streamer
694 
695  // Register the null streamer
698 
699  // Register the MC Inst Printer
702 }
HexagonTargetInfo.h
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:70
HexagonMCTargetDesc.h
llvm::Hexagon::ArchEnum::V73
@ V73
HexagonInstPrinter.h
EnableHvxIeeeFp
static cl::opt< bool > EnableHvxIeeeFp("mhvx-ieee-fp", cl::Hidden, cl::desc("Enable HVX IEEE floating point extensions"))
MCDwarf.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Hexagon::ArchEnum::NoArch
@ NoArch
llvm::HexagonConvertUnits
unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes)
Definition: HexagonMCTargetDesc.cpp:174
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::ELF::EF_HEXAGON_MACH_V65
@ EF_HEXAGON_MACH_V65
Definition: ELF.h:617
llvm::Hexagon::ArchEnum::V65
@ V65
HexagonGetArchVariant
static StringRef HexagonGetArchVariant()
Definition: HexagonMCTargetDesc.cpp:123
createMCStreamer
static MCStreamer * createMCStreamer(Triple const &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll)
Definition: HexagonMCTargetDesc.cpp:348
llvm::HexagonDisableCompound
cl::opt< bool > HexagonDisableCompound
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
StringRef.h
MCCodeEmitter.h
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:629
isCPUValid
static bool isCPUValid(StringRef CPU)
Definition: HexagonMCTargetDesc.cpp:440
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
ErrorHandling.h
llvm::ELF::EF_HEXAGON_MACH_V69
@ EF_HEXAGON_MACH_V69
Definition: ELF.h:622
llvm::cl::ValueOptional
@ ValueOptional
Definition: CommandLine.h:133
llvm::Hexagon_MC::GetELFFlags
unsigned GetELFFlags(const MCSubtargetInfo &STI)
Definition: HexagonMCTargetDesc.cpp:594
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1038
llvm::ELF::EF_HEXAGON_MACH_V55
@ EF_HEXAGON_MACH_V55
Definition: ELF.h:614
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:881
createHexagonMCInstPrinter
static MCInstPrinter * createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: HexagonMCTargetDesc.cpp:330
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCAssembler.h
llvm::Hexagon_MC::addArchSubtarget
void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)
Definition: HexagonMCTargetDesc.cpp:582
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::HexagonInstPrinter
Prints bundles as a newline separated list of individual instructions Duplexes are separated by a ver...
Definition: HexagonInstPrinter.h:25
llvm::X86AS::FS
@ FS
Definition: X86.h:200
llvm::StringRef::substr
StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:564
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::Hexagon::ArchEnum::V5
@ V5
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:891
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:172
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:988
llvm::Hexagon_MC::getArchSubtarget
const MCSubtargetInfo * getArchSubtarget(MCSubtargetInfo const *STI)
Definition: HexagonMCTargetDesc.cpp:458
llvm::MCInstPrinter::printInst
virtual void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS)=0
Print the specified MCInst to the specified raw_ostream.
MCELFStreamer.h
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::Hexagon::ArchEnum::V66
@ V66
llvm::FeatureBitset::set
FeatureBitset & set()
Definition: SubtargetFeature.h:56
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::HexagonMCInstrInfo::isMemReorderDisabled
bool isMemReorderDisabled(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:795
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:212
Emitter
dxil DXContainer Global Emitter
Definition: DXContainerGlobals.cpp:67
llvm::createHexagonELFStreamer
MCStreamer * createHexagonELFStreamer(Triple const &TT, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > CE)
Definition: HexagonMCELFStreamer.cpp:152
ELF.h
llvm::MCELFStreamer
Definition: MCELFStreamer.h:31
MCAsmBackend.h
llvm::HexagonDisableDuplex
cl::opt< bool > HexagonDisableDuplex
llvm::ELF::EF_HEXAGON_MACH_V71
@ EF_HEXAGON_MACH_V71
Definition: ELF.h:623
HexagonMCInstrInfo.h
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:108
MCContext.h
llvm::HexagonMCInstrInfo::isBundle
bool isBundle(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:539
MCInstrInfo.h
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::ELF::EF_HEXAGON_MACH_V73
@ EF_HEXAGON_MACH_V73
Definition: ELF.h:625
llvm::Hexagon::ArchEnum::Generic
@ Generic
IP
Definition: NVPTXLowerArgs.cpp:168
llvm::ELF::EF_HEXAGON_MACH_V60
@ EF_HEXAGON_MACH_V60
Definition: ELF.h:615
llvm::Hexagon::ArchEnum::V71
@ V71
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:30
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::MCInstrAnalysis::isUnconditionalBranch
virtual bool isUnconditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:48
llvm::HexagonTargetStreamer
Definition: HexagonTargetStreamer.h:15
llvm::ELF::EF_HEXAGON_MACH_V71T
@ EF_HEXAGON_MACH_V71T
Definition: ELF.h:624
llvm::Hexagon::ArchEnum::V62
@ V62
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:93
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:1178
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
llvm::ELF::EF_HEXAGON_MACH_V66
@ EF_HEXAGON_MACH_V66
Definition: ELF.h:618
llvm::MCCFIInstruction
Definition: MCDwarf.h:478
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::StringRef::equals
bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:164
llvm::MCSubtargetInfo::ToggleFeature
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
Definition: MCSubtargetInfo.cpp:240
llvm::Hexagon::ArchEnum::V67
@ V67
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::cl::opt< bool >
llvm::Hexagon_MC::GetVectRegRev
llvm::ArrayRef< MCPhysReg > GetVectRegRev()
Definition: HexagonMCTargetDesc.cpp:612
llvm::MCAssembler
Definition: MCAssembler.h:73
llvm::cl::values
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:705
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:935
HexagonMCELFStreamer.h
llvm::createHexagonMCInstrInfo
MCInstrInfo * createHexagonMCInstrInfo()
Definition: HexagonMCTargetDesc.cpp:304
uint64_t
llvm::MCInstrAnalysis::isConditionalBranch
virtual bool isConditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:44
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
createHexagonMCAsmInfo
static MCAsmInfo * createHexagonMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
Definition: HexagonMCTargetDesc.cpp:317
llvm::createHexagonMCRegisterInfo
MCRegisterInfo * createHexagonMCRegisterInfo(StringRef TT)
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
checkFeature
static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo *STI, uint64_t F)
Definition: HexagonMCTargetDesc.cpp:371
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:109
StringExtras.h
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1044
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
MCRegisterInfo.h
llvm::HexagonGetLastSlot
unsigned HexagonGetLastSlot()
Definition: HexagonMCTargetDesc.cpp:172
llvm::MCAssembler::setELFHeaderEFlags
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:277
llvm::formatted_raw_ostream
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Definition: FormattedStream.h:30
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::Hexagon::ArchEnum::V55
@ V55
llvm::Hexagon::getCpu
Optional< Hexagon::ArchEnum > getCpu(StringRef CPU)
Definition: HexagonDepArch.h:32
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:532
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:86
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:908
llvm::MCTargetOptions
Definition: MCTargetOptions.h:37
createHexagonNullTargetStreamer
static MCTargetStreamer * createHexagonNullTargetStreamer(MCStreamer &S)
Definition: HexagonMCTargetDesc.cpp:362
llvm::getTheHexagonTarget
Target & getTheHexagonTarget()
Definition: HexagonTargetInfo.cpp:13
EnableHexagonCabac
static cl::opt< bool > EnableHexagonCabac("mcabac", cl::desc("tbd"), cl::init(false))
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
MCInstrAnalysis.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
clEnumValN
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:680
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::HexagonMCAsmInfo
Definition: HexagonMCAsmInfo.h:21
llvm::ELF::EF_HEXAGON_MACH_V68
@ EF_HEXAGON_MACH_V68
Definition: ELF.h:621
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::FeatureBitset::reset
constexpr FeatureBitset & reset(unsigned I)
Definition: SubtargetFeature.h:68
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
isUnconditionalBranch
static bool isUnconditionalBranch(Instruction *Term)
Definition: ADCE.cpp:211
llvm::HexagonMCELFStreamer
Definition: HexagonMCELFStreamer.h:20
llvm::HexagonFUnits::isSlot0Only
bool isSlot0Only(unsigned units)
Definition: HexagonMCTargetDesc.cpp:218
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
MCObjectWriter.h
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:875
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:1001
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
LLVMInitializeHexagonTargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTargetMC()
Definition: HexagonMCTargetDesc.cpp:656
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:895
DisableHVX
static cl::opt< bool > DisableHVX("mno-hvx", cl::Hidden, cl::desc("Disable Hexagon Vector eXtensions"))
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition: TargetRegistry.h:1013
llvm::Hexagon::ArchEnum::V69
@ V69
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::HexagonMCInstrInfo::getExtendableOperand
const MCOperand & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:323
llvm::LCOMM::ByteAlignment
@ ByteAlignment
Definition: MCAsmInfo.h:50
llvm::TargetRegistry::RegisterNullTargetStreamer
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1033
llvm::ELF::EF_HEXAGON_MACH_V5
@ EF_HEXAGON_MACH_V5
Definition: ELF.h:613
llvm::StringRef::contains
bool contains(StringRef Other) const
Return true if the given string is a substring of *this, and false otherwise.
Definition: StringRef.h:428
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
HexagonDepArch.h
llvm::Hexagon_MC::createHexagonMCSubtargetInfo
MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a Hexagon MCSubtargetInfo instance.
Definition: HexagonMCTargetDesc.cpp:533
createHexagonMCInstrAnalysis
static MCInstrAnalysis * createHexagonMCInstrAnalysis(const MCInstrInfo *Info)
Definition: HexagonMCTargetDesc.cpp:651
llvm::FeatureBitset::test
constexpr bool test(unsigned I) const
Definition: SubtargetFeature.h:87
llvm::createHexagonMCCodeEmitter
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, MCContext &MCT)
Definition: HexagonMCCodeEmitter.cpp:789
llvm::Hexagon_MC::selectHexagonCPU
StringRef selectHexagonCPU(StringRef CPU)
Definition: HexagonMCTargetDesc.cpp:153
createMCAsmTargetStreamer
static MCTargetStreamer * createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *IP, bool IsVerboseAsm)
Definition: HexagonMCTargetDesc.cpp:343
clearFeature
static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo *STI, uint64_t F)
Definition: HexagonMCTargetDesc.cpp:366
DefaultArch
static StringRef DefaultArch
Definition: HexagonMCTargetDesc.cpp:121
llvm::logicalview::LVAttributeKind::Extended
@ Extended
exit
declare void exit(i32) noreturn nounwind This compiles into
Definition: README.txt:1072
MCStreamer.h
llvm::Hexagon::ArchEnum::V68
@ V68
createHexagonObjectTargetStreamer
static MCTargetStreamer * createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: HexagonMCTargetDesc.cpp:358
EnableHVX
cl::opt< Hexagon::ArchEnum > EnableHVX("mhvx", cl::desc("Enable Hexagon Vector eXtensions"), cl::values(clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"), clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"), clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"), clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"), clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"), clEnumValN(Hexagon::ArchEnum::V68, "v68", "Build for HVX v68"), clEnumValN(Hexagon::ArchEnum::V69, "v69", "Build for HVX v69"), clEnumValN(Hexagon::ArchEnum::V71, "v71", "Build for HVX v71"), clEnumValN(Hexagon::ArchEnum::V73, "v73", "Build for HVX v73"), clEnumValN(Hexagon::ArchEnum::Generic, "", "")), cl::init(Hexagon::ArchEnum::NoArch), cl::ValueOptional)
HexagonMCAsmInfo.h
llvm::Hexagon::ArchEnum::V60
@ V60
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:45
llvm::StringRef::str
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:221
llvm::StringRef::find
size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:294
llvm::Hexagon_MC::completeHVXFeatures
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
Definition: HexagonMCTargetDesc.cpp:466
llvm::HexagonMCELFStreamer::HexagonMCEmitLocalCommonSymbol
void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
Definition: HexagonMCELFStreamer.cpp:139
llvm::cl::desc
Definition: CommandLine.h:413
raw_ostream.h
llvm::ELF::EF_HEXAGON_MACH_V67T
@ EF_HEXAGON_MACH_V67T
Definition: ELF.h:620
HEXAGON_PACKET_SIZE
#define HEXAGON_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
TargetRegistry.h
llvm::createHexagonAsmBackend
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: HexagonAsmBackend.cpp:774
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::StringRef::split
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:692
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
HexagonTargetStreamer.h
llvm::ELF::EF_HEXAGON_MACH_V62
@ EF_HEXAGON_MACH_V62
Definition: ELF.h:616
llvm::HexagonMCELFStreamer::HexagonMCEmitCommonSymbol
void HexagonMCEmitCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
Definition: HexagonMCELFStreamer.cpp:88
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:620
llvm::ELF::EF_HEXAGON_MACH_V67
@ EF_HEXAGON_MACH_V67
Definition: ELF.h:619