LLVM  14.0.0git
Namespaces | Macros | Functions | Variables
HexagonGenInsert.cpp File Reference
#include "BitTracker.h"
#include "HexagonBitTracker.h"
#include "HexagonInstrInfo.h"
#include "HexagonRegisterInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/GraphTraits.h"
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <utility>
#include <vector>
Include dependency graph for HexagonGenInsert.cpp:

Go to the source code of this file.

Namespaces

 llvm
 This is an optimization pass for GlobalISel generic memory operations.
 

Macros

#define DEBUG_TYPE   "hexinsert"
 

Functions

static bool isDebug ()
 
void llvm::initializeHexagonGenInsertPass (PassRegistry &)
 
FunctionPassllvm::createHexagonGenInsert ()
 
 INITIALIZE_PASS_BEGIN (HexagonGenInsert, "hexinsert", "Hexagon generate \"insert\" instructions", false, false) INITIALIZE_PASS_END(HexagonGenInsert
 

Variables

static cl::opt< unsigned > VRegIndexCutoff ("insert-vreg-cutoff", cl::init(~0U), cl::Hidden, cl::ZeroOrMore, cl::desc("Vreg# cutoff for insert generation."))
 
static cl::opt< unsigned > VRegDistCutoff ("insert-dist-cutoff", cl::init(30U), cl::Hidden, cl::ZeroOrMore, cl::desc("Vreg distance cutoff for insert " "generation."))
 
static cl::opt< unsigned > MaxORLSize ("insert-max-orl", cl::init(4096), cl::Hidden, cl::ZeroOrMore, cl::desc("Maximum size of OrderedRegisterList"))
 
static cl::opt< unsigned > MaxIFMSize ("insert-max-ifmap", cl::init(1024), cl::Hidden, cl::ZeroOrMore, cl::desc("Maximum size of IFMap"))
 
static cl::opt< bool > OptTiming ("insert-timing", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable timing of insert generation"))
 
static cl::opt< bool > OptTimingDetail ("insert-timing-detail", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable detailed timing of insert " "generation"))
 
static cl::opt< bool > OptSelectAll0 ("insert-all0", cl::init(false), cl::Hidden, cl::ZeroOrMore)
 
static cl::opt< bool > OptSelectHas0 ("insert-has0", cl::init(false), cl::Hidden, cl::ZeroOrMore)
 
static cl::opt< bool > OptConst ("insert-const", cl::init(false), cl::Hidden, cl::ZeroOrMore)
 
 hexinsert
 
Hexagon generate insert instructions
 
Hexagon generate insert false
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "hexinsert"

Definition at line 46 of file HexagonGenInsert.cpp.

Function Documentation

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN ( HexagonGenInsert  ,
"hexinsert"  ,
"Hexagon generate \"insert\" instructions"  ,
false  ,
false   
)

◆ isDebug()

static bool isDebug ( )
inlinestatic

Definition at line 81 of file HexagonGenInsert.cpp.

References DEBUG_TYPE, llvm::DebugFlag, and llvm::isCurrentDebugType().

Variable Documentation

◆ false

Hexagon generate insert false

Definition at line 1618 of file HexagonGenInsert.cpp.

◆ hexinsert

hexinsert

Definition at line 1617 of file HexagonGenInsert.cpp.

◆ instructions

Hexagon generate insert instructions

Definition at line 1618 of file HexagonGenInsert.cpp.

◆ MaxIFMSize

cl::opt<unsigned> MaxIFMSize("insert-max-ifmap", cl::init(1024), cl::Hidden, cl::ZeroOrMore, cl::desc("Maximum size of IFMap"))
static

◆ MaxORLSize

cl::opt<unsigned> MaxORLSize("insert-max-orl", cl::init(4096), cl::Hidden, cl::ZeroOrMore, cl::desc("Maximum size of OrderedRegisterList"))
static

◆ OptConst

cl::opt<bool> OptConst("insert-const", cl::init(false), cl::Hidden, cl::ZeroOrMore)
static

◆ OptSelectAll0

cl::opt<bool> OptSelectAll0("insert-all0", cl::init(false), cl::Hidden, cl::ZeroOrMore)
static

◆ OptSelectHas0

cl::opt<bool> OptSelectHas0("insert-has0", cl::init(false), cl::Hidden, cl::ZeroOrMore)
static

◆ OptTiming

cl::opt<bool> OptTiming("insert-timing", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable timing of insert generation"))
static

◆ OptTimingDetail

cl::opt<bool> OptTimingDetail("insert-timing-detail", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable detailed timing of insert " "generation"))
static

◆ VRegDistCutoff

cl::opt<unsigned> VRegDistCutoff("insert-dist-cutoff", cl::init(30U), cl::Hidden, cl::ZeroOrMore, cl::desc("Vreg distance cutoff for insert " "generation."))
static

◆ VRegIndexCutoff

cl::opt<unsigned> VRegIndexCutoff("insert-vreg-cutoff", cl::init(~0U), cl::Hidden, cl::ZeroOrMore, cl::desc("Vreg# cutoff for insert generation."))
static