Go to the documentation of this file.
9 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONBITTRACKER_H
10 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONBITTRACKER_H
18 class HexagonInstrInfo;
19 class HexagonRegisterInfo;
20 class MachineFrameInfo;
21 class MachineFunction;
23 class MachineRegisterInfo;
57 unsigned getNextPhysReg(
unsigned PReg,
unsigned Width)
const;
58 unsigned getVirtRegFor(
unsigned PReg)
const;
71 using RegExtMap = DenseMap<unsigned, ExtType>;
77 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONBITTRACKER_H
This is an optimization pass for GlobalISel generic memory operations.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Reg
All possible values of the reg field in the ModR/M byte.
The instances of the Type class are immutable: once they are created, they are never changed.
uint16_t getPhysRegBitWidth(MCRegister Reg) const override
std::map< unsigned, RegisterCell > CellMapType
BitTracker::CellMapType CellMapType
bitcast float %x to i32 %s=and i32 %t, 2147483647 %d=bitcast i32 %s to float ret float %d } declare float @fabsf(float %n) define float @bar(float %x) nounwind { %d=call float @fabsf(float %x) ret float %d } This IR(from PR6194):target datalayout="e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple="x86_64-apple-darwin10.0.0" %0=type { double, double } %struct.float3=type { float, float, float } define void @test(%0, %struct.float3 *nocapture %res) nounwind noinline ssp { entry:%tmp18=extractvalue %0 %0, 0 t
BitTracker::BitMask mask(Register Reg, unsigned Sub) const override
SetVector< const MachineBasicBlock * > BranchTargetList
Representation of each machine instruction.
HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri, const HexagonInstrInfo &tii, MachineFunction &mf)
bool evaluate(const MachineInstr &MI, const CellMapType &Inputs, CellMapType &Outputs) const override
Wrapper class representing virtual and physical registers.
const TargetRegisterClass & composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const override
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
A vector that has set insertion semantics.
const HexagonInstrInfo & TII
Wrapper class representing physical registers. Should be passed by value.