LLVM  14.0.0git
MachineSSAUpdater.cpp
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1 //===- MachineSSAUpdater.cpp - Unstructured SSA Update Tool ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the MachineSSAUpdater class. It's based on SSAUpdater
10 // class in lib/Transforms/Utils.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/Support/Debug.h"
31 #include <utility>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "machine-ssaupdater"
36 
38 
39 static AvailableValsTy &getAvailableVals(void *AV) {
40  return *static_cast<AvailableValsTy*>(AV);
41 }
42 
45  : InsertedPHIs(NewPHI), TII(MF.getSubtarget().getInstrInfo()),
46  MRI(&MF.getRegInfo()) {}
47 
49  delete static_cast<AvailableValsTy*>(AV);
50 }
51 
52 /// Initialize - Reset this object to get ready for a new set of SSA
53 /// updates.
55  if (!AV)
56  AV = new AvailableValsTy();
57  else
58  getAvailableVals(AV).clear();
59 
60  VRC = RC;
61 }
62 
64  Initialize(MRI->getRegClass(V));
65 }
66 
67 /// HasValueForBlock - Return true if the MachineSSAUpdater already has a value for
68 /// the specified block.
70  return getAvailableVals(AV).count(BB);
71 }
72 
73 /// AddAvailableValue - Indicate that a rewritten value is available in the
74 /// specified block with the specified value.
76  getAvailableVals(AV)[BB] = V;
77 }
78 
79 /// GetValueAtEndOfBlock - Construct SSA form, materializing a value that is
80 /// live at the end of the specified block.
82  return GetValueAtEndOfBlockInternal(BB);
83 }
84 
85 static
87  SmallVectorImpl<std::pair<MachineBasicBlock *, Register>> &PredValues) {
88  if (BB->empty())
89  return Register();
90 
91  MachineBasicBlock::iterator I = BB->begin();
92  if (!I->isPHI())
93  return Register();
94 
95  AvailableValsTy AVals;
96  for (unsigned i = 0, e = PredValues.size(); i != e; ++i)
97  AVals[PredValues[i].first] = PredValues[i].second;
98  while (I != BB->end() && I->isPHI()) {
99  bool Same = true;
100  for (unsigned i = 1, e = I->getNumOperands(); i != e; i += 2) {
101  Register SrcReg = I->getOperand(i).getReg();
102  MachineBasicBlock *SrcBB = I->getOperand(i+1).getMBB();
103  if (AVals[SrcBB] != SrcReg) {
104  Same = false;
105  break;
106  }
107  }
108  if (Same)
109  return I->getOperand(0).getReg();
110  ++I;
111  }
112  return Register();
113 }
114 
115 /// InsertNewDef - Insert an empty PHI or IMPLICIT_DEF instruction which define
116 /// a value of the given register class at the start of the specified basic
117 /// block. It returns the virtual register defined by the instruction.
118 static
121  const TargetRegisterClass *RC,
123  const TargetInstrInfo *TII) {
124  Register NewVR = MRI->createVirtualRegister(RC);
125  return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR);
126 }
127 
128 /// GetValueInMiddleOfBlock - Construct SSA form, materializing a value that
129 /// is live in the middle of the specified block.
130 ///
131 /// GetValueInMiddleOfBlock is the same as GetValueAtEndOfBlock except in one
132 /// important case: if there is a definition of the rewritten value after the
133 /// 'use' in BB. Consider code like this:
134 ///
135 /// X1 = ...
136 /// SomeBB:
137 /// use(X)
138 /// X2 = ...
139 /// br Cond, SomeBB, OutBB
140 ///
141 /// In this case, there are two values (X1 and X2) added to the AvailableVals
142 /// set by the client of the rewriter, and those values are both live out of
143 /// their respective blocks. However, the use of X happens in the *middle* of
144 /// a block. Because of this, we need to insert a new PHI node in SomeBB to
145 /// merge the appropriate values, and this value isn't live out of the block.
147  // If there is no definition of the renamed variable in this block, just use
148  // GetValueAtEndOfBlock to do our work.
149  if (!HasValueForBlock(BB))
150  return GetValueAtEndOfBlockInternal(BB);
151 
152  // If there are no predecessors, just return undef.
153  if (BB->pred_empty()) {
154  // Insert an implicit_def to represent an undef value.
155  MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
156  BB, BB->getFirstTerminator(),
157  VRC, MRI, TII);
158  return NewDef->getOperand(0).getReg();
159  }
160 
161  // Otherwise, we have the hard case. Get the live-in values for each
162  // predecessor.
164  Register SingularValue;
165 
166  bool isFirstPred = true;
167  for (MachineBasicBlock *PredBB : BB->predecessors()) {
168  Register PredVal = GetValueAtEndOfBlockInternal(PredBB);
169  PredValues.push_back(std::make_pair(PredBB, PredVal));
170 
171  // Compute SingularValue.
172  if (isFirstPred) {
173  SingularValue = PredVal;
174  isFirstPred = false;
175  } else if (PredVal != SingularValue)
176  SingularValue = Register();
177  }
178 
179  // Otherwise, if all the merged values are the same, just use it.
180  if (SingularValue)
181  return SingularValue;
182 
183  // If an identical PHI is already in BB, just reuse it.
184  Register DupPHI = LookForIdenticalPHI(BB, PredValues);
185  if (DupPHI)
186  return DupPHI;
187 
188  // Otherwise, we do need a PHI: insert one now.
189  MachineBasicBlock::iterator Loc = BB->empty() ? BB->end() : BB->begin();
190  MachineInstrBuilder InsertedPHI = InsertNewDef(TargetOpcode::PHI, BB,
191  Loc, VRC, MRI, TII);
192 
193  // Fill in all the predecessors of the PHI.
194  for (unsigned i = 0, e = PredValues.size(); i != e; ++i)
195  InsertedPHI.addReg(PredValues[i].second).addMBB(PredValues[i].first);
196 
197  // See if the PHI node can be merged to a single value. This can happen in
198  // loop cases when we get a PHI of itself and one other value.
199  if (unsigned ConstVal = InsertedPHI->isConstantValuePHI()) {
200  InsertedPHI->eraseFromParent();
201  return ConstVal;
202  }
203 
204  // If the client wants to know about all new instructions, tell it.
205  if (InsertedPHIs) InsertedPHIs->push_back(InsertedPHI);
206 
207  LLVM_DEBUG(dbgs() << " Inserted PHI: " << *InsertedPHI << "\n");
208  return InsertedPHI.getReg(0);
209 }
210 
211 static
213  MachineOperand *U) {
214  for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
215  if (&MI->getOperand(i) == U)
216  return MI->getOperand(i+1).getMBB();
217  }
218 
219  llvm_unreachable("MachineOperand::getParent() failure?");
220 }
221 
222 /// RewriteUse - Rewrite a use of the symbolic value. This handles PHI nodes,
223 /// which use their value in the corresponding predecessor.
226  Register NewVR;
227  if (UseMI->isPHI()) {
229  NewVR = GetValueAtEndOfBlockInternal(SourceBB);
230  } else {
232  }
233 
234  U.setReg(NewVR);
235 }
236 
237 namespace llvm {
238 
239 /// SSAUpdaterTraits<MachineSSAUpdater> - Traits for the SSAUpdaterImpl
240 /// template, specialized for MachineSSAUpdater.
241 template<>
243 public:
245  using ValT = Register;
248 
249  static BlkSucc_iterator BlkSucc_begin(BlkT *BB) { return BB->succ_begin(); }
250  static BlkSucc_iterator BlkSucc_end(BlkT *BB) { return BB->succ_end(); }
251 
252  /// Iterator for PHI operands.
253  class PHI_iterator {
254  private:
255  MachineInstr *PHI;
256  unsigned idx;
257 
258  public:
259  explicit PHI_iterator(MachineInstr *P) // begin iterator
260  : PHI(P), idx(1) {}
261  PHI_iterator(MachineInstr *P, bool) // end iterator
262  : PHI(P), idx(PHI->getNumOperands()) {}
263 
264  PHI_iterator &operator++() { idx += 2; return *this; }
265  bool operator==(const PHI_iterator& x) const { return idx == x.idx; }
266  bool operator!=(const PHI_iterator& x) const { return !operator==(x); }
267 
268  unsigned getIncomingValue() { return PHI->getOperand(idx).getReg(); }
269 
271  return PHI->getOperand(idx+1).getMBB();
272  }
273  };
274 
275  static inline PHI_iterator PHI_begin(PhiT *PHI) { return PHI_iterator(PHI); }
276 
277  static inline PHI_iterator PHI_end(PhiT *PHI) {
278  return PHI_iterator(PHI, true);
279  }
280 
281  /// FindPredecessorBlocks - Put the predecessors of BB into the Preds
282  /// vector.
285  append_range(*Preds, BB->predecessors());
286  }
287 
288  /// GetUndefVal - Create an IMPLICIT_DEF instruction with a new register.
289  /// Add it into the specified block and return the register.
291  MachineSSAUpdater *Updater) {
292  // Insert an implicit_def to represent an undef value.
293  MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
294  BB, BB->getFirstNonPHI(),
295  Updater->VRC, Updater->MRI,
296  Updater->TII);
297  return NewDef->getOperand(0).getReg();
298  }
299 
300  /// CreateEmptyPHI - Create a PHI instruction that defines a new register.
301  /// Add it into the specified block and return the register.
302  static Register CreateEmptyPHI(MachineBasicBlock *BB, unsigned NumPreds,
303  MachineSSAUpdater *Updater) {
304  MachineBasicBlock::iterator Loc = BB->empty() ? BB->end() : BB->begin();
305  MachineInstr *PHI = InsertNewDef(TargetOpcode::PHI, BB, Loc,
306  Updater->VRC, Updater->MRI,
307  Updater->TII);
308  return PHI->getOperand(0).getReg();
309  }
310 
311  /// AddPHIOperand - Add the specified value as an operand of the PHI for
312  /// the specified predecessor block.
313  static void AddPHIOperand(MachineInstr *PHI, Register Val,
314  MachineBasicBlock *Pred) {
315  MachineInstrBuilder(*Pred->getParent(), PHI).addReg(Val).addMBB(Pred);
316  }
317 
318  /// InstrIsPHI - Check if an instruction is a PHI.
320  if (I && I->isPHI())
321  return I;
322  return nullptr;
323  }
324 
325  /// ValueIsPHI - Check if the instruction that defines the specified register
326  /// is a PHI instruction.
328  return InstrIsPHI(Updater->MRI->getVRegDef(Val));
329  }
330 
331  /// ValueIsNewPHI - Like ValueIsPHI but also check if the PHI has no source
332  /// operands, i.e., it was just added.
334  MachineInstr *PHI = ValueIsPHI(Val, Updater);
335  if (PHI && PHI->getNumOperands() <= 1)
336  return PHI;
337  return nullptr;
338  }
339 
340  /// GetPHIValue - For the specified PHI instruction, return the register
341  /// that it defines.
343  return PHI->getOperand(0).getReg();
344  }
345 };
346 
347 } // end namespace llvm
348 
349 /// GetValueAtEndOfBlockInternal - Check to see if AvailableVals has an entry
350 /// for the specified BB and if so, return it. If not, construct SSA form by
351 /// first calculating the required placement of PHIs and then inserting new
352 /// PHIs where needed.
353 Register MachineSSAUpdater::GetValueAtEndOfBlockInternal(MachineBasicBlock *BB){
354  AvailableValsTy &AvailableVals = getAvailableVals(AV);
355  if (Register V = AvailableVals[BB])
356  return V;
357 
358  SSAUpdaterImpl<MachineSSAUpdater> Impl(this, &AvailableVals, InsertedPHIs);
359  return Impl.GetValue(BB);
360 }
i
i
Definition: README.txt:29
llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetUndefVal
static Register GetUndefVal(MachineBasicBlock *BB, MachineSSAUpdater *Updater)
GetUndefVal - Create an IMPLICIT_DEF instruction with a new register.
Definition: MachineSSAUpdater.cpp:290
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
MachineInstr.h
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
MachineSSAUpdater.h
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_end
static PHI_iterator PHI_end(PhiT *PHI)
Definition: MachineSSAUpdater.cpp:277
llvm::SSAUpdaterTraits< MachineSSAUpdater >::BlkSucc_end
static BlkSucc_iterator BlkSucc_end(BlkT *BB)
Definition: MachineSSAUpdater.cpp:250
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
ErrorHandling.h
MachineBasicBlock.h
llvm::MachineInstr::isConstantValuePHI
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
Definition: MachineInstr.cpp:1444
DenseMap.h
TargetInstrInfo.h
llvm::DenseMapBase::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
LookForIdenticalPHI
static Register LookForIdenticalPHI(MachineBasicBlock *BB, SmallVectorImpl< std::pair< MachineBasicBlock *, Register >> &PredValues)
Definition: MachineSSAUpdater.cpp:86
llvm::SSAUpdaterTraits< MachineSSAUpdater >::BlkSucc_iterator
MachineBasicBlock::succ_iterator BlkSucc_iterator
Definition: MachineSSAUpdater.cpp:247
llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_iterator::operator!=
bool operator!=(const PHI_iterator &x) const
Definition: MachineSSAUpdater.cpp:266
llvm::SSAUpdaterTraits< MachineSSAUpdater >::FindPredecessorBlocks
static void FindPredecessorBlocks(MachineBasicBlock *BB, SmallVectorImpl< MachineBasicBlock * > *Preds)
FindPredecessorBlocks - Put the predecessors of BB into the Preds vector.
Definition: MachineSSAUpdater.cpp:283
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
findCorrespondingPred
static MachineBasicBlock * findCorrespondingPred(const MachineInstr *MI, MachineOperand *U)
Definition: MachineSSAUpdater.cpp:212
llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_iterator::getIncomingBlock
MachineBasicBlock * getIncomingBlock()
Definition: MachineSSAUpdater.cpp:270
llvm::SSAUpdaterTraits< MachineSSAUpdater >::CreateEmptyPHI
static Register CreateEmptyPHI(MachineBasicBlock *BB, unsigned NumPreds, MachineSSAUpdater *Updater)
CreateEmptyPHI - Create a PHI instruction that defines a new register.
Definition: MachineSSAUpdater.cpp:302
MachineRegisterInfo.h
llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_iterator::operator++
PHI_iterator & operator++()
Definition: MachineSSAUpdater.cpp:264
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::SSAUpdaterTraits< MachineSSAUpdater >::InstrIsPHI
static MachineInstr * InstrIsPHI(MachineInstr *I)
InstrIsPHI - Check if an instruction is a PHI.
Definition: MachineSSAUpdater.cpp:319
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
SSAUpdaterImpl.h
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SSAUpdaterTraits< MachineSSAUpdater >::ValueIsNewPHI
static MachineInstr * ValueIsNewPHI(Register Val, MachineSSAUpdater *Updater)
ValueIsNewPHI - Like ValueIsPHI but also check if the PHI has no source operands, i....
Definition: MachineSSAUpdater.cpp:333
llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_iterator::operator==
bool operator==(const PHI_iterator &x) const
Definition: MachineSSAUpdater.cpp:265
llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetPHIValue
static Register GetPHIValue(MachineInstr *PHI)
GetPHIValue - For the specified PHI instruction, return the register that it defines.
Definition: MachineSSAUpdater.cpp:342
DebugLoc.h
llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_iterator::PHI_iterator
PHI_iterator(MachineInstr *P)
Definition: MachineSSAUpdater.cpp:259
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::MachineSSAUpdater::~MachineSSAUpdater
~MachineSSAUpdater()
Definition: MachineSSAUpdater.cpp:48
llvm::MachineBasicBlock::succ_iterator
std::vector< MachineBasicBlock * >::iterator succ_iterator
Definition: MachineBasicBlock.h:306
llvm::MachineSSAUpdater::MachineSSAUpdater
MachineSSAUpdater(MachineFunction &MF, SmallVectorImpl< MachineInstr * > *NewPHI=nullptr)
MachineSSAUpdater constructor.
Definition: MachineSSAUpdater.cpp:43
llvm::DenseMapBase::clear
void clear()
Definition: DenseMap.h:111
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap
Definition: DenseMap.h:714
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MachineSSAUpdater::HasValueForBlock
bool HasValueForBlock(MachineBasicBlock *BB) const
HasValueForBlock - Return true if the MachineSSAUpdater already has a value for the specified block.
Definition: MachineSSAUpdater.cpp:69
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::operator==
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1974
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1255
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_begin
static PHI_iterator PHI_begin(PhiT *PHI)
Definition: MachineSSAUpdater.cpp:275
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::append_range
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
Definition: STLExtras.h:1744
TargetSubtargetInfo.h
llvm::SSAUpdaterTraits< MachineSSAUpdater >::BlkSucc_begin
static BlkSucc_iterator BlkSucc_begin(BlkT *BB)
Definition: MachineSSAUpdater.cpp:249
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_iterator::getIncomingValue
unsigned getIncomingValue()
Definition: MachineSSAUpdater.cpp:268
x
TODO unsigned x
Definition: README.txt:10
llvm::MachineSSAUpdater::GetValueAtEndOfBlock
Register GetValueAtEndOfBlock(MachineBasicBlock *BB)
GetValueAtEndOfBlock - Construct SSA form, materializing a value that is live at the end of the speci...
Definition: MachineSSAUpdater.cpp:81
InsertNewDef
static MachineInstrBuilder InsertNewDef(unsigned Opcode, MachineBasicBlock *BB, MachineBasicBlock::iterator I, const TargetRegisterClass *RC, MachineRegisterInfo *MRI, const TargetInstrInfo *TII)
InsertNewDef - Insert an empty PHI or IMPLICIT_DEF instruction which define a value of the given regi...
Definition: MachineSSAUpdater.cpp:119
llvm::MachineSSAUpdater::RewriteUse
void RewriteUse(MachineOperand &U)
RewriteUse - Rewrite a use of the symbolic value.
Definition: MachineSSAUpdater.cpp:224
llvm::SSAUpdaterTraits
Definition: MachineSSAUpdater.h:28
llvm::SSAUpdaterTraits< MachineSSAUpdater >::ValueIsPHI
static MachineInstr * ValueIsPHI(Register Val, MachineSSAUpdater *Updater)
ValueIsPHI - Check if the instruction that defines the specified register is a PHI instruction.
Definition: MachineSSAUpdater.cpp:327
llvm::MachineSSAUpdater
MachineSSAUpdater - This class updates SSA form for a set of virtual registers defined in multiple bl...
Definition: MachineSSAUpdater.h:34
SmallVector.h
MachineInstrBuilder.h
llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_iterator::PHI_iterator
PHI_iterator(MachineInstr *P, bool)
Definition: MachineSSAUpdater.cpp:261
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
getAvailableVals
static AvailableValsTy & getAvailableVals(void *AV)
Definition: MachineSSAUpdater.cpp:39
llvm::SmallVectorImpl< MachineInstr * >
MachineOperand.h
llvm::SSAUpdaterTraits< MachineSSAUpdater >::AddPHIOperand
static void AddPHIOperand(MachineInstr *PHI, Register Val, MachineBasicBlock *Pred)
AddPHIOperand - Add the specified value as an operand of the PHI for the specified predecessor block.
Definition: MachineSSAUpdater.cpp:313
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MachineSSAUpdater::AddAvailableValue
void AddAvailableValue(MachineBasicBlock *BB, Register V)
AddAvailableValue - Indicate that a rewritten value is available at the end of the specified block wi...
Definition: MachineSSAUpdater.cpp:75
llvm::MachineSSAUpdater::Initialize
void Initialize(Register V)
Initialize - Reset this object to get ready for a new set of SSA updates.
Definition: MachineSSAUpdater.cpp:63
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
raw_ostream.h
llvm::MachineSSAUpdater::GetValueInMiddleOfBlock
Register GetValueInMiddleOfBlock(MachineBasicBlock *BB)
GetValueInMiddleOfBlock - Construct SSA form, materializing a value that is live in the middle of the...
Definition: MachineSSAUpdater.cpp:146
MachineFunction.h
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:677
llvm::MachineInstrBundleIterator< MachineInstr >
Debug.h
AvailableValsTy
DenseMap< MachineBasicBlock *, Register > AvailableValsTy
Definition: MachineSSAUpdater.cpp:37
llvm::SSAUpdaterImpl
Definition: SSAUpdaterImpl.h:30