LLVM  10.0.0svn
AllocationOrder.cpp
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1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements an allocation order for virtual registers.
10 //
11 // The preferred allocation order for a virtual register depends on allocation
12 // hints and target hooks. The AllocationOrder class encapsulates all of that.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AllocationOrder.h"
21 #include "llvm/Support/Debug.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "regalloc"
27 
28 // Compare VirtRegMap::getRegAllocPref().
30  const VirtRegMap &VRM,
31  const RegisterClassInfo &RegClassInfo,
32  const LiveRegMatrix *Matrix)
33  : Pos(0), HardHints(false) {
34  const MachineFunction &MF = VRM.getMachineFunction();
35  const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
36  Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
37  if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix))
38  HardHints = true;
39  rewind();
40 
41  LLVM_DEBUG({
42  if (!Hints.empty()) {
43  dbgs() << "hints:";
44  for (unsigned I = 0, E = Hints.size(); I != E; ++I)
45  dbgs() << ' ' << printReg(Hints[I], TRI);
46  dbgs() << '\n';
47  }
48  });
49 #ifndef NDEBUG
50  for (unsigned I = 0, E = Hints.size(); I != E; ++I)
51  assert(is_contained(Order, Hints[I]) &&
52  "Target hint is outside allocation order.");
53 #endif
54 }
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
void rewind()
Start over from the beginning.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned const TargetRegisterInfo * TRI
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
const TargetRegisterInfo & getTargetRegInfo() const
Definition: VirtRegMap.h:90
Live Register Matrix
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo, const LiveRegMatrix *Matrix)
Create a new AllocationOrder for VirtReg.
MachineFunction & getMachineFunction() const
Definition: VirtRegMap.h:84
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define LLVM_DEBUG(X)
Definition: Debug.h:122
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1224