LLVM 18.0.0git
AArch64TargetMachine.cpp
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1//===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
13#include "AArch64.h"
16#include "AArch64MacroFusion.h"
17#include "AArch64Subtarget.h"
22#include "llvm/ADT/STLExtras.h"
36#include "llvm/CodeGen/Passes.h"
39#include "llvm/IR/Attributes.h"
40#include "llvm/IR/Function.h"
42#include "llvm/MC/MCAsmInfo.h"
45#include "llvm/Pass.h"
53#include <memory>
54#include <optional>
55#include <string>
56
57using namespace llvm;
58
59static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
60 cl::desc("Enable the CCMP formation pass"),
61 cl::init(true), cl::Hidden);
62
63static cl::opt<bool>
64 EnableCondBrTuning("aarch64-enable-cond-br-tune",
65 cl::desc("Enable the conditional branch tuning pass"),
66 cl::init(true), cl::Hidden);
67
69 "aarch64-enable-copy-propagation",
70 cl::desc("Enable the copy propagation with AArch64 copy instr"),
71 cl::init(true), cl::Hidden);
72
73static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
74 cl::desc("Enable the machine combiner pass"),
75 cl::init(true), cl::Hidden);
76
77static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
78 cl::desc("Suppress STP for AArch64"),
79 cl::init(true), cl::Hidden);
80
82 "aarch64-enable-simd-scalar",
83 cl::desc("Enable use of AdvSIMD scalar integer instructions"),
84 cl::init(false), cl::Hidden);
85
86static cl::opt<bool>
87 EnablePromoteConstant("aarch64-enable-promote-const",
88 cl::desc("Enable the promote constant pass"),
89 cl::init(true), cl::Hidden);
90
92 "aarch64-enable-collect-loh",
93 cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
94 cl::init(true), cl::Hidden);
95
96static cl::opt<bool>
97 EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
98 cl::desc("Enable the pass that removes dead"
99 " definitons and replaces stores to"
100 " them with stores to the zero"
101 " register"),
102 cl::init(true));
103
105 "aarch64-enable-copyelim",
106 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
107 cl::Hidden);
108
109static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
110 cl::desc("Enable the load/store pair"
111 " optimization pass"),
112 cl::init(true), cl::Hidden);
113
115 "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
116 cl::desc("Run SimplifyCFG after expanding atomic operations"
117 " to make use of cmpxchg flow-based information"),
118 cl::init(true));
119
120static cl::opt<bool>
121EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
122 cl::desc("Run early if-conversion"),
123 cl::init(true));
124
125static cl::opt<bool>
126 EnableCondOpt("aarch64-enable-condopt",
127 cl::desc("Enable the condition optimizer pass"),
128 cl::init(true), cl::Hidden);
129
130static cl::opt<bool>
131 EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
132 cl::desc("Enable optimizations on complex GEPs"),
133 cl::init(false));
134
135static cl::opt<bool>
136 EnableSelectOpt("aarch64-select-opt", cl::Hidden,
137 cl::desc("Enable select to branch optimizations"),
138 cl::init(true));
139
140static cl::opt<bool>
141 BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
142 cl::desc("Relax out of range conditional branches"));
143
145 "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
146 cl::desc("Use smallest entry possible for jump tables"));
147
148// FIXME: Unify control over GlobalMerge.
150 EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
151 cl::desc("Enable the global merge pass"));
152
153static cl::opt<bool>
154 EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
155 cl::desc("Enable the loop data prefetch pass"),
156 cl::init(true));
157
159 "aarch64-enable-global-isel-at-O", cl::Hidden,
160 cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
161 cl::init(0));
162
163static cl::opt<bool>
164 EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
165 cl::desc("Enable SVE intrinsic opts"),
166 cl::init(true));
167
168static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
169 cl::init(true), cl::Hidden);
170
171static cl::opt<bool>
172 EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
173 cl::desc("Enable the AArch64 branch target pass"),
174 cl::init(true));
175
177 "aarch64-sve-vector-bits-max",
178 cl::desc("Assume SVE vector registers are at most this big, "
179 "with zero meaning no maximum size is assumed."),
180 cl::init(0), cl::Hidden);
181
183 "aarch64-sve-vector-bits-min",
184 cl::desc("Assume SVE vector registers are at least this big, "
185 "with zero meaning no minimum size is assumed."),
186 cl::init(0), cl::Hidden);
187
189
191 "aarch64-enable-gisel-ldst-prelegal",
192 cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"),
193 cl::init(true), cl::Hidden);
194
196 "aarch64-enable-gisel-ldst-postlegal",
197 cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"),
198 cl::init(false), cl::Hidden);
199
201 // Register the target.
244}
245
246//===----------------------------------------------------------------------===//
247// AArch64 Lowering public interface.
248//===----------------------------------------------------------------------===//
249static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
250 if (TT.isOSBinFormatMachO())
251 return std::make_unique<AArch64_MachoTargetObjectFile>();
252 if (TT.isOSBinFormatCOFF())
253 return std::make_unique<AArch64_COFFTargetObjectFile>();
254
255 return std::make_unique<AArch64_ELFTargetObjectFile>();
256}
257
258// Helper function to build a DataLayout string
259static std::string computeDataLayout(const Triple &TT,
261 bool LittleEndian) {
262 if (TT.isOSBinFormatMachO()) {
263 if (TT.getArch() == Triple::aarch64_32)
264 return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
265 return "e-m:o-i64:64-i128:128-n32:64-S128";
266 }
267 if (TT.isOSBinFormatCOFF())
268 return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
269 std::string Endian = LittleEndian ? "e" : "E";
270 std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
271 return Endian + "-m:e" + Ptr32 +
272 "-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
273}
274
276 if (CPU.empty() && TT.isArm64e())
277 return "apple-a12";
278 return CPU;
279}
280
282 std::optional<Reloc::Model> RM) {
283 // AArch64 Darwin and Windows are always PIC.
284 if (TT.isOSDarwin() || TT.isOSWindows())
285 return Reloc::PIC_;
286 // On ELF platforms the default static relocation model has a smart enough
287 // linker to cope with referencing external symbols defined in a shared
288 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
289 if (!RM || *RM == Reloc::DynamicNoPIC)
290 return Reloc::Static;
291 return *RM;
292}
293
294static CodeModel::Model
296 std::optional<CodeModel::Model> CM, bool JIT) {
297 if (CM) {
298 if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
299 *CM != CodeModel::Large) {
301 "Only small, tiny and large code models are allowed on AArch64");
302 } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
303 report_fatal_error("tiny code model is only supported on ELF");
304 return *CM;
305 }
306 // The default MCJIT memory managers make no guarantees about where they can
307 // find an executable page; JITed code needs to be able to refer to globals
308 // no matter how far away they are.
309 // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
310 // since with large code model LLVM generating 4 MOV instructions, and
311 // Windows doesn't support relocating these long branch (4 MOVs).
312 if (JIT && !TT.isOSWindows())
313 return CodeModel::Large;
314 return CodeModel::Small;
315}
316
317/// Create an AArch64 architecture model.
318///
320 StringRef CPU, StringRef FS,
321 const TargetOptions &Options,
322 std::optional<Reloc::Model> RM,
323 std::optional<CodeModel::Model> CM,
324 CodeGenOptLevel OL, bool JIT,
325 bool LittleEndian)
327 computeDataLayout(TT, Options.MCOptions, LittleEndian),
328 TT, computeDefaultCPU(TT, CPU), FS, Options,
330 getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
331 TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
332 initAsmInfo();
333
334 if (TT.isOSBinFormatMachO()) {
335 this->Options.TrapUnreachable = true;
336 this->Options.NoTrapAfterNoreturn = true;
337 }
338
339 if (getMCAsmInfo()->usesWindowsCFI()) {
340 // Unwinding can get confused if the last instruction in an
341 // exception-handling region (function, funclet, try block, etc.)
342 // is a call.
343 //
344 // FIXME: We could elide the trap if the next instruction would be in
345 // the same region anyway.
346 this->Options.TrapUnreachable = true;
347 }
348
349 if (this->Options.TLSSize == 0) // default
350 this->Options.TLSSize = 24;
351 if ((getCodeModel() == CodeModel::Small ||
353 this->Options.TLSSize > 32)
354 // for the small (and kernel) code model, the maximum TLS size is 4GiB
355 this->Options.TLSSize = 32;
356 else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
357 // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
358 this->Options.TLSSize = 24;
359
360 // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
361 // MachO/CodeModel::Large, which GlobalISel does not support.
362 if (static_cast<int>(getOptLevel()) <= EnableGlobalISelAtO &&
363 TT.getArch() != Triple::aarch64_32 &&
364 TT.getEnvironment() != Triple::GNUILP32 &&
365 !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
366 setGlobalISel(true);
368 }
369
370 // AArch64 supports the MachineOutliner.
371 setMachineOutliner(true);
372
373 // AArch64 supports default outlining behaviour.
375
376 // AArch64 supports the debug entry values.
378
379 // AArch64 supports fixing up the DWARF unwind information.
380 if (!getMCAsmInfo()->usesWindowsCFI())
381 setCFIFixup(true);
382}
383
385
386const AArch64Subtarget *
388 Attribute CPUAttr = F.getFnAttribute("target-cpu");
389 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
390 Attribute FSAttr = F.getFnAttribute("target-features");
391
392 StringRef CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString() : TargetCPU;
393 StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString() : CPU;
394 StringRef FS = FSAttr.isValid() ? FSAttr.getValueAsString() : TargetFS;
395
396 bool StreamingSVEMode = F.hasFnAttribute("aarch64_pstate_sm_enabled") ||
397 F.hasFnAttribute("aarch64_pstate_sm_body");
398 bool StreamingCompatibleSVEMode =
399 F.hasFnAttribute("aarch64_pstate_sm_compatible");
400
401 unsigned MinSVEVectorSize = 0;
402 unsigned MaxSVEVectorSize = 0;
403 if (F.hasFnAttribute(Attribute::VScaleRange)) {
404 ConstantRange CR = getVScaleRange(&F, 64);
405 MinSVEVectorSize = CR.getUnsignedMin().getZExtValue() * 128;
406 MaxSVEVectorSize = CR.getUnsignedMax().getZExtValue() * 128;
407 } else {
408 MinSVEVectorSize = SVEVectorBitsMinOpt;
409 MaxSVEVectorSize = SVEVectorBitsMaxOpt;
410 }
411
412 assert(MinSVEVectorSize % 128 == 0 &&
413 "SVE requires vector length in multiples of 128!");
414 assert(MaxSVEVectorSize % 128 == 0 &&
415 "SVE requires vector length in multiples of 128!");
416 assert((MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == 0) &&
417 "Minimum SVE vector size should not be larger than its maximum!");
418
419 // Sanitize user input in case of no asserts
420 if (MaxSVEVectorSize != 0) {
421 MinSVEVectorSize = std::min(MinSVEVectorSize, MaxSVEVectorSize);
422 MaxSVEVectorSize = std::max(MinSVEVectorSize, MaxSVEVectorSize);
423 }
424
426 raw_svector_ostream(Key) << "SVEMin" << MinSVEVectorSize << "SVEMax"
427 << MaxSVEVectorSize
428 << "StreamingSVEMode=" << StreamingSVEMode
429 << "StreamingCompatibleSVEMode="
430 << StreamingCompatibleSVEMode << CPU << TuneCPU
431 << FS;
432
433 auto &I = SubtargetMap[Key];
434 if (!I) {
435 // This needs to be done before we create a new subtarget since any
436 // creation will depend on the TM and the code generation flags on the
437 // function that reside in TargetOptions.
439 I = std::make_unique<AArch64Subtarget>(
440 TargetTriple, CPU, TuneCPU, FS, *this, isLittle, MinSVEVectorSize,
441 MaxSVEVectorSize, StreamingSVEMode, StreamingCompatibleSVEMode);
442 }
443
444 assert((!StreamingSVEMode || I->hasSME()) &&
445 "Expected SME to be available");
446
447 return I.get();
448}
449
450void AArch64leTargetMachine::anchor() { }
451
453 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
454 const TargetOptions &Options, std::optional<Reloc::Model> RM,
455 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
456 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
457
458void AArch64beTargetMachine::anchor() { }
459
461 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
462 const TargetOptions &Options, std::optional<Reloc::Model> RM,
463 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
464 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
465
466namespace {
467
468/// AArch64 Code Generator Pass Configuration Options.
469class AArch64PassConfig : public TargetPassConfig {
470public:
471 AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
472 : TargetPassConfig(TM, PM) {
473 if (TM.getOptLevel() != CodeGenOptLevel::None)
474 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
475 }
476
477 AArch64TargetMachine &getAArch64TargetMachine() const {
478 return getTM<AArch64TargetMachine>();
479 }
480
482 createMachineScheduler(MachineSchedContext *C) const override {
483 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
485 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
486 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
487 if (ST.hasFusion())
488 DAG->addMutation(createAArch64MacroFusionDAGMutation());
489 return DAG;
490 }
491
493 createPostMachineScheduler(MachineSchedContext *C) const override {
494 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
495 ScheduleDAGMI *DAG =
496 new ScheduleDAGMI(C, std::make_unique<AArch64PostRASchedStrategy>(C),
497 /* RemoveKillFlags=*/true);
498 if (ST.hasFusion()) {
499 // Run the Macro Fusion after RA again since literals are expanded from
500 // pseudos then (v. addPreSched2()).
501 DAG->addMutation(createAArch64MacroFusionDAGMutation());
502 return DAG;
503 }
504
505 return DAG;
506 }
507
508 void addIRPasses() override;
509 bool addPreISel() override;
510 void addCodeGenPrepare() override;
511 bool addInstSelector() override;
512 bool addIRTranslator() override;
513 void addPreLegalizeMachineIR() override;
514 bool addLegalizeMachineIR() override;
515 void addPreRegBankSelect() override;
516 bool addRegBankSelect() override;
517 bool addGlobalInstructionSelect() override;
518 void addMachineSSAOptimization() override;
519 bool addILPOpts() override;
520 void addPreRegAlloc() override;
521 void addPostRegAlloc() override;
522 void addPreSched2() override;
523 void addPreEmitPass() override;
524 void addPostBBSections() override;
525 void addPreEmitPass2() override;
526
527 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
528};
529
530} // end anonymous namespace
531
534 return TargetTransformInfo(AArch64TTIImpl(this, F));
535}
536
538 return new AArch64PassConfig(*this, PM);
539}
540
541std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
542 return getStandardCSEConfigForOpt(TM->getOptLevel());
543}
544
545void AArch64PassConfig::addIRPasses() {
546 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
547 // ourselves.
548 addPass(createAtomicExpandPass());
549
550 // Expand any SVE vector library calls that we can't code generate directly.
552 TM->getOptLevel() == CodeGenOptLevel::Aggressive)
554
555 // Cmpxchg instructions are often used with a subsequent comparison to
556 // determine whether it succeeded. We can exploit existing control-flow in
557 // ldrex/strex loops to simplify this, but it needs tidying up.
558 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAtomicTidy)
560 .forwardSwitchCondToPhi(true)
561 .convertSwitchRangeToICmp(true)
562 .convertSwitchToLookupTable(true)
563 .needCanonicalLoops(false)
564 .hoistCommonInsts(true)
565 .sinkCommonInsts(true)));
566
567 // Run LoopDataPrefetch
568 //
569 // Run this before LSR to remove the multiplies involved in computing the
570 // pointer values N iterations ahead.
571 if (TM->getOptLevel() != CodeGenOptLevel::None) {
576 }
577
578 if (TM->getOptLevel() == CodeGenOptLevel::Aggressive && EnableGEPOpt) {
579 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
580 // and lower a GEP with multiple indices to either arithmetic operations or
581 // multiple GEPs with single index.
583 // Call EarlyCSE pass to find and remove subexpressions in the lowered
584 // result.
585 addPass(createEarlyCSEPass());
586 // Do loop invariant code motion in case part of the lowered result is
587 // invariant.
588 addPass(createLICMPass());
589 }
590
592
593 if (getOptLevel() == CodeGenOptLevel::Aggressive && EnableSelectOpt)
594 addPass(createSelectOptimizePass());
595
598 /*IsOptNone=*/TM->getOptLevel() == CodeGenOptLevel::None));
599
600 // Match complex arithmetic patterns
601 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
603
604 // Match interleaved memory accesses to ldN/stN intrinsics.
605 if (TM->getOptLevel() != CodeGenOptLevel::None) {
608 }
609
610 // Expand any functions marked with SME attributes which require special
611 // changes for the calling convention or that require the lazy-saving
612 // mechanism specified in the SME ABI.
613 addPass(createSMEABIPass());
614
615 // Add Control Flow Guard checks.
616 if (TM->getTargetTriple().isOSWindows())
617 addPass(createCFGuardCheckPass());
618
619 if (TM->Options.JMCInstrument)
620 addPass(createJMCInstrumenterPass());
621}
622
623// Pass Pipeline Configuration
624bool AArch64PassConfig::addPreISel() {
625 // Run promote constant before global merge, so that the promoted constants
626 // get a chance to be merged
627 if (TM->getOptLevel() != CodeGenOptLevel::None && EnablePromoteConstant)
629 // FIXME: On AArch64, this depends on the type.
630 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
631 // and the offset has to be a multiple of the related size in bytes.
632 if ((TM->getOptLevel() != CodeGenOptLevel::None &&
635 bool OnlyOptimizeForSize =
636 (TM->getOptLevel() < CodeGenOptLevel::Aggressive) &&
638
639 // Merging of extern globals is enabled by default on non-Mach-O as we
640 // expect it to be generally either beneficial or harmless. On Mach-O it
641 // is disabled as we emit the .subsections_via_symbols directive which
642 // means that merging extern globals is not safe.
643 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
644
645 // FIXME: extern global merging is only enabled when we optimise for size
646 // because there are some regressions with it also enabled for performance.
647 if (!OnlyOptimizeForSize)
648 MergeExternalByDefault = false;
649
650 addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
651 MergeExternalByDefault));
652 }
653
654 return false;
655}
656
657void AArch64PassConfig::addCodeGenPrepare() {
658 if (getOptLevel() != CodeGenOptLevel::None)
661}
662
663bool AArch64PassConfig::addInstSelector() {
664 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
665
666 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
667 // references to _TLS_MODULE_BASE_ as possible.
668 if (TM->getTargetTriple().isOSBinFormatELF() &&
669 getOptLevel() != CodeGenOptLevel::None)
671
672 return false;
673}
674
675bool AArch64PassConfig::addIRTranslator() {
676 addPass(new IRTranslator(getOptLevel()));
677 return false;
678}
679
680void AArch64PassConfig::addPreLegalizeMachineIR() {
681 if (getOptLevel() == CodeGenOptLevel::None) {
683 addPass(new Localizer());
684 } else {
686 addPass(new Localizer());
688 addPass(new LoadStoreOpt());
689 }
690}
691
692bool AArch64PassConfig::addLegalizeMachineIR() {
693 addPass(new Legalizer());
694 return false;
695}
696
697void AArch64PassConfig::addPreRegBankSelect() {
698 bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;
699 if (!IsOptNone) {
700 addPass(createAArch64PostLegalizerCombiner(IsOptNone));
702 addPass(new LoadStoreOpt());
703 }
705}
706
707bool AArch64PassConfig::addRegBankSelect() {
708 addPass(new RegBankSelect());
709 return false;
710}
711
712bool AArch64PassConfig::addGlobalInstructionSelect() {
713 addPass(new InstructionSelect(getOptLevel()));
714 if (getOptLevel() != CodeGenOptLevel::None)
716 return false;
717}
718
719void AArch64PassConfig::addMachineSSAOptimization() {
720 // Run default MachineSSAOptimization first.
722
723 if (TM->getOptLevel() != CodeGenOptLevel::None)
725}
726
727bool AArch64PassConfig::addILPOpts() {
728 if (EnableCondOpt)
730 if (EnableCCMP)
732 if (EnableMCR)
733 addPass(&MachineCombinerID);
735 addPass(createAArch64CondBrTuning());
737 addPass(&EarlyIfConverterID);
741 if (TM->getOptLevel() != CodeGenOptLevel::None)
743 return true;
744}
745
746void AArch64PassConfig::addPreRegAlloc() {
747 // Change dead register definitions to refer to the zero register.
748 if (TM->getOptLevel() != CodeGenOptLevel::None &&
751
752 // Use AdvSIMD scalar instructions whenever profitable.
753 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAdvSIMDScalar) {
755 // The AdvSIMD pass may produce copies that can be rewritten to
756 // be register coalescer friendly.
757 addPass(&PeepholeOptimizerID);
758 }
759}
760
761void AArch64PassConfig::addPostRegAlloc() {
762 // Remove redundant copy instructions.
763 if (TM->getOptLevel() != CodeGenOptLevel::None &&
766
767 if (TM->getOptLevel() != CodeGenOptLevel::None && usingDefaultRegAlloc())
768 // Improve performance for some FP/SIMD code for A57.
770}
771
772void AArch64PassConfig::addPreSched2() {
773 // Lower homogeneous frame instructions
776 // Expand some pseudo instructions to allow proper scheduling.
778 // Use load/store pair instructions when possible.
779 if (TM->getOptLevel() != CodeGenOptLevel::None) {
782 }
783 // Emit KCFI checks for indirect calls.
784 addPass(createKCFIPass());
785
786 // The AArch64SpeculationHardeningPass destroys dominator tree and natural
787 // loop info, which is needed for the FalkorHWPFFixPass and also later on.
788 // Therefore, run the AArch64SpeculationHardeningPass before the
789 // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
790 // info.
792
795
796 if (TM->getOptLevel() != CodeGenOptLevel::None) {
798 addPass(createFalkorHWPFFixPass());
799 }
800}
801
802void AArch64PassConfig::addPreEmitPass() {
803 // Machine Block Placement might have created new opportunities when run
804 // at O3, where the Tail Duplication Threshold is set to 4 instructions.
805 // Run the load/store optimizer once more.
806 if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive && EnableLoadStoreOpt)
808
809 if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive &&
812
813 addPass(createAArch64A53Fix835769());
814
815 if (TM->getTargetTriple().isOSWindows()) {
816 // Identify valid longjmp targets for Windows Control Flow Guard.
817 addPass(createCFGuardLongjmpPass());
818 // Identify valid eh continuation targets for Windows EHCont Guard.
820 }
821
822 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableCollectLOH &&
823 TM->getTargetTriple().isOSBinFormatMachO())
825}
826
827void AArch64PassConfig::addPostBBSections() {
831 // Relax conditional branch instructions if they're otherwise out of
832 // range of their destination.
833 if (BranchRelaxation)
834 addPass(&BranchRelaxationPassID);
835
836 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableCompressJumpTables)
838}
839
840void AArch64PassConfig::addPreEmitPass2() {
841 // SVE bundles move prefixes with destructive operations. BLR_RVMARKER pseudo
842 // instructions are lowered to bundles as well.
843 addPass(createUnpackMachineBundles(nullptr));
844}
845
847 BumpPtrAllocator &Allocator, const Function &F,
848 const TargetSubtargetInfo *STI) const {
849 return AArch64FunctionInfo::create<AArch64FunctionInfo>(
850 Allocator, F, static_cast<const AArch64Subtarget *>(STI));
851}
852
855 return new yaml::AArch64FunctionInfo();
856}
857
860 const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
861 return new yaml::AArch64FunctionInfo(*MFI);
862}
863
866 SMDiagnostic &Error, SMRange &SourceRange) const {
867 const auto &YamlMFI = static_cast<const yaml::AArch64FunctionInfo &>(MFI);
868 MachineFunction &MF = PFS.MF;
869 MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
870 return false;
871}
cl::opt< bool > EnableHomogeneousPrologEpilog("homogeneous-prolog-epilog", cl::Hidden, cl::desc("Emit homogeneous prologue and epilogue for the size " "optimization (default = off)"))
static cl::opt< bool > EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden, cl::desc("Enable the AArch64 branch target pass"), cl::init(true))
static cl::opt< bool > EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden, cl::desc("Enable SVE intrinsic opts"), cl::init(true))
static cl::opt< bool > EnableAArch64CopyPropagation("aarch64-enable-copy-propagation", cl::desc("Enable the copy propagation with AArch64 copy instr"), cl::init(true), cl::Hidden)
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
static cl::opt< bool > EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableCondBrTuning("aarch64-enable-cond-br-tune", cl::desc("Enable the conditional branch tuning pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))
static cl::opt< bool > EnableSelectOpt("aarch64-select-opt", cl::Hidden, cl::desc("Enable select to branch optimizations"), cl::init(true))
static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden)
cl::opt< bool > EnableHomogeneousPrologEpilog
static cl::opt< bool > EnableGISelLoadStoreOptPostLegal("aarch64-enable-gisel-ldst-postlegal", cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"), cl::init(false), cl::Hidden)
static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU)
static cl::opt< unsigned > SVEVectorBitsMinOpt("aarch64-sve-vector-bits-min", cl::desc("Assume SVE vector registers are at least this big, " "with zero meaning no minimum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< bool > EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
static cl::opt< bool > EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to the zero" " register"), cl::init(true))
static cl::opt< bool > EnableStPairSuppress("aarch64-enable-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden)
static CodeModel::Model getEffectiveAArch64CodeModel(const Triple &TT, std::optional< CodeModel::Model > CM, bool JIT)
static cl::opt< bool > EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableCollectLOH("aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableGISelLoadStoreOptPreLegal("aarch64-enable-gisel-ldst-prelegal", cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
static cl::opt< bool > EnableAdvSIMDScalar("aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden)
static cl::opt< int > EnableGlobalISelAtO("aarch64-enable-global-isel-at-O", cl::Hidden, cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"), cl::init(0))
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target()
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional< Reloc::Model > RM)
static cl::opt< bool > EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix", cl::init(true), cl::Hidden)
static cl::opt< unsigned > SVEVectorBitsMaxOpt("aarch64-sve-vector-bits-max", cl::desc("Assume SVE vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< bool > EnableCompressJumpTables("aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true), cl::desc("Use smallest entry possible for jump tables"))
static cl::opt< bool > EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)
This file a TargetTransformInfo::Concept conforming object specific to the AArch64 target machine.
This file contains the simple types necessary to represent the attributes associated with functions a...
basic Basic Alias true
Contains definition of the base CFIFixup pass.
Provides analysis for continuously CSEing during GISel passes.
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
Basic Register Allocator
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
endianness Endian
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
const AArch64Subtarget * getSubtargetImpl() const =delete
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT, bool IsLittleEndian)
Create an AArch64 architecture model.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1485
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:318
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:184
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
This class represents a range of values.
Definition: ConstantRange.h:47
APInt getUnsignedMin() const
Return the smallest unsigned value contained in the ConstantRange.
APInt getUnsignedMax() const
Return the largest unsigned value contained in the ConstantRange.
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:43
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
Represents a range in source code.
Definition: SMLoc.h:48
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:97
void setMachineOutliner(bool Enable)
void setCFIFixup(bool Enable)
void setSupportsDefaultOutlining(bool Enable)
void setGlobalISelAbort(GlobalISelAbortMode Mode)
std::string TargetFS
Definition: TargetMachine.h:99
std::string TargetCPU
Definition: TargetMachine.h:98
std::unique_ptr< const MCSubtargetInfo > STI
void setGlobalISel(bool Enable)
CodeModel::Model getCodeModel() const
Returns the code model.
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned TLSSize
Bit size of immediate TLS offsets (0 == use the default).
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Target-Independent Code Generator Pass Configuration Options.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
@ aarch64_32
Definition: Triple.h:53
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:672
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ DynamicNoPIC
Definition: CodeGen.h:25
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createAArch64PreLegalizerCombiner()
void initializeLDTLSCleanupPass(PassRegistry &)
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
FunctionPass * createSMEABIPass()
Definition: SMEABIPass.cpp:53
void initializeAArch64A57FPLoadBalancingPass(PassRegistry &)
FunctionPass * createAArch64PostSelectOptimize()
void initializeAArch64SpeculationHardeningPass(PassRegistry &)
void initializeAArch64PostLegalizerLoweringPass(PassRegistry &)
FunctionPass * createAArch64RedundantCopyEliminationPass()
FunctionPass * createAArch64StackTaggingPreRAPass()
FunctionPass * createTypePromotionLegacyPass()
Create IR Type Promotion pass.
void initializeAArch64PostLegalizerCombinerPass(PassRegistry &)
FunctionPass * createAArch64MIPeepholeOptPass()
void initializeAArch64AdvSIMDScalarPass(PassRegistry &)
FunctionPass * createSelectOptimizePass()
This pass converts conditional moves to conditional jumps when profitable.
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
void initializeAArch64GlobalsTaggingPass(PassRegistry &)
void initializeAArch64PromoteConstantPass(PassRegistry &)
FunctionPass * createFalkorMarkStridedAccessesPass()
Target & getTheAArch64beTarget()
FunctionPass * createAArch64PointerAuthPass()
FunctionPass * createFalkorHWPFFixPass()
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createAArch64O0PreLegalizerCombiner()
FunctionPass * createAArch64A57FPLoadBalancing()
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
FunctionPass * createAArch64CondBrTuning()
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)
Definition: CSEInfo.cpp:79
void initializeSMEABIPass(PassRegistry &)
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Pass * createLICMPass()
Definition: LICM.cpp:370
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Target & getTheAArch64leTarget()
FunctionPass * createAArch64DeadRegisterDefinitions()
FunctionPass * createAArch64PostLegalizerLowering()
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
FunctionPass * createAArch64IndirectThunks()
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
FunctionPass * createAArch64CompressJumpTablesPass()
Target & getTheAArch64_32Target()
FunctionPass * createAArch64ConditionalCompares()
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry &)
void initializeAArch64ExpandPseudoPass(PassRegistry &)
void initializeAArch64DAGToDAGISelPass(PassRegistry &)
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
void initializeAArch64StackTaggingPass(PassRegistry &)
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
Definition: KCFI.cpp:61
std::unique_ptr< ScheduleDAGMutation > createAArch64MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAArch64MacroFusionDAGMutation()); to AArch64PassConf...
FunctionPass * createComplexDeinterleavingPass(const TargetMachine *TM)
This pass implements generation of target-specific intrinsics to support handling of complex number a...
ModulePass * createAArch64GlobalsTaggingPass()
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createAArch64SIMDInstrOptPass()
Returns an instance of the high cost ASIMD instruction replacement optimization pass.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
FunctionPass * createAArch64StorePairSuppressPass()
FunctionPass * createAArch64ConditionOptimizerPass()
ModulePass * createSVEIntrinsicOptsPass()
void initializeAArch64CompressJumpTablesPass(PassRegistry &)
void initializeAArch64SLSHardeningPass(PassRegistry &)
FunctionPass * createAArch64CollectLOHPass()
ConstantRange getVScaleRange(const Function *F, unsigned BitWidth)
Determine the possible constant range of vscale with the given bit width, based on the vscale_range f...
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
FunctionPass * createAArch64LoadStoreOptimizationPass()
createAArch64LoadStoreOptimizationPass - returns an instance of the load / store optimization pass.
void initializeAArch64StackTaggingPreRAPass(PassRegistry &)
void initializeAArch64PreLegalizerCombinerPass(PassRegistry &)
Target & getTheARM64_32Target()
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
FunctionPass * createAArch64PostLegalizerCombiner(bool IsOptNone)
void initializeAArch64StorePairSuppressPass(PassRegistry &)
void initializeAArch64LowerHomogeneousPrologEpilogPass(PassRegistry &)
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOptLevel OptLevel)
createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG,...
void initializeAArch64MIPeepholeOptPass(PassRegistry &)
FunctionPass * createAArch64SLSHardeningPass()
FunctionPass * createAArch64BranchTargetsPass()
Target & getTheARM64Target()
void initializeFalkorHWPFFixPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
void initializeKCFIPass(PassRegistry &)
void initializeAArch64BranchTargetsPass(PassRegistry &)
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:306
void initializeAArch64A53Fix835769Pass(PassRegistry &)
ModulePass * createAArch64LowerHomogeneousPrologEpilogPass()
void initializeAArch64LoadStoreOptPass(PassRegistry &)
void initializeAArch64SIMDInstrOptPass(PassRegistry &)
void initializeAArch64PostSelectOptimizePass(PassRegistry &)
void initializeAArch64CollectLOHPass(PassRegistry &)
FunctionPass * createAArch64StackTaggingPass(bool IsOptNone)
void initializeAArch64O0PreLegalizerCombinerPass(PassRegistry &)
void initializeAArch64ConditionOptimizerPass(PassRegistry &)
void initializeAArch64ConditionalComparesPass(PassRegistry &)
FunctionPass * createAArch64CleanupLocalDynamicTLSPass()
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
ModulePass * createAArch64PromoteConstantPass()
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1932
MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
FunctionPass * createAArch64AdvSIMDScalar()
FunctionPass * createAArch64SpeculationHardeningPass()
Returns an instance of the pseudo instruction expansion pass.
void initializeSVEIntrinsicOptsPass(PassRegistry &)
void initializeAArch64PointerAuthPass(PassRegistry &)
void initializeAArch64RedundantCopyEliminationPass(PassRegistry &)
FunctionPass * createInterleavedLoadCombinePass()
InterleavedLoadCombines Pass - This pass identifies interleaved loads and combines them into wide loa...
FunctionPass * createAArch64A53Fix835769()
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.