LLVM  15.0.0git
AArch64TargetMachine.cpp
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1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
16 #include "AArch64MacroFusion.h"
17 #include "AArch64Subtarget.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/Triple.h"
25 #include "llvm/CodeGen/CFIFixup.h"
36 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/InitializePasses.h"
42 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/TargetRegistry.h"
45 #include "llvm/Pass.h"
46 #include "llvm/Support/CodeGen.h"
51 #include "llvm/Transforms/Scalar.h"
52 #include <memory>
53 #include <string>
54 
55 using namespace llvm;
56 
57 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
58  cl::desc("Enable the CCMP formation pass"),
59  cl::init(true), cl::Hidden);
60 
61 static cl::opt<bool>
62  EnableCondBrTuning("aarch64-enable-cond-br-tune",
63  cl::desc("Enable the conditional branch tuning pass"),
64  cl::init(true), cl::Hidden);
65 
67  "aarch64-enable-copy-propagation",
68  cl::desc("Enable the copy propagation with AArch64 copy instr"),
69  cl::init(true), cl::Hidden);
70 
71 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
72  cl::desc("Enable the machine combiner pass"),
73  cl::init(true), cl::Hidden);
74 
75 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
76  cl::desc("Suppress STP for AArch64"),
77  cl::init(true), cl::Hidden);
78 
80  "aarch64-enable-simd-scalar",
81  cl::desc("Enable use of AdvSIMD scalar integer instructions"),
82  cl::init(false), cl::Hidden);
83 
84 static cl::opt<bool>
85  EnablePromoteConstant("aarch64-enable-promote-const",
86  cl::desc("Enable the promote constant pass"),
87  cl::init(true), cl::Hidden);
88 
90  "aarch64-enable-collect-loh",
91  cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
92  cl::init(true), cl::Hidden);
93 
94 static cl::opt<bool>
95  EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
96  cl::desc("Enable the pass that removes dead"
97  " definitons and replaces stores to"
98  " them with stores to the zero"
99  " register"),
100  cl::init(true));
101 
103  "aarch64-enable-copyelim",
104  cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
105  cl::Hidden);
106 
107 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
108  cl::desc("Enable the load/store pair"
109  " optimization pass"),
110  cl::init(true), cl::Hidden);
111 
113  "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
114  cl::desc("Run SimplifyCFG after expanding atomic operations"
115  " to make use of cmpxchg flow-based information"),
116  cl::init(true));
117 
118 static cl::opt<bool>
119 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
120  cl::desc("Run early if-conversion"),
121  cl::init(true));
122 
123 static cl::opt<bool>
124  EnableCondOpt("aarch64-enable-condopt",
125  cl::desc("Enable the condition optimizer pass"),
126  cl::init(true), cl::Hidden);
127 
128 static cl::opt<bool>
129  EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
130  cl::desc("Enable optimizations on complex GEPs"),
131  cl::init(false));
132 
133 static cl::opt<bool>
134  BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
135  cl::desc("Relax out of range conditional branches"));
136 
138  "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
139  cl::desc("Use smallest entry possible for jump tables"));
140 
141 // FIXME: Unify control over GlobalMerge.
143  EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
144  cl::desc("Enable the global merge pass"));
145 
146 static cl::opt<bool>
147  EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
148  cl::desc("Enable the loop data prefetch pass"),
149  cl::init(true));
150 
152  "aarch64-enable-global-isel-at-O", cl::Hidden,
153  cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
154  cl::init(0));
155 
156 static cl::opt<bool>
157  EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
158  cl::desc("Enable SVE intrinsic opts"),
159  cl::init(true));
160 
161 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
162  cl::init(true), cl::Hidden);
163 
164 static cl::opt<bool>
165  EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
166  cl::desc("Enable the AArch64 branch target pass"),
167  cl::init(true));
168 
170  "aarch64-sve-vector-bits-max",
171  cl::desc("Assume SVE vector registers are at most this big, "
172  "with zero meaning no maximum size is assumed."),
173  cl::init(0), cl::Hidden);
174 
176  "aarch64-sve-vector-bits-min",
177  cl::desc("Assume SVE vector registers are at least this big, "
178  "with zero meaning no minimum size is assumed."),
179  cl::init(0), cl::Hidden);
180 
182 
184  "aarch64-enable-gisel-ldst-prelegal",
185  cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"),
186  cl::init(true), cl::Hidden);
187 
189  "aarch64-enable-gisel-ldst-postlegal",
190  cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"),
191  cl::init(false), cl::Hidden);
192 
194  // Register the target.
200  auto PR = PassRegistry::getPassRegistry();
232 }
233 
234 //===----------------------------------------------------------------------===//
235 // AArch64 Lowering public interface.
236 //===----------------------------------------------------------------------===//
237 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
238  if (TT.isOSBinFormatMachO())
239  return std::make_unique<AArch64_MachoTargetObjectFile>();
240  if (TT.isOSBinFormatCOFF())
241  return std::make_unique<AArch64_COFFTargetObjectFile>();
242 
243  return std::make_unique<AArch64_ELFTargetObjectFile>();
244 }
245 
246 // Helper function to build a DataLayout string
247 static std::string computeDataLayout(const Triple &TT,
248  const MCTargetOptions &Options,
249  bool LittleEndian) {
250  if (TT.isOSBinFormatMachO()) {
251  if (TT.getArch() == Triple::aarch64_32)
252  return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
253  return "e-m:o-i64:64-i128:128-n32:64-S128";
254  }
255  if (TT.isOSBinFormatCOFF())
256  return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
257  std::string Endian = LittleEndian ? "e" : "E";
258  std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
259  return Endian + "-m:e" + Ptr32 +
260  "-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
261 }
262 
263 static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {
264  if (CPU.empty() && TT.isArm64e())
265  return "apple-a12";
266  return CPU;
267 }
268 
271  // AArch64 Darwin and Windows are always PIC.
272  if (TT.isOSDarwin() || TT.isOSWindows())
273  return Reloc::PIC_;
274  // On ELF platforms the default static relocation model has a smart enough
275  // linker to cope with referencing external symbols defined in a shared
276  // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
277  if (!RM || *RM == Reloc::DynamicNoPIC)
278  return Reloc::Static;
279  return *RM;
280 }
281 
282 static CodeModel::Model
284  bool JIT) {
285  if (CM) {
286  if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
287  *CM != CodeModel::Large) {
289  "Only small, tiny and large code models are allowed on AArch64");
290  } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
291  report_fatal_error("tiny code model is only supported on ELF");
292  return *CM;
293  }
294  // The default MCJIT memory managers make no guarantees about where they can
295  // find an executable page; JITed code needs to be able to refer to globals
296  // no matter how far away they are.
297  // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
298  // since with large code model LLVM generating 4 MOV instructions, and
299  // Windows doesn't support relocating these long branch (4 MOVs).
300  if (JIT && !TT.isOSWindows())
301  return CodeModel::Large;
302  return CodeModel::Small;
303 }
304 
305 /// Create an AArch64 architecture model.
306 ///
308  StringRef CPU, StringRef FS,
309  const TargetOptions &Options,
312  CodeGenOpt::Level OL, bool JIT,
313  bool LittleEndian)
315  computeDataLayout(TT, Options.MCOptions, LittleEndian),
316  TT, computeDefaultCPU(TT, CPU), FS, Options,
318  getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
319  TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
320  initAsmInfo();
321 
322  if (TT.isOSBinFormatMachO()) {
323  this->Options.TrapUnreachable = true;
324  this->Options.NoTrapAfterNoreturn = true;
325  }
326 
327  if (getMCAsmInfo()->usesWindowsCFI()) {
328  // Unwinding can get confused if the last instruction in an
329  // exception-handling region (function, funclet, try block, etc.)
330  // is a call.
331  //
332  // FIXME: We could elide the trap if the next instruction would be in
333  // the same region anyway.
334  this->Options.TrapUnreachable = true;
335  }
336 
337  if (this->Options.TLSSize == 0) // default
338  this->Options.TLSSize = 24;
339  if ((getCodeModel() == CodeModel::Small ||
341  this->Options.TLSSize > 32)
342  // for the small (and kernel) code model, the maximum TLS size is 4GiB
343  this->Options.TLSSize = 32;
344  else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
345  // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
346  this->Options.TLSSize = 24;
347 
348  // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
349  // MachO/CodeModel::Large, which GlobalISel does not support.
350  if (getOptLevel() <= EnableGlobalISelAtO &&
351  TT.getArch() != Triple::aarch64_32 &&
352  TT.getEnvironment() != Triple::GNUILP32 &&
353  !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
354  setGlobalISel(true);
356  }
357 
358  // AArch64 supports the MachineOutliner.
359  setMachineOutliner(true);
360 
361  // AArch64 supports default outlining behaviour.
363 
364  // AArch64 supports the debug entry values.
366 
367  // AArch64 supports fixing up the DWARF unwind information.
368  if (!getMCAsmInfo()->usesWindowsCFI())
369  setCFIFixup(true);
370 }
371 
373 
374 const AArch64Subtarget *
376  Attribute CPUAttr = F.getFnAttribute("target-cpu");
377  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
378  Attribute FSAttr = F.getFnAttribute("target-features");
379 
380  std::string CPU =
381  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
382  std::string TuneCPU =
383  TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
384  std::string FS =
385  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
386 
388 
389  unsigned MinSVEVectorSize = 0;
390  unsigned MaxSVEVectorSize = 0;
391  Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
392  if (VScaleRangeAttr.isValid()) {
393  Optional<unsigned> VScaleMax = VScaleRangeAttr.getVScaleRangeMax();
394  MinSVEVectorSize = VScaleRangeAttr.getVScaleRangeMin() * 128;
395  MaxSVEVectorSize = VScaleMax ? *VScaleMax * 128 : 0;
396  } else {
397  MinSVEVectorSize = SVEVectorBitsMinOpt;
398  MaxSVEVectorSize = SVEVectorBitsMaxOpt;
399  }
400 
401  assert(MinSVEVectorSize % 128 == 0 &&
402  "SVE requires vector length in multiples of 128!");
403  assert(MaxSVEVectorSize % 128 == 0 &&
404  "SVE requires vector length in multiples of 128!");
405  assert((MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == 0) &&
406  "Minimum SVE vector size should not be larger than its maximum!");
407 
408  // Sanitize user input in case of no asserts
409  if (MaxSVEVectorSize == 0)
410  MinSVEVectorSize = (MinSVEVectorSize / 128) * 128;
411  else {
412  MinSVEVectorSize =
413  (std::min(MinSVEVectorSize, MaxSVEVectorSize) / 128) * 128;
414  MaxSVEVectorSize =
415  (std::max(MinSVEVectorSize, MaxSVEVectorSize) / 128) * 128;
416  }
417 
418  Key += "SVEMin";
419  Key += std::to_string(MinSVEVectorSize);
420  Key += "SVEMax";
421  Key += std::to_string(MaxSVEVectorSize);
422  Key += CPU;
423  Key += TuneCPU;
424  Key += FS;
425 
426  auto &I = SubtargetMap[Key];
427  if (!I) {
428  // This needs to be done before we create a new subtarget since any
429  // creation will depend on the TM and the code generation flags on the
430  // function that reside in TargetOptions.
432  I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, TuneCPU, FS,
433  *this, isLittle, MinSVEVectorSize,
434  MaxSVEVectorSize);
435  }
436  return I.get();
437 }
438 
439 void AArch64leTargetMachine::anchor() { }
440 
442  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
445  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
446 
447 void AArch64beTargetMachine::anchor() { }
448 
450  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
453  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
454 
455 namespace {
456 
457 /// AArch64 Code Generator Pass Configuration Options.
458 class AArch64PassConfig : public TargetPassConfig {
459 public:
460  AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
461  : TargetPassConfig(TM, PM) {
462  if (TM.getOptLevel() != CodeGenOpt::None)
463  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
464  }
465 
466  AArch64TargetMachine &getAArch64TargetMachine() const {
467  return getTM<AArch64TargetMachine>();
468  }
469 
471  createMachineScheduler(MachineSchedContext *C) const override {
472  const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
474  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
475  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
476  if (ST.hasFusion())
477  DAG->addMutation(createAArch64MacroFusionDAGMutation());
478  return DAG;
479  }
480 
482  createPostMachineScheduler(MachineSchedContext *C) const override {
483  const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
484  ScheduleDAGMI *DAG =
485  new ScheduleDAGMI(C, std::make_unique<AArch64PostRASchedStrategy>(C),
486  /* RemoveKillFlags=*/true);
487  if (ST.hasFusion()) {
488  // Run the Macro Fusion after RA again since literals are expanded from
489  // pseudos then (v. addPreSched2()).
490  DAG->addMutation(createAArch64MacroFusionDAGMutation());
491  return DAG;
492  }
493 
494  return DAG;
495  }
496 
497  void addIRPasses() override;
498  bool addPreISel() override;
499  void addCodeGenPrepare() override;
500  bool addInstSelector() override;
501  bool addIRTranslator() override;
502  void addPreLegalizeMachineIR() override;
503  bool addLegalizeMachineIR() override;
504  void addPreRegBankSelect() override;
505  bool addRegBankSelect() override;
506  void addPreGlobalInstructionSelect() override;
507  bool addGlobalInstructionSelect() override;
508  void addMachineSSAOptimization() override;
509  bool addILPOpts() override;
510  void addPreRegAlloc() override;
511  void addPostRegAlloc() override;
512  void addPreSched2() override;
513  void addPreEmitPass() override;
514  void addPreEmitPass2() override;
515 
516  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
517 };
518 
519 } // end anonymous namespace
520 
523  return TargetTransformInfo(AArch64TTIImpl(this, F));
524 }
525 
527  return new AArch64PassConfig(*this, PM);
528 }
529 
530 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
531  return getStandardCSEConfigForOpt(TM->getOptLevel());
532 }
533 
534 void AArch64PassConfig::addIRPasses() {
535  // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
536  // ourselves.
537  addPass(createAtomicExpandPass());
538 
539  // Expand any SVE vector library calls that we can't code generate directly.
540  if (EnableSVEIntrinsicOpts && TM->getOptLevel() == CodeGenOpt::Aggressive)
541  addPass(createSVEIntrinsicOptsPass());
542 
543  // Cmpxchg instructions are often used with a subsequent comparison to
544  // determine whether it succeeded. We can exploit existing control-flow in
545  // ldrex/strex loops to simplify this, but it needs tidying up.
546  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
548  .forwardSwitchCondToPhi(true)
549  .convertSwitchRangeToICmp(true)
550  .convertSwitchToLookupTable(true)
551  .needCanonicalLoops(false)
552  .hoistCommonInsts(true)
553  .sinkCommonInsts(true)));
554 
555  // Run LoopDataPrefetch
556  //
557  // Run this before LSR to remove the multiplies involved in computing the
558  // pointer values N iterations ahead.
559  if (TM->getOptLevel() != CodeGenOpt::None) {
561  addPass(createLoopDataPrefetchPass());
564  }
565 
567 
569  /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
570 
571  // Match interleaved memory accesses to ldN/stN intrinsics.
572  if (TM->getOptLevel() != CodeGenOpt::None) {
574  addPass(createInterleavedAccessPass());
575  }
576 
577  if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
578  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
579  // and lower a GEP with multiple indices to either arithmetic operations or
580  // multiple GEPs with single index.
582  // Call EarlyCSE pass to find and remove subexpressions in the lowered
583  // result.
584  addPass(createEarlyCSEPass());
585  // Do loop invariant code motion in case part of the lowered result is
586  // invariant.
587  addPass(createLICMPass());
588  }
589 
590  // Add Control Flow Guard checks.
591  if (TM->getTargetTriple().isOSWindows())
592  addPass(createCFGuardCheckPass());
593 
594  if (TM->Options.JMCInstrument)
595  addPass(createJMCInstrumenterPass());
596 }
597 
598 // Pass Pipeline Configuration
599 bool AArch64PassConfig::addPreISel() {
600  // Run promote constant before global merge, so that the promoted constants
601  // get a chance to be merged
602  if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
604  // FIXME: On AArch64, this depends on the type.
605  // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
606  // and the offset has to be a multiple of the related size in bytes.
607  if ((TM->getOptLevel() != CodeGenOpt::None &&
610  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
612 
613  // Merging of extern globals is enabled by default on non-Mach-O as we
614  // expect it to be generally either beneficial or harmless. On Mach-O it
615  // is disabled as we emit the .subsections_via_symbols directive which
616  // means that merging extern globals is not safe.
617  bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
618 
619  // FIXME: extern global merging is only enabled when we optimise for size
620  // because there are some regressions with it also enabled for performance.
621  if (!OnlyOptimizeForSize)
622  MergeExternalByDefault = false;
623 
624  addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
625  MergeExternalByDefault));
626  }
627 
628  return false;
629 }
630 
631 void AArch64PassConfig::addCodeGenPrepare() {
632  if (getOptLevel() != CodeGenOpt::None)
633  addPass(createTypePromotionPass());
635 }
636 
637 bool AArch64PassConfig::addInstSelector() {
638  addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
639 
640  // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
641  // references to _TLS_MODULE_BASE_ as possible.
642  if (TM->getTargetTriple().isOSBinFormatELF() &&
643  getOptLevel() != CodeGenOpt::None)
645 
646  return false;
647 }
648 
649 bool AArch64PassConfig::addIRTranslator() {
650  addPass(new IRTranslator(getOptLevel()));
651  return false;
652 }
653 
654 void AArch64PassConfig::addPreLegalizeMachineIR() {
655  if (getOptLevel() == CodeGenOpt::None)
657  else {
660  addPass(new LoadStoreOpt());
661  }
662 }
663 
664 bool AArch64PassConfig::addLegalizeMachineIR() {
665  addPass(new Legalizer());
666  return false;
667 }
668 
669 void AArch64PassConfig::addPreRegBankSelect() {
670  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
671  if (!IsOptNone) {
672  addPass(createAArch64PostLegalizerCombiner(IsOptNone));
674  addPass(new LoadStoreOpt());
675  }
677 }
678 
679 bool AArch64PassConfig::addRegBankSelect() {
680  addPass(new RegBankSelect());
681  return false;
682 }
683 
684 void AArch64PassConfig::addPreGlobalInstructionSelect() {
685  addPass(new Localizer());
686 }
687 
688 bool AArch64PassConfig::addGlobalInstructionSelect() {
689  addPass(new InstructionSelect(getOptLevel()));
690  if (getOptLevel() != CodeGenOpt::None)
692  return false;
693 }
694 
695 void AArch64PassConfig::addMachineSSAOptimization() {
696  // Run default MachineSSAOptimization first.
698 
699  if (TM->getOptLevel() != CodeGenOpt::None)
701 }
702 
703 bool AArch64PassConfig::addILPOpts() {
704  if (EnableCondOpt)
706  if (EnableCCMP)
708  if (EnableMCR)
709  addPass(&MachineCombinerID);
710  if (EnableCondBrTuning)
711  addPass(createAArch64CondBrTuning());
713  addPass(&EarlyIfConverterID);
717  if (TM->getOptLevel() != CodeGenOpt::None)
719  return true;
720 }
721 
722 void AArch64PassConfig::addPreRegAlloc() {
723  // Change dead register definitions to refer to the zero register.
724  if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
726 
727  // Use AdvSIMD scalar instructions whenever profitable.
728  if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
729  addPass(createAArch64AdvSIMDScalar());
730  // The AdvSIMD pass may produce copies that can be rewritten to
731  // be register coalescer friendly.
732  addPass(&PeepholeOptimizerID);
733  }
734 }
735 
736 void AArch64PassConfig::addPostRegAlloc() {
737  // Remove redundant copy instructions.
738  if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
740 
741  if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
742  // Improve performance for some FP/SIMD code for A57.
744 }
745 
746 void AArch64PassConfig::addPreSched2() {
747  // Lower homogeneous frame instructions
750  // Expand some pseudo instructions to allow proper scheduling.
752  // Use load/store pair instructions when possible.
753  if (TM->getOptLevel() != CodeGenOpt::None) {
754  if (EnableLoadStoreOpt)
756  }
757 
758  // The AArch64SpeculationHardeningPass destroys dominator tree and natural
759  // loop info, which is needed for the FalkorHWPFFixPass and also later on.
760  // Therefore, run the AArch64SpeculationHardeningPass before the
761  // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
762  // info.
764 
765  addPass(createAArch64IndirectThunks());
767 
768  if (TM->getOptLevel() != CodeGenOpt::None) {
770  addPass(createFalkorHWPFFixPass());
771  }
772 }
773 
774 void AArch64PassConfig::addPreEmitPass() {
775  // Machine Block Placement might have created new opportunities when run
776  // at O3, where the Tail Duplication Threshold is set to 4 instructions.
777  // Run the load/store optimizer once more.
778  if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
780 
781  if (TM->getOptLevel() >= CodeGenOpt::Aggressive &&
783  addPass(createMachineCopyPropagationPass(true));
784 
785  addPass(createAArch64A53Fix835769());
786 
789 
790  // Relax conditional branch instructions if they're otherwise out of
791  // range of their destination.
792  if (BranchRelaxation)
793  addPass(&BranchRelaxationPassID);
794 
795  if (TM->getTargetTriple().isOSWindows()) {
796  // Identify valid longjmp targets for Windows Control Flow Guard.
797  addPass(createCFGuardLongjmpPass());
798  // Identify valid eh continuation targets for Windows EHCont Guard.
800  }
801 
802  if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
804 
805  if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
806  TM->getTargetTriple().isOSBinFormatMachO())
807  addPass(createAArch64CollectLOHPass());
808 }
809 
810 void AArch64PassConfig::addPreEmitPass2() {
811  // SVE bundles move prefixes with destructive operations. BLR_RVMARKER pseudo
812  // instructions are lowered to bundles as well.
813  addPass(createUnpackMachineBundles(nullptr));
814 }
815 
818  return new yaml::AArch64FunctionInfo();
819 }
820 
823  const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
824  return new yaml::AArch64FunctionInfo(*MFI);
825 }
826 
829  SMDiagnostic &Error, SMRange &SourceRange) const {
830  const auto &YamlMFI = static_cast<const yaml::AArch64FunctionInfo &>(MFI);
831  MachineFunction &MF = PFS.MF;
832  MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
833  return false;
834 }
llvm::initializeAArch64A57FPLoadBalancingPass
void initializeAArch64A57FPLoadBalancingPass(PassRegistry &)
llvm::createJMCInstrumenterPass
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
computeDefaultCPU
static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU)
Definition: AArch64TargetMachine.cpp:263
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: AArch64TargetMachine.cpp:237
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:182
EnableBranchTargets
static cl::opt< bool > EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden, cl::desc("Enable the AArch64 branch target pass"), cl::init(true))
EnableStPairSuppress
static cl::opt< bool > EnableStPairSuppress("aarch64-enable-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden)
llvm::createAArch64LowerHomogeneousPrologEpilogPass
ModulePass * createAArch64LowerHomogeneousPrologEpilogPass()
Definition: AArch64LowerHomogeneousPrologEpilog.cpp:612
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
AArch64MachineFunctionInfo.h
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:182
llvm::initializeAArch64StackTaggingPass
void initializeAArch64StackTaggingPass(PassRegistry &)
llvm::createMachineCopyPropagationPass
MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
Definition: MachineCopyPropagation.cpp:1026
llvm::createSeparateConstOffsetFromGEPPass
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Definition: SeparateConstOffsetFromGEP.cpp:498
AArch64.h
llvm::Triple::GNUILP32
@ GNUILP32
Definition: Triple.h:233
llvm::createAArch64PromoteConstantPass
ModulePass * createAArch64PromoteConstantPass()
Definition: AArch64PromoteConstant.cpp:235
MCTargetOptions.h
llvm::PeepholeOptimizerID
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
Definition: PeepholeOptimizer.cpp:443
llvm::initializeAArch64BranchTargetsPass
void initializeAArch64BranchTargetsPass(PassRegistry &)
llvm::TargetOptions
Definition: TargetOptions.h:124
Scalar.h
T
llvm::initializeAArch64O0PreLegalizerCombinerPass
void initializeAArch64O0PreLegalizerCombinerPass(PassRegistry &)
llvm::Function
Definition: Function.h:60
llvm::Attribute
Definition: Attributes.h:65
Pass.h
llvm::yaml::MachineFunctionInfo
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Definition: MIRYamlMapping.h:676
EnableGlobalISelAtO
static cl::opt< int > EnableGlobalISelAtO("aarch64-enable-global-isel-at-O", cl::Hidden, cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"), cl::init(0))
CSEConfigBase.h
llvm::createAArch64SpeculationHardeningPass
FunctionPass * createAArch64SpeculationHardeningPass()
Returns an instance of the pseudo instruction expansion pass.
Definition: AArch64SpeculationHardening.cpp:700
llvm::createCFGSimplificationPass
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
Definition: SimplifyCFGPass.cpp:432
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
EnableRedundantCopyElimination
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:242
EnableCompressJumpTables
static cl::opt< bool > EnableCompressJumpTables("aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true), cl::desc("Use smallest entry possible for jump tables"))
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::initializeAArch64DeadRegisterDefinitionsPass
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
llvm::createAArch64CondBrTuning
FunctionPass * createAArch64CondBrTuning()
Definition: AArch64CondBrTuning.cpp:322
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
llvm::AArch64beTargetMachine::AArch64beTargetMachine
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AArch64TargetMachine.cpp:449
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::createEarlyCSEPass
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1759
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::createAArch64DeadRegisterDefinitions
FunctionPass * createAArch64DeadRegisterDefinitions()
Definition: AArch64DeadRegisterDefinitionsPass.cpp:201
llvm::createAArch64BranchTargetsPass
FunctionPass * createAArch64BranchTargetsPass()
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1886
EnableAdvSIMDScalar
static cl::opt< bool > EnableAdvSIMDScalar("aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden)
EnableHomogeneousPrologEpilog
cl::opt< bool > EnableHomogeneousPrologEpilog
llvm::TargetMachine::setSupportsDefaultOutlining
void setSupportsDefaultOutlining(bool Enable)
Definition: TargetMachine.h:256
llvm::AArch64TargetMachine::convertFuncInfoToYAML
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
Definition: AArch64TargetMachine.cpp:822
TargetInstrInfo.h
llvm::initializeAArch64CompressJumpTablesPass
void initializeAArch64CompressJumpTablesPass(PassRegistry &)
llvm::TargetOptions::TrapUnreachable
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Definition: TargetOptions.h:280
llvm::initializeAArch64A53Fix835769Pass
void initializeAArch64A53Fix835769Pass(PassRegistry &)
InstructionSelect.h
llvm::createSVEIntrinsicOptsPass
ModulePass * createSVEIntrinsicOptsPass()
Definition: SVEIntrinsicOpts.cpp:79
llvm::Optional< Reloc::Model >
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
llvm::createAArch64A57FPLoadBalancing
FunctionPass * createAArch64A57FPLoadBalancing()
Definition: AArch64A57FPLoadBalancing.cpp:721
llvm::createAArch64PostSelectOptimize
FunctionPass * createAArch64PostSelectOptimize()
Definition: AArch64PostSelectOptimize.cpp:195
llvm::TargetMachine::setCFIFixup
void setCFIFixup(bool Enable)
Definition: TargetMachine.h:263
llvm::initializeAArch64LowerHomogeneousPrologEpilogPass
void initializeAArch64LowerHomogeneousPrologEpilogPass(PassRegistry &)
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::initializeAArch64SIMDInstrOptPass
void initializeAArch64SIMDInstrOptPass(PassRegistry &)
llvm::createAArch64PreLegalizerCombiner
FunctionPass * createAArch64PreLegalizerCombiner()
Definition: AArch64PreLegalizerCombiner.cpp:488
STLExtras.h
llvm::initializeAArch64PromoteConstantPass
void initializeAArch64PromoteConstantPass(PassRegistry &)
llvm::createAArch64SIMDInstrOptPass
FunctionPass * createAArch64SIMDInstrOptPass()
Returns an instance of the high cost ASIMD instruction replacement optimization pass.
Definition: AArch64SIMDInstrOpt.cpp:738
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:28
llvm::Triple::aarch64_32
@ aarch64_32
Definition: Triple.h:53
llvm::createAArch64LoadStoreOptimizationPass
FunctionPass * createAArch64LoadStoreOptimizationPass()
createAArch64LoadStoreOptimizationPass - returns an instance of the load / store optimization pass.
Definition: AArch64LoadStoreOptimizer.cpp:2326
LLVMInitializeAArch64Target
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target()
Definition: AArch64TargetMachine.cpp:193
llvm::AArch64TargetMachine::SubtargetMap
StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap
Definition: AArch64TargetMachine.h:26
llvm::initializeFalkorHWPFFixPass
void initializeFalkorHWPFFixPass(PassRegistry &)
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::createAArch64A53Fix835769
FunctionPass * createAArch64A53Fix835769()
Definition: AArch64A53Fix835769.cpp:249
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
CSEInfo.h
BranchRelaxation
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
CommandLine.h
llvm::createAArch64PostLegalizerLowering
FunctionPass * createAArch64PostLegalizerLowering()
Definition: AArch64PostLegalizerLowering.cpp:1067
AArch64TargetMachine.h
llvm::createEHContGuardCatchretPass
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::createAArch64CompressJumpTablesPass
FunctionPass * createAArch64CompressJumpTablesPass()
Definition: AArch64CompressJumpTables.cpp:186
llvm::TargetMachine::setMachineOutliner
void setMachineOutliner(bool Enable)
Definition: TargetMachine.h:253
llvm::initializeAArch64ExpandPseudoPass
void initializeAArch64ExpandPseudoPass(PassRegistry &)
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
EnableAArch64CopyPropagation
static cl::opt< bool > EnableAArch64CopyPropagation("aarch64-enable-copy-propagation", cl::desc("Enable the copy propagation with AArch64 copy instr"), cl::init(true), cl::Hidden)
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::initializeAArch64StorePairSuppressPass
void initializeAArch64StorePairSuppressPass(PassRegistry &)
llvm::Legalizer
Definition: Legalizer.h:36
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
EnableFalkorHWPFFix
static cl::opt< bool > EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix", cl::init(true), cl::Hidden)
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:486
llvm::createAArch64StorePairSuppressPass
FunctionPass * createAArch64StorePairSuppressPass()
false
Definition: StackSlotColoring.cpp:141
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:782
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
EnableAtomicTidy
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::Attribute::getVScaleRangeMin
unsigned getVScaleRangeMin() const
Returns the minimum value for the vscale_range attribute.
Definition: Attributes.cpp:360
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1318
AArch64TargetObjectFile.h
llvm::AArch64TargetMachine
Definition: AArch64TargetMachine.h:23
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createAArch64ISelDag
FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOpt::Level OptLevel)
createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG,...
Definition: AArch64ISelDAGToDAG.cpp:5059
EnableCollectLOH
static cl::opt< bool > EnableCollectLOH("aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden)
llvm::LoadStoreOpt
Definition: LoadStoreOpt.h:62
llvm::initializeAArch64SLSHardeningPass
void initializeAArch64SLSHardeningPass(PassRegistry &)
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:98
AArch64MachineScheduler.h
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:249
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
llvm::createAArch64IndirectThunks
FunctionPass * createAArch64IndirectThunks()
Definition: AArch64SLSHardening.cpp:434
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
AArch64MacroFusion.h
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::cl::opt< bool >
llvm::createFalkorHWPFFixPass
FunctionPass * createFalkorHWPFFixPass()
Definition: AArch64FalkorHWPFFix.cpp:839
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
getEffectiveAArch64CodeModel
static CodeModel::Model getEffectiveAArch64CodeModel(const Triple &TT, Optional< CodeModel::Model > CM, bool JIT)
Definition: AArch64TargetMachine.cpp:283
llvm::cl::BOU_UNSET
@ BOU_UNSET
Definition: CommandLine.h:611
llvm::initializeAArch64ConditionalComparesPass
void initializeAArch64ConditionalComparesPass(PassRegistry &)
llvm::initializeAArch64SpeculationHardeningPass
void initializeAArch64SpeculationHardeningPass(PassRegistry &)
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::AArch64TTIImpl
Definition: AArch64TargetTransformInfo.h:41
llvm::Attribute::getVScaleRangeMax
Optional< unsigned > getVScaleRangeMax() const
Returns the maximum value for the vscale_range attribute or None when unknown.
Definition: Attributes.cpp:366
EnableGISelLoadStoreOptPostLegal
static cl::opt< bool > EnableGISelLoadStoreOptPostLegal("aarch64-enable-gisel-ldst-postlegal", cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"), cl::init(false), cl::Hidden)
llvm::initializeAArch64PostSelectOptimizePass
void initializeAArch64PostSelectOptimizePass(PassRegistry &)
CFGuard.h
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3489
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
EnableGlobalMerge
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
llvm::createAArch64ExpandPseudoPass
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
Definition: AArch64ExpandPseudoInsts.cpp:1306
llvm::createAArch64RedundantCopyEliminationPass
FunctionPass * createAArch64RedundantCopyEliminationPass()
Definition: AArch64RedundantCopyElimination.cpp:495
llvm::initializeAArch64CollectLOHPass
void initializeAArch64CollectLOHPass(PassRegistry &)
llvm::initializeAArch64PostLegalizerLoweringPass
void initializeAArch64PostLegalizerLoweringPass(PassRegistry &)
LoadStoreOpt.h
computeDataLayout
static std::string computeDataLayout(const Triple &TT, const MCTargetOptions &Options, bool LittleEndian)
Definition: AArch64TargetMachine.cpp:247
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:125
EnableMCR
static cl::opt< bool > EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
llvm::AArch64FunctionInfo
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Definition: AArch64MachineFunctionInfo.h:38
llvm::TargetOptions::NoTrapAfterNoreturn
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
Definition: TargetOptions.h:284
llvm::initializeAArch64AdvSIMDScalarPass
void initializeAArch64AdvSIMDScalarPass(PassRegistry &)
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:853
llvm::createUnpackMachineBundles
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
Definition: MachineInstrBundle.cpp:81
EnableEarlyIfConversion
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
EnableCondBrTuning
static cl::opt< bool > EnableCondBrTuning("aarch64-enable-cond-br-tune", cl::desc("Enable the conditional branch tuning pass"), cl::init(true), cl::Hidden)
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
TargetPassConfig.h
Localizer.h
llvm::createAArch64MIPeepholeOptPass
FunctionPass * createAArch64MIPeepholeOptPass()
Definition: AArch64MIPeepholeOpt.cpp:544
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:995
llvm::initializeAArch64PreLegalizerCombinerPass
void initializeAArch64PreLegalizerCombinerPass(PassRegistry &)
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::createTypePromotionPass
FunctionPass * createTypePromotionPass()
Create IR Type Promotion pass.
Definition: TypePromotion.cpp:954
llvm::X86AS::FS
@ FS
Definition: X86.h:192
llvm::createAArch64PostLegalizerCombiner
FunctionPass * createAArch64PostLegalizerCombiner(bool IsOptNone)
Definition: AArch64PostLegalizerCombiner.cpp:448
llvm::TargetOptions::TLSSize
unsigned TLSSize
Bit size of immediate TLS offsets (0 == use the default).
Definition: TargetOptions.h:287
llvm::createCFGuardCheckPass
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:300
llvm::initializeLDTLSCleanupPass
void initializeLDTLSCleanupPass(PassRegistry &)
EnableLoadStoreOpt
static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden)
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::MCTargetOptions
Definition: MCTargetOptions.h:42
llvm::Reloc::DynamicNoPIC
@ DynamicNoPIC
Definition: CodeGen.h:22
llvm::MachineFunction
Definition: MachineFunction.h:257
Triple.h
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:470
EnableGEPOpt
static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:205
llvm::initializeAArch64StackTaggingPreRAPass
void initializeAArch64StackTaggingPreRAPass(PassRegistry &)
llvm::initializeAArch64PostLegalizerCombinerPass
void initializeAArch64PostLegalizerCombinerPass(PassRegistry &)
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
llvm::createAArch64SLSHardeningPass
FunctionPass * createAArch64SLSHardeningPass()
Definition: AArch64SLSHardening.cpp:394
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::createAArch64StackTaggingPreRAPass
FunctionPass * createAArch64StackTaggingPreRAPass()
Definition: AArch64StackTaggingPreRA.cpp:98
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:75
IRTranslator.h
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
EnableSVEIntrinsicOpts
static cl::opt< bool > EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden, cl::desc("Enable SVE intrinsic opts"), cl::init(true))
AArch64TargetTransformInfo.h
llvm::createInterleavedAccessPass
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
Definition: InterleavedAccessPass.cpp:145
llvm::AArch64TargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: AArch64TargetMachine.cpp:827
Attributes.h
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::initializeAArch64MIPeepholeOptPass
void initializeAArch64MIPeepholeOptPass(PassRegistry &)
llvm::initializeAArch64RedundantCopyEliminationPass
void initializeAArch64RedundantCopyEliminationPass(PassRegistry &)
llvm::initializeFalkorMarkStridedAccessesLegacyPass
void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry &)
llvm::initializeAArch64LoadStoreOptPass
void initializeAArch64LoadStoreOptPass(PassRegistry &)
llvm::TargetMachine::setGlobalISelAbort
void setGlobalISelAbort(GlobalISelAbortMode Mode)
Definition: TargetMachine.h:250
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1306
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::createLoadClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1573
RegBankSelect.h
llvm::createAArch64MacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAArch64MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAArch64MacroFusionDAGMutation()); to AArch64PassConf...
Definition: AArch64MacroFusion.cpp:418
EnableCondOpt
static cl::opt< bool > EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)
Function.h
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
llvm::createAArch64CollectLOHPass
FunctionPass * createAArch64CollectLOHPass()
Definition: AArch64CollectLOH.cpp:595
llvm::createAArch64O0PreLegalizerCombiner
FunctionPass * createAArch64O0PreLegalizerCombiner()
Definition: AArch64O0PreLegalizerCombiner.cpp:170
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:414
AArch64MCTargetDesc.h
llvm::initializeSVEIntrinsicOptsPass
void initializeSVEIntrinsicOptsPass(PassRegistry &)
llvm::TargetMachine::setGlobalISel
void setGlobalISel(bool Enable)
Definition: TargetMachine.h:249
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:164
llvm::AArch64TargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: AArch64TargetMachine.cpp:526
CFIFixup.h
llvm::createGlobalMergePass
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
Definition: GlobalMerge.cpp:692
llvm::BranchRelaxationPassID
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Definition: BranchRelaxation.cpp:118
EnableLoopDataPrefetch
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
CodeGen.h
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
EnableCCMP
static cl::opt< bool > EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)
llvm::cl::BOU_TRUE
@ BOU_TRUE
Definition: CommandLine.h:611
Legalizer.h
llvm::SimplifyCFGOptions
Definition: SimplifyCFGOptions.h:23
llvm::createLICMPass
Pass * createLICMPass()
Definition: LICM.cpp:345
MachineScheduler.h
AArch64Subtarget.h
EnableDeadRegisterElimination
static cl::opt< bool > EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to the zero" " register"), cl::init(true))
llvm::createAArch64AdvSIMDScalar
FunctionPass * createAArch64AdvSIMDScalar()
Definition: AArch64AdvSIMDScalarPass.cpp:409
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:197
SVEVectorBitsMinOpt
static cl::opt< unsigned > SVEVectorBitsMinOpt("aarch64-sve-vector-bits-min", cl::desc("Assume SVE vector registers are at least this big, " "with zero meaning no minimum size is assumed."), cl::init(0), cl::Hidden)
llvm::createAArch64StackTaggingPass
FunctionPass * createAArch64StackTaggingPass(bool IsOptNone)
Definition: AArch64StackTagging.cpp:352
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
llvm::createAArch64ConditionOptimizerPass
FunctionPass * createAArch64ConditionOptimizerPass()
Definition: AArch64ConditionOptimizer.cpp:133
llvm::AArch64TargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: AArch64TargetMachine.cpp:522
llvm::to_string
std::string to_string(const T &Value)
Definition: ScopedPrinter.h:85
llvm::MachineCombinerID
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
Definition: MachineCombiner.cpp:129
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::createStoreClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1580
llvm::IRTranslator
Definition: IRTranslator.h:62
llvm::GlobalISelAbortMode::Disable
@ Disable
EnablePromoteConstant
static cl::opt< bool > EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden)
llvm::AArch64TargetMachine::AArch64TargetMachine
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT, bool IsLittleEndian)
Create an AArch64 architecture model.
Definition: AArch64TargetMachine.cpp:307
llvm::initializeAArch64ConditionOptimizerPass
void initializeAArch64ConditionOptimizerPass(PassRegistry &)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.h:225
llvm::createInterleavedLoadCombinePass
FunctionPass * createInterleavedLoadCombinePass()
InterleavedLoadCombines Pass - This pass identifies interleaved loads and combines them into wide loa...
Definition: InterleavedLoadCombinePass.cpp:1358
llvm::TargetMachine::setSupportsDebugEntryValues
void setSupportsDebugEntryValues(bool Enable)
Definition: TargetMachine.h:259
llvm::createAArch64CleanupLocalDynamicTLSPass
FunctionPass * createAArch64CleanupLocalDynamicTLSPass()
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:244
llvm::cl::desc
Definition: CommandLine.h:405
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:390
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::createAArch64ConditionalCompares
FunctionPass * createAArch64ConditionalCompares()
Definition: AArch64ConditionalCompares.cpp:805
llvm::createFalkorMarkStridedAccessesPass
FunctionPass * createFalkorMarkStridedAccessesPass()
Definition: AArch64FalkorHWPFFix.cpp:116
TargetRegistry.h
llvm::AArch64TargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: AArch64TargetMachine.cpp:817
InitializePasses.h
SVEVectorBitsMaxOpt
static cl::opt< unsigned > SVEVectorBitsMaxOpt("aarch64-sve-vector-bits-max", cl::desc("Assume SVE vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
llvm::AArch64leTargetMachine::AArch64leTargetMachine
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AArch64TargetMachine.cpp:441
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:97
llvm::yaml::AArch64FunctionInfo
Definition: AArch64MachineFunctionInfo.h:439
EnableGISelLoadStoreOptPreLegal
static cl::opt< bool > EnableGISelLoadStoreOptPreLegal("aarch64-enable-gisel-ldst-prelegal", cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"), cl::init(true), cl::Hidden)
llvm::createLoopDataPrefetchPass
FunctionPass * createLoopDataPrefetchPass()
Definition: LoopDataPrefetch.cpp:152
MIParser.h
AArch64TargetInfo.h
llvm::createCFGuardLongjmpPass
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
llvm::AArch64TargetMachine::~AArch64TargetMachine
~AArch64TargetMachine() override
llvm::Localizer
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:43
llvm::AArch64TargetMachine::getSubtargetImpl
const AArch64Subtarget * getSubtargetImpl() const =delete