LLVM  17.0.0git
AArch64TargetMachine.cpp
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1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
16 #include "AArch64MacroFusion.h"
17 #include "AArch64Subtarget.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/Triple.h"
25 #include "llvm/CodeGen/CFIFixup.h"
36 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/InitializePasses.h"
42 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/TargetRegistry.h"
45 #include "llvm/Pass.h"
46 #include "llvm/Support/CodeGen.h"
51 #include "llvm/Transforms/Scalar.h"
52 #include <memory>
53 #include <optional>
54 #include <string>
55 
56 using namespace llvm;
57 
58 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
59  cl::desc("Enable the CCMP formation pass"),
60  cl::init(true), cl::Hidden);
61 
62 static cl::opt<bool>
63  EnableCondBrTuning("aarch64-enable-cond-br-tune",
64  cl::desc("Enable the conditional branch tuning pass"),
65  cl::init(true), cl::Hidden);
66 
68  "aarch64-enable-copy-propagation",
69  cl::desc("Enable the copy propagation with AArch64 copy instr"),
70  cl::init(true), cl::Hidden);
71 
72 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
73  cl::desc("Enable the machine combiner pass"),
74  cl::init(true), cl::Hidden);
75 
76 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
77  cl::desc("Suppress STP for AArch64"),
78  cl::init(true), cl::Hidden);
79 
81  "aarch64-enable-simd-scalar",
82  cl::desc("Enable use of AdvSIMD scalar integer instructions"),
83  cl::init(false), cl::Hidden);
84 
85 static cl::opt<bool>
86  EnablePromoteConstant("aarch64-enable-promote-const",
87  cl::desc("Enable the promote constant pass"),
88  cl::init(true), cl::Hidden);
89 
91  "aarch64-enable-collect-loh",
92  cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
93  cl::init(true), cl::Hidden);
94 
95 static cl::opt<bool>
96  EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
97  cl::desc("Enable the pass that removes dead"
98  " definitons and replaces stores to"
99  " them with stores to the zero"
100  " register"),
101  cl::init(true));
102 
104  "aarch64-enable-copyelim",
105  cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
106  cl::Hidden);
107 
108 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
109  cl::desc("Enable the load/store pair"
110  " optimization pass"),
111  cl::init(true), cl::Hidden);
112 
114  "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
115  cl::desc("Run SimplifyCFG after expanding atomic operations"
116  " to make use of cmpxchg flow-based information"),
117  cl::init(true));
118 
119 static cl::opt<bool>
120 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
121  cl::desc("Run early if-conversion"),
122  cl::init(true));
123 
124 static cl::opt<bool>
125  EnableCondOpt("aarch64-enable-condopt",
126  cl::desc("Enable the condition optimizer pass"),
127  cl::init(true), cl::Hidden);
128 
129 static cl::opt<bool>
130  EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
131  cl::desc("Enable optimizations on complex GEPs"),
132  cl::init(false));
133 
134 static cl::opt<bool>
135  EnableSelectOpt("aarch64-select-opt", cl::Hidden,
136  cl::desc("Enable select to branch optimizations"),
137  cl::init(true));
138 
139 static cl::opt<bool>
140  BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
141  cl::desc("Relax out of range conditional branches"));
142 
144  "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
145  cl::desc("Use smallest entry possible for jump tables"));
146 
147 // FIXME: Unify control over GlobalMerge.
149  EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
150  cl::desc("Enable the global merge pass"));
151 
152 static cl::opt<bool>
153  EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
154  cl::desc("Enable the loop data prefetch pass"),
155  cl::init(true));
156 
158  "aarch64-enable-global-isel-at-O", cl::Hidden,
159  cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
160  cl::init(0));
161 
162 static cl::opt<bool>
163  EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
164  cl::desc("Enable SVE intrinsic opts"),
165  cl::init(true));
166 
167 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
168  cl::init(true), cl::Hidden);
169 
170 static cl::opt<bool>
171  EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
172  cl::desc("Enable the AArch64 branch target pass"),
173  cl::init(true));
174 
176  "aarch64-sve-vector-bits-max",
177  cl::desc("Assume SVE vector registers are at most this big, "
178  "with zero meaning no maximum size is assumed."),
179  cl::init(0), cl::Hidden);
180 
182  "aarch64-sve-vector-bits-min",
183  cl::desc("Assume SVE vector registers are at least this big, "
184  "with zero meaning no minimum size is assumed."),
185  cl::init(0), cl::Hidden);
186 
188 
190  "aarch64-enable-gisel-ldst-prelegal",
191  cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"),
192  cl::init(true), cl::Hidden);
193 
195  "aarch64-enable-gisel-ldst-postlegal",
196  cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"),
197  cl::init(false), cl::Hidden);
198 
200  // Register the target.
206  auto PR = PassRegistry::getPassRegistry();
241 }
242 
243 //===----------------------------------------------------------------------===//
244 // AArch64 Lowering public interface.
245 //===----------------------------------------------------------------------===//
246 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
247  if (TT.isOSBinFormatMachO())
248  return std::make_unique<AArch64_MachoTargetObjectFile>();
249  if (TT.isOSBinFormatCOFF())
250  return std::make_unique<AArch64_COFFTargetObjectFile>();
251 
252  return std::make_unique<AArch64_ELFTargetObjectFile>();
253 }
254 
255 // Helper function to build a DataLayout string
256 static std::string computeDataLayout(const Triple &TT,
257  const MCTargetOptions &Options,
258  bool LittleEndian) {
259  if (TT.isOSBinFormatMachO()) {
260  if (TT.getArch() == Triple::aarch64_32)
261  return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
262  return "e-m:o-i64:64-i128:128-n32:64-S128";
263  }
264  if (TT.isOSBinFormatCOFF())
265  return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
266  std::string Endian = LittleEndian ? "e" : "E";
267  std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
268  return Endian + "-m:e" + Ptr32 +
269  "-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
270 }
271 
272 static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {
273  if (CPU.empty() && TT.isArm64e())
274  return "apple-a12";
275  return CPU;
276 }
277 
279  std::optional<Reloc::Model> RM) {
280  // AArch64 Darwin and Windows are always PIC.
281  if (TT.isOSDarwin() || TT.isOSWindows())
282  return Reloc::PIC_;
283  // On ELF platforms the default static relocation model has a smart enough
284  // linker to cope with referencing external symbols defined in a shared
285  // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
286  if (!RM || *RM == Reloc::DynamicNoPIC)
287  return Reloc::Static;
288  return *RM;
289 }
290 
291 static CodeModel::Model
293  std::optional<CodeModel::Model> CM, bool JIT) {
294  if (CM) {
295  if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
296  *CM != CodeModel::Large) {
298  "Only small, tiny and large code models are allowed on AArch64");
299  } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
300  report_fatal_error("tiny code model is only supported on ELF");
301  return *CM;
302  }
303  // The default MCJIT memory managers make no guarantees about where they can
304  // find an executable page; JITed code needs to be able to refer to globals
305  // no matter how far away they are.
306  // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
307  // since with large code model LLVM generating 4 MOV instructions, and
308  // Windows doesn't support relocating these long branch (4 MOVs).
309  if (JIT && !TT.isOSWindows())
310  return CodeModel::Large;
311  return CodeModel::Small;
312 }
313 
314 /// Create an AArch64 architecture model.
315 ///
317  StringRef CPU, StringRef FS,
318  const TargetOptions &Options,
319  std::optional<Reloc::Model> RM,
320  std::optional<CodeModel::Model> CM,
321  CodeGenOpt::Level OL, bool JIT,
322  bool LittleEndian)
324  computeDataLayout(TT, Options.MCOptions, LittleEndian),
325  TT, computeDefaultCPU(TT, CPU), FS, Options,
327  getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
328  TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
329  initAsmInfo();
330 
331  if (TT.isOSBinFormatMachO()) {
332  this->Options.TrapUnreachable = true;
333  this->Options.NoTrapAfterNoreturn = true;
334  }
335 
336  if (getMCAsmInfo()->usesWindowsCFI()) {
337  // Unwinding can get confused if the last instruction in an
338  // exception-handling region (function, funclet, try block, etc.)
339  // is a call.
340  //
341  // FIXME: We could elide the trap if the next instruction would be in
342  // the same region anyway.
343  this->Options.TrapUnreachable = true;
344  }
345 
346  if (this->Options.TLSSize == 0) // default
347  this->Options.TLSSize = 24;
348  if ((getCodeModel() == CodeModel::Small ||
350  this->Options.TLSSize > 32)
351  // for the small (and kernel) code model, the maximum TLS size is 4GiB
352  this->Options.TLSSize = 32;
353  else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
354  // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
355  this->Options.TLSSize = 24;
356 
357  // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
358  // MachO/CodeModel::Large, which GlobalISel does not support.
359  if (getOptLevel() <= EnableGlobalISelAtO &&
360  TT.getArch() != Triple::aarch64_32 &&
361  TT.getEnvironment() != Triple::GNUILP32 &&
362  !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
363  setGlobalISel(true);
365  }
366 
367  // AArch64 supports the MachineOutliner.
368  setMachineOutliner(true);
369 
370  // AArch64 supports default outlining behaviour.
372 
373  // AArch64 supports the debug entry values.
375 
376  // AArch64 supports fixing up the DWARF unwind information.
377  if (!getMCAsmInfo()->usesWindowsCFI())
378  setCFIFixup(true);
379 }
380 
382 
383 const AArch64Subtarget *
385  Attribute CPUAttr = F.getFnAttribute("target-cpu");
386  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
387  Attribute FSAttr = F.getFnAttribute("target-features");
388 
389  StringRef CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString() : TargetCPU;
390  StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString() : CPU;
391  StringRef FS = FSAttr.isValid() ? FSAttr.getValueAsString() : TargetFS;
392 
393  bool StreamingSVEModeDisabled =
394  !F.hasFnAttribute("aarch64_pstate_sm_enabled") &&
395  !F.hasFnAttribute("aarch64_pstate_sm_compatible") &&
396  !F.hasFnAttribute("aarch64_pstate_sm_body");
397 
398  unsigned MinSVEVectorSize = 0;
399  unsigned MaxSVEVectorSize = 0;
400  Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
401  if (VScaleRangeAttr.isValid()) {
402  std::optional<unsigned> VScaleMax = VScaleRangeAttr.getVScaleRangeMax();
403  MinSVEVectorSize = VScaleRangeAttr.getVScaleRangeMin() * 128;
404  MaxSVEVectorSize = VScaleMax ? *VScaleMax * 128 : 0;
405  } else {
406  MinSVEVectorSize = SVEVectorBitsMinOpt;
407  MaxSVEVectorSize = SVEVectorBitsMaxOpt;
408  }
409 
410  assert(MinSVEVectorSize % 128 == 0 &&
411  "SVE requires vector length in multiples of 128!");
412  assert(MaxSVEVectorSize % 128 == 0 &&
413  "SVE requires vector length in multiples of 128!");
414  assert((MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == 0) &&
415  "Minimum SVE vector size should not be larger than its maximum!");
416 
417  // Sanitize user input in case of no asserts
418  if (MaxSVEVectorSize == 0)
419  MinSVEVectorSize = (MinSVEVectorSize / 128) * 128;
420  else {
421  MinSVEVectorSize =
422  (std::min(MinSVEVectorSize, MaxSVEVectorSize) / 128) * 128;
423  MaxSVEVectorSize =
424  (std::max(MinSVEVectorSize, MaxSVEVectorSize) / 128) * 128;
425  }
426 
428  raw_svector_ostream(Key) << "SVEMin" << MinSVEVectorSize << "SVEMax"
429  << MaxSVEVectorSize << "StreamingSVEModeDisabled="
430  << StreamingSVEModeDisabled << CPU << TuneCPU << FS;
431 
432  auto &I = SubtargetMap[Key];
433  if (!I) {
434  // This needs to be done before we create a new subtarget since any
435  // creation will depend on the TM and the code generation flags on the
436  // function that reside in TargetOptions.
438  I = std::make_unique<AArch64Subtarget>(
439  TargetTriple, CPU, TuneCPU, FS, *this, isLittle, MinSVEVectorSize,
440  MaxSVEVectorSize, StreamingSVEModeDisabled);
441  }
442  return I.get();
443 }
444 
445 void AArch64leTargetMachine::anchor() { }
446 
448  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
449  const TargetOptions &Options, std::optional<Reloc::Model> RM,
450  std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
451  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
452 
453 void AArch64beTargetMachine::anchor() { }
454 
456  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
457  const TargetOptions &Options, std::optional<Reloc::Model> RM,
458  std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
459  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
460 
461 namespace {
462 
463 /// AArch64 Code Generator Pass Configuration Options.
464 class AArch64PassConfig : public TargetPassConfig {
465 public:
466  AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
467  : TargetPassConfig(TM, PM) {
468  if (TM.getOptLevel() != CodeGenOpt::None)
469  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
470  }
471 
472  AArch64TargetMachine &getAArch64TargetMachine() const {
473  return getTM<AArch64TargetMachine>();
474  }
475 
477  createMachineScheduler(MachineSchedContext *C) const override {
478  const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
480  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
481  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
482  if (ST.hasFusion())
483  DAG->addMutation(createAArch64MacroFusionDAGMutation());
484  return DAG;
485  }
486 
488  createPostMachineScheduler(MachineSchedContext *C) const override {
489  const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
490  ScheduleDAGMI *DAG =
491  new ScheduleDAGMI(C, std::make_unique<AArch64PostRASchedStrategy>(C),
492  /* RemoveKillFlags=*/true);
493  if (ST.hasFusion()) {
494  // Run the Macro Fusion after RA again since literals are expanded from
495  // pseudos then (v. addPreSched2()).
496  DAG->addMutation(createAArch64MacroFusionDAGMutation());
497  return DAG;
498  }
499 
500  return DAG;
501  }
502 
503  void addIRPasses() override;
504  bool addPreISel() override;
505  void addCodeGenPrepare() override;
506  bool addInstSelector() override;
507  bool addIRTranslator() override;
508  void addPreLegalizeMachineIR() override;
509  bool addLegalizeMachineIR() override;
510  void addPreRegBankSelect() override;
511  bool addRegBankSelect() override;
512  void addPreGlobalInstructionSelect() override;
513  bool addGlobalInstructionSelect() override;
514  void addMachineSSAOptimization() override;
515  bool addILPOpts() override;
516  void addPreRegAlloc() override;
517  void addPostRegAlloc() override;
518  void addPreSched2() override;
519  void addPreEmitPass() override;
520  void addPreEmitPass2() override;
521 
522  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
523 };
524 
525 } // end anonymous namespace
526 
529  return TargetTransformInfo(AArch64TTIImpl(this, F));
530 }
531 
533  return new AArch64PassConfig(*this, PM);
534 }
535 
536 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
537  return getStandardCSEConfigForOpt(TM->getOptLevel());
538 }
539 
540 void AArch64PassConfig::addIRPasses() {
541  // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
542  // ourselves.
543  addPass(createAtomicExpandPass());
544 
545  // Expand any SVE vector library calls that we can't code generate directly.
546  if (EnableSVEIntrinsicOpts && TM->getOptLevel() == CodeGenOpt::Aggressive)
547  addPass(createSVEIntrinsicOptsPass());
548 
549  // Cmpxchg instructions are often used with a subsequent comparison to
550  // determine whether it succeeded. We can exploit existing control-flow in
551  // ldrex/strex loops to simplify this, but it needs tidying up.
552  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
554  .forwardSwitchCondToPhi(true)
555  .convertSwitchRangeToICmp(true)
556  .convertSwitchToLookupTable(true)
557  .needCanonicalLoops(false)
558  .hoistCommonInsts(true)
559  .sinkCommonInsts(true)));
560 
561  // Run LoopDataPrefetch
562  //
563  // Run this before LSR to remove the multiplies involved in computing the
564  // pointer values N iterations ahead.
565  if (TM->getOptLevel() != CodeGenOpt::None) {
567  addPass(createLoopDataPrefetchPass());
570  }
571 
572  if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
573  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
574  // and lower a GEP with multiple indices to either arithmetic operations or
575  // multiple GEPs with single index.
577  // Call EarlyCSE pass to find and remove subexpressions in the lowered
578  // result.
579  addPass(createEarlyCSEPass());
580  // Do loop invariant code motion in case part of the lowered result is
581  // invariant.
582  addPass(createLICMPass());
583  }
584 
586 
587  if (getOptLevel() == CodeGenOpt::Aggressive && EnableSelectOpt)
588  addPass(createSelectOptimizePass());
589 
591  /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
592 
593  // Match complex arithmetic patterns
594  if (TM->getOptLevel() >= CodeGenOpt::Default)
596 
597  // Match interleaved memory accesses to ldN/stN intrinsics.
598  if (TM->getOptLevel() != CodeGenOpt::None) {
600  addPass(createInterleavedAccessPass());
601  }
602 
603  // Expand any functions marked with SME attributes which require special
604  // changes for the calling convention or that require the lazy-saving
605  // mechanism specified in the SME ABI.
606  addPass(createSMEABIPass());
607 
608  // Add Control Flow Guard checks.
609  if (TM->getTargetTriple().isOSWindows())
610  addPass(createCFGuardCheckPass());
611 
612  if (TM->Options.JMCInstrument)
613  addPass(createJMCInstrumenterPass());
614 }
615 
616 // Pass Pipeline Configuration
617 bool AArch64PassConfig::addPreISel() {
618  // Run promote constant before global merge, so that the promoted constants
619  // get a chance to be merged
620  if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
622  // FIXME: On AArch64, this depends on the type.
623  // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
624  // and the offset has to be a multiple of the related size in bytes.
625  if ((TM->getOptLevel() != CodeGenOpt::None &&
628  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
630 
631  // Merging of extern globals is enabled by default on non-Mach-O as we
632  // expect it to be generally either beneficial or harmless. On Mach-O it
633  // is disabled as we emit the .subsections_via_symbols directive which
634  // means that merging extern globals is not safe.
635  bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
636 
637  // FIXME: extern global merging is only enabled when we optimise for size
638  // because there are some regressions with it also enabled for performance.
639  if (!OnlyOptimizeForSize)
640  MergeExternalByDefault = false;
641 
642  addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
643  MergeExternalByDefault));
644  }
645 
646  return false;
647 }
648 
649 void AArch64PassConfig::addCodeGenPrepare() {
650  if (getOptLevel() != CodeGenOpt::None)
653 }
654 
655 bool AArch64PassConfig::addInstSelector() {
656  addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
657 
658  // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
659  // references to _TLS_MODULE_BASE_ as possible.
660  if (TM->getTargetTriple().isOSBinFormatELF() &&
661  getOptLevel() != CodeGenOpt::None)
663 
664  return false;
665 }
666 
667 bool AArch64PassConfig::addIRTranslator() {
668  addPass(new IRTranslator(getOptLevel()));
669  return false;
670 }
671 
672 void AArch64PassConfig::addPreLegalizeMachineIR() {
673  if (getOptLevel() == CodeGenOpt::None)
675  else {
678  addPass(new LoadStoreOpt());
679  }
680 }
681 
682 bool AArch64PassConfig::addLegalizeMachineIR() {
683  addPass(new Legalizer());
684  return false;
685 }
686 
687 void AArch64PassConfig::addPreRegBankSelect() {
688  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
689  if (!IsOptNone) {
690  addPass(createAArch64PostLegalizerCombiner(IsOptNone));
692  addPass(new LoadStoreOpt());
693  }
695 }
696 
697 bool AArch64PassConfig::addRegBankSelect() {
698  addPass(new RegBankSelect());
699  return false;
700 }
701 
702 void AArch64PassConfig::addPreGlobalInstructionSelect() {
703  addPass(new Localizer());
704 }
705 
706 bool AArch64PassConfig::addGlobalInstructionSelect() {
707  addPass(new InstructionSelect(getOptLevel()));
708  if (getOptLevel() != CodeGenOpt::None)
710  return false;
711 }
712 
713 void AArch64PassConfig::addMachineSSAOptimization() {
714  // Run default MachineSSAOptimization first.
716 
717  if (TM->getOptLevel() != CodeGenOpt::None)
719 }
720 
721 bool AArch64PassConfig::addILPOpts() {
722  if (EnableCondOpt)
724  if (EnableCCMP)
726  if (EnableMCR)
727  addPass(&MachineCombinerID);
728  if (EnableCondBrTuning)
729  addPass(createAArch64CondBrTuning());
731  addPass(&EarlyIfConverterID);
735  if (TM->getOptLevel() != CodeGenOpt::None)
737  return true;
738 }
739 
740 void AArch64PassConfig::addPreRegAlloc() {
741  // Change dead register definitions to refer to the zero register.
742  if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
744 
745  // Use AdvSIMD scalar instructions whenever profitable.
746  if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
747  addPass(createAArch64AdvSIMDScalar());
748  // The AdvSIMD pass may produce copies that can be rewritten to
749  // be register coalescer friendly.
750  addPass(&PeepholeOptimizerID);
751  }
752 }
753 
754 void AArch64PassConfig::addPostRegAlloc() {
755  // Remove redundant copy instructions.
756  if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
758 
759  if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
760  // Improve performance for some FP/SIMD code for A57.
762 }
763 
764 void AArch64PassConfig::addPreSched2() {
765  // Lower homogeneous frame instructions
768  // Expand some pseudo instructions to allow proper scheduling.
770  // Use load/store pair instructions when possible.
771  if (TM->getOptLevel() != CodeGenOpt::None) {
772  if (EnableLoadStoreOpt)
774  }
775  // Emit KCFI checks for indirect calls.
776  addPass(createAArch64KCFIPass());
777 
778  // The AArch64SpeculationHardeningPass destroys dominator tree and natural
779  // loop info, which is needed for the FalkorHWPFFixPass and also later on.
780  // Therefore, run the AArch64SpeculationHardeningPass before the
781  // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
782  // info.
784 
785  addPass(createAArch64IndirectThunks());
787 
788  if (TM->getOptLevel() != CodeGenOpt::None) {
790  addPass(createFalkorHWPFFixPass());
791  }
792 }
793 
794 void AArch64PassConfig::addPreEmitPass() {
795  // Machine Block Placement might have created new opportunities when run
796  // at O3, where the Tail Duplication Threshold is set to 4 instructions.
797  // Run the load/store optimizer once more.
798  if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
800 
801  if (TM->getOptLevel() >= CodeGenOpt::Aggressive &&
803  addPass(createMachineCopyPropagationPass(true));
804 
805  addPass(createAArch64A53Fix835769());
806 
809 
810  // Relax conditional branch instructions if they're otherwise out of
811  // range of their destination.
812  if (BranchRelaxation)
813  addPass(&BranchRelaxationPassID);
814 
815  if (TM->getTargetTriple().isOSWindows()) {
816  // Identify valid longjmp targets for Windows Control Flow Guard.
817  addPass(createCFGuardLongjmpPass());
818  // Identify valid eh continuation targets for Windows EHCont Guard.
820  }
821 
822  if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
824 
825  if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
826  TM->getTargetTriple().isOSBinFormatMachO())
827  addPass(createAArch64CollectLOHPass());
828 }
829 
830 void AArch64PassConfig::addPreEmitPass2() {
831  // SVE bundles move prefixes with destructive operations. BLR_RVMARKER pseudo
832  // instructions are lowered to bundles as well.
833  addPass(createUnpackMachineBundles(nullptr));
834 }
835 
838  const TargetSubtargetInfo *STI) const {
839  return AArch64FunctionInfo::create<AArch64FunctionInfo>(
840  Allocator, F, static_cast<const AArch64Subtarget *>(STI));
841 }
842 
845  return new yaml::AArch64FunctionInfo();
846 }
847 
850  const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
851  return new yaml::AArch64FunctionInfo(*MFI);
852 }
853 
856  SMDiagnostic &Error, SMRange &SourceRange) const {
857  const auto &YamlMFI = static_cast<const yaml::AArch64FunctionInfo &>(MFI);
858  MachineFunction &MF = PFS.MF;
859  MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
860  return false;
861 }
llvm::initializeAArch64A57FPLoadBalancingPass
void initializeAArch64A57FPLoadBalancingPass(PassRegistry &)
llvm::createJMCInstrumenterPass
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
computeDefaultCPU
static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU)
Definition: AArch64TargetMachine.cpp:272
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: AArch64TargetMachine.cpp:246
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:182
EnableBranchTargets
static cl::opt< bool > EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden, cl::desc("Enable the AArch64 branch target pass"), cl::init(true))
EnableStPairSuppress
static cl::opt< bool > EnableStPairSuppress("aarch64-enable-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden)
llvm::createAArch64LowerHomogeneousPrologEpilogPass
ModulePass * createAArch64LowerHomogeneousPrologEpilogPass()
Definition: AArch64LowerHomogeneousPrologEpilog.cpp:612
llvm::initializeAArch64DAGToDAGISelPass
void initializeAArch64DAGToDAGISelPass(PassRegistry &)
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
AArch64MachineFunctionInfo.h
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:185
llvm::initializeAArch64StackTaggingPass
void initializeAArch64StackTaggingPass(PassRegistry &)
llvm::TargetMachine::STI
std::unique_ptr< const MCSubtargetInfo > STI
Definition: TargetMachine.h:109
llvm::createMachineCopyPropagationPass
MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
Definition: MachineCopyPropagation.cpp:1037
llvm::createSeparateConstOffsetFromGEPPass
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Definition: SeparateConstOffsetFromGEP.cpp:498
AArch64.h
llvm::Triple::GNUILP32
@ GNUILP32
Definition: Triple.h:240
llvm::createAArch64KCFIPass
FunctionPass * createAArch64KCFIPass()
Definition: AArch64KCFI.cpp:55
llvm::createAArch64PromoteConstantPass
ModulePass * createAArch64PromoteConstantPass()
Definition: AArch64PromoteConstant.cpp:235
MCTargetOptions.h
llvm::PeepholeOptimizerID
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
Definition: PeepholeOptimizer.cpp:442
llvm::initializeAArch64BranchTargetsPass
void initializeAArch64BranchTargetsPass(PassRegistry &)
llvm::TargetOptions
Definition: TargetOptions.h:124
Scalar.h
T
llvm::initializeAArch64O0PreLegalizerCombinerPass
void initializeAArch64O0PreLegalizerCombinerPass(PassRegistry &)
llvm::Function
Definition: Function.h:59
EnableSelectOpt
static cl::opt< bool > EnableSelectOpt("aarch64-select-opt", cl::Hidden, cl::desc("Enable select to branch optimizations"), cl::init(true))
llvm::Attribute
Definition: Attributes.h:67
Pass.h
llvm::yaml::MachineFunctionInfo
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Definition: MIRYamlMapping.h:677
EnableGlobalISelAtO
static cl::opt< int > EnableGlobalISelAtO("aarch64-enable-global-isel-at-O", cl::Hidden, cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"), cl::init(0))
CSEConfigBase.h
llvm::createAArch64SpeculationHardeningPass
FunctionPass * createAArch64SpeculationHardeningPass()
Returns an instance of the pseudo instruction expansion pass.
Definition: AArch64SpeculationHardening.cpp:700
llvm::createCFGSimplificationPass
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
Definition: SimplifyCFGPass.cpp:432
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
EnableRedundantCopyElimination
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:276
EnableCompressJumpTables
static cl::opt< bool > EnableCompressJumpTables("aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true), cl::desc("Use smallest entry possible for jump tables"))
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:172
llvm::AArch64TargetMachine::createMachineFunctionInfo
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
Definition: AArch64TargetMachine.cpp:836
llvm::initializeAArch64DeadRegisterDefinitionsPass
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
llvm::createAArch64CondBrTuning
FunctionPass * createAArch64CondBrTuning()
Definition: AArch64CondBrTuning.cpp:323
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
llvm::AArch64leTargetMachine::AArch64leTargetMachine
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AArch64TargetMachine.cpp:447
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::createEarlyCSEPass
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1793
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:138
llvm::createAArch64DeadRegisterDefinitions
FunctionPass * createAArch64DeadRegisterDefinitions()
Definition: AArch64DeadRegisterDefinitionsPass.cpp:200
llvm::initializeAArch64KCFIPass
void initializeAArch64KCFIPass(PassRegistry &)
llvm::createAArch64BranchTargetsPass
FunctionPass * createAArch64BranchTargetsPass()
EnableAdvSIMDScalar
static cl::opt< bool > EnableAdvSIMDScalar("aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden)
llvm::X86AS::FS
@ FS
Definition: X86.h:201
EnableHomogeneousPrologEpilog
cl::opt< bool > EnableHomogeneousPrologEpilog
llvm::TargetMachine::setSupportsDefaultOutlining
void setSupportsDefaultOutlining(bool Enable)
Definition: TargetMachine.h:264
llvm::AArch64TargetMachine::convertFuncInfoToYAML
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
Definition: AArch64TargetMachine.cpp:849
TargetInstrInfo.h
llvm::initializeAArch64CompressJumpTablesPass
void initializeAArch64CompressJumpTablesPass(PassRegistry &)
llvm::TargetOptions::TrapUnreachable
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Definition: TargetOptions.h:280
llvm::initializeAArch64A53Fix835769Pass
void initializeAArch64A53Fix835769Pass(PassRegistry &)
InstructionSelect.h
llvm::createSVEIntrinsicOptsPass
ModulePass * createSVEIntrinsicOptsPass()
Definition: SVEIntrinsicOpts.cpp:80
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
llvm::createAArch64A57FPLoadBalancing
FunctionPass * createAArch64A57FPLoadBalancing()
Definition: AArch64A57FPLoadBalancing.cpp:721
llvm::createAArch64PostSelectOptimize
FunctionPass * createAArch64PostSelectOptimize()
Definition: AArch64PostSelectOptimize.cpp:259
llvm::TargetMachine::setCFIFixup
void setCFIFixup(bool Enable)
Definition: TargetMachine.h:271
llvm::initializeAArch64LowerHomogeneousPrologEpilogPass
void initializeAArch64LowerHomogeneousPrologEpilogPass(PassRegistry &)
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::initializeAArch64SIMDInstrOptPass
void initializeAArch64SIMDInstrOptPass(PassRegistry &)
llvm::createAArch64PreLegalizerCombiner
FunctionPass * createAArch64PreLegalizerCombiner()
Definition: AArch64PreLegalizerCombiner.cpp:489
STLExtras.h
llvm::initializeAArch64PromoteConstantPass
void initializeAArch64PromoteConstantPass(PassRegistry &)
llvm::createAArch64SIMDInstrOptPass
FunctionPass * createAArch64SIMDInstrOptPass()
Returns an instance of the high cost ASIMD instruction replacement optimization pass.
Definition: AArch64SIMDInstrOpt.cpp:738
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:31
llvm::Triple::aarch64_32
@ aarch64_32
Definition: Triple.h:53
llvm::createAArch64LoadStoreOptimizationPass
FunctionPass * createAArch64LoadStoreOptimizationPass()
createAArch64LoadStoreOptimizationPass - returns an instance of the load / store optimization pass.
Definition: AArch64LoadStoreOptimizer.cpp:2335
LLVMInitializeAArch64Target
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target()
Definition: AArch64TargetMachine.cpp:199
llvm::AArch64TargetMachine::SubtargetMap
StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap
Definition: AArch64TargetMachine.h:27
llvm::initializeFalkorHWPFFixPass
void initializeFalkorHWPFFixPass(PassRegistry &)
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::createComplexDeinterleavingPass
FunctionPass * createComplexDeinterleavingPass(const TargetMachine *TM)
This pass implements generation of target-specific intrinsics to support handling of complex number a...
Definition: ComplexDeinterleavingPass.cpp:313
llvm::createAArch64A53Fix835769
FunctionPass * createAArch64A53Fix835769()
Definition: AArch64A53Fix835769.cpp:249
llvm::Reloc::Model
Model
Definition: CodeGen.h:25
CSEInfo.h
BranchRelaxation
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
CommandLine.h
llvm::AArch64beTargetMachine::AArch64beTargetMachine
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AArch64TargetMachine.cpp:455
llvm::createAArch64PostLegalizerLowering
FunctionPass * createAArch64PostLegalizerLowering()
Definition: AArch64PostLegalizerLowering.cpp:1139
AArch64TargetMachine.h
llvm::createEHContGuardCatchretPass
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::createAArch64CompressJumpTablesPass
FunctionPass * createAArch64CompressJumpTablesPass()
Definition: AArch64CompressJumpTables.cpp:186
llvm::TargetMachine::setMachineOutliner
void setMachineOutliner(bool Enable)
Definition: TargetMachine.h:261
llvm::initializeAArch64ExpandPseudoPass
void initializeAArch64ExpandPseudoPass(PassRegistry &)
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
EnableAArch64CopyPropagation
static cl::opt< bool > EnableAArch64CopyPropagation("aarch64-enable-copy-propagation", cl::desc("Enable the copy propagation with AArch64 copy instr"), cl::init(true), cl::Hidden)
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:770
llvm::initializeAArch64StorePairSuppressPass
void initializeAArch64StorePairSuppressPass(PassRegistry &)
llvm::Legalizer
Definition: Legalizer.h:36
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
EnableFalkorHWPFFix
static cl::opt< bool > EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix", cl::init(true), cl::Hidden)
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::CodeGenOpt::Aggressive
@ Aggressive
-O3
Definition: CodeGen.h:61
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:486
llvm::createAArch64StorePairSuppressPass
FunctionPass * createAArch64StorePairSuppressPass()
false
Definition: StackSlotColoring.cpp:141
llvm::Attribute::getVScaleRangeMax
std::optional< unsigned > getVScaleRangeMax() const
Returns the maximum value for the vscale_range attribute or std::nullopt when unknown.
Definition: Attributes.cpp:375
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:788
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:31
EnableAtomicTidy
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::Attribute::getVScaleRangeMin
unsigned getVScaleRangeMin() const
Returns the minimum value for the vscale_range attribute.
Definition: Attributes.cpp:369
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1354
AArch64TargetObjectFile.h
llvm::AArch64TargetMachine
Definition: AArch64TargetMachine.h:24
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createAArch64ISelDag
FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOpt::Level OptLevel)
createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG,...
Definition: AArch64ISelDAGToDAG.cpp:6028
EnableCollectLOH
static cl::opt< bool > EnableCollectLOH("aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden)
llvm::LoadStoreOpt
Definition: LoadStoreOpt.h:62
llvm::initializeAArch64SLSHardeningPass
void initializeAArch64SLSHardeningPass(PassRegistry &)
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:99
AArch64MachineScheduler.h
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:312
llvm::createAArch64IndirectThunks
FunctionPass * createAArch64IndirectThunks()
Definition: AArch64SLSHardening.cpp:438
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
AArch64MacroFusion.h
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
llvm::CodeModel::Model
Model
Definition: CodeGen.h:31
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::cl::opt< bool >
llvm::createFalkorHWPFFixPass
FunctionPass * createFalkorHWPFFixPass()
Definition: AArch64FalkorHWPFFix.cpp:838
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:97
llvm::cl::BOU_UNSET
@ BOU_UNSET
Definition: CommandLine.h:629
llvm::initializeAArch64ConditionalComparesPass
void initializeAArch64ConditionalComparesPass(PassRegistry &)
llvm::initializeAArch64SpeculationHardeningPass
void initializeAArch64SpeculationHardeningPass(PassRegistry &)
llvm::AArch64TTIImpl
Definition: AArch64TargetTransformInfo.h:42
EnableGISelLoadStoreOptPostLegal
static cl::opt< bool > EnableGISelLoadStoreOptPostLegal("aarch64-enable-gisel-ldst-postlegal", cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"), cl::init(false), cl::Hidden)
llvm::initializeAArch64PostSelectOptimizePass
void initializeAArch64PostSelectOptimizePass(PassRegistry &)
CFGuard.h
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3678
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
llvm::AArch64TargetMachine::AArch64TargetMachine
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT, bool IsLittleEndian)
Create an AArch64 architecture model.
Definition: AArch64TargetMachine.cpp:316
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
EnableGlobalMerge
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
llvm::createAArch64ExpandPseudoPass
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
Definition: AArch64ExpandPseudoInsts.cpp:1485
llvm::createAArch64RedundantCopyEliminationPass
FunctionPass * createAArch64RedundantCopyEliminationPass()
Definition: AArch64RedundantCopyElimination.cpp:494
llvm::initializeAArch64CollectLOHPass
void initializeAArch64CollectLOHPass(PassRegistry &)
llvm::initializeAArch64PostLegalizerLoweringPass
void initializeAArch64PostLegalizerLoweringPass(PassRegistry &)
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:63
LoadStoreOpt.h
computeDataLayout
static std::string computeDataLayout(const Triple &TT, const MCTargetOptions &Options, bool LittleEndian)
Definition: AArch64TargetMachine.cpp:256
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1804
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:127
EnableMCR
static cl::opt< bool > EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
llvm::AArch64FunctionInfo
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Definition: AArch64MachineFunctionInfo.h:39
llvm::TargetOptions::NoTrapAfterNoreturn
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
Definition: TargetOptions.h:284
llvm::initializeAArch64AdvSIMDScalarPass
void initializeAArch64AdvSIMDScalarPass(PassRegistry &)
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:839
llvm::createUnpackMachineBundles
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
Definition: MachineInstrBundle.cpp:81
EnableEarlyIfConversion
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
EnableCondBrTuning
static cl::opt< bool > EnableCondBrTuning("aarch64-enable-cond-br-tune", cl::desc("Enable the conditional branch tuning pass"), cl::init(true), cl::Hidden)
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
TargetPassConfig.h
Localizer.h
llvm::createAArch64MIPeepholeOptPass
FunctionPass * createAArch64MIPeepholeOptPass()
Definition: AArch64MIPeepholeOpt.cpp:596
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:966
llvm::initializeAArch64PreLegalizerCombinerPass
void initializeAArch64PreLegalizerCombinerPass(PassRegistry &)
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::createAArch64PostLegalizerCombiner
FunctionPass * createAArch64PostLegalizerCombiner(bool IsOptNone)
Definition: AArch64PostLegalizerCombiner.cpp:448
llvm::TargetOptions::TLSSize
unsigned TLSSize
Bit size of immediate TLS offsets (0 == use the default).
Definition: TargetOptions.h:287
llvm::createCFGuardCheckPass
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:307
llvm::initializeLDTLSCleanupPass
void initializeLDTLSCleanupPass(PassRegistry &)
EnableLoadStoreOpt
static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden)
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:273
llvm::CodeGenOpt::None
@ None
-O0
Definition: CodeGen.h:58
llvm::MCTargetOptions
Definition: MCTargetOptions.h:37
llvm::Reloc::DynamicNoPIC
@ DynamicNoPIC
Definition: CodeGen.h:25
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:43
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:499
EnableGEPOpt
static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:213
llvm::initializeAArch64StackTaggingPreRAPass
void initializeAArch64StackTaggingPreRAPass(PassRegistry &)
llvm::initializeAArch64PostLegalizerCombinerPass
void initializeAArch64PostLegalizerCombinerPass(PassRegistry &)
Triple.h
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:25
llvm::createAArch64SLSHardeningPass
FunctionPass * createAArch64SLSHardeningPass()
Definition: AArch64SLSHardening.cpp:398
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::createAArch64StackTaggingPreRAPass
FunctionPass * createAArch64StackTaggingPreRAPass()
Definition: AArch64StackTaggingPreRA.cpp:98
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:25
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:79
getEffectiveAArch64CodeModel
static CodeModel::Model getEffectiveAArch64CodeModel(const Triple &TT, std::optional< CodeModel::Model > CM, bool JIT)
Definition: AArch64TargetMachine.cpp:292
IRTranslator.h
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:31
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:62
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
EnableSVEIntrinsicOpts
static cl::opt< bool > EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden, cl::desc("Enable SVE intrinsic opts"), cl::init(true))
AArch64TargetTransformInfo.h
llvm::createInterleavedAccessPass
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
Definition: InterleavedAccessPass.cpp:145
llvm::AArch64TargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: AArch64TargetMachine.cpp:854
Attributes.h
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::initializeAArch64MIPeepholeOptPass
void initializeAArch64MIPeepholeOptPass(PassRegistry &)
llvm::initializeAArch64RedundantCopyEliminationPass
void initializeAArch64RedundantCopyEliminationPass(PassRegistry &)
llvm::initializeFalkorMarkStridedAccessesLegacyPass
void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry &)
llvm::initializeAArch64LoadStoreOptPass
void initializeAArch64LoadStoreOptPass(PassRegistry &)
llvm::createSelectOptimizePass
FunctionPass * createSelectOptimizePass()
This pass converts conditional moves to conditional jumps when profitable.
Definition: SelectOptimize.cpp:229
llvm::TargetMachine::setGlobalISelAbort
void setGlobalISelAbort(GlobalISelAbortMode Mode)
Definition: TargetMachine.h:258
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1282
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:156
llvm::createLoadClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1738
RegBankSelect.h
llvm::createAArch64MacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAArch64MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAArch64MacroFusionDAGMutation()); to AArch64PassConf...
Definition: AArch64MacroFusion.cpp:419
EnableCondOpt
static cl::opt< bool > EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)
Function.h
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
llvm::ARCCC::Z
@ Z
Definition: ARCInfo.h:41
llvm::createAArch64CollectLOHPass
FunctionPass * createAArch64CollectLOHPass()
Definition: AArch64CollectLOH.cpp:595
llvm::createAArch64O0PreLegalizerCombiner
FunctionPass * createAArch64O0PreLegalizerCombiner()
Definition: AArch64O0PreLegalizerCombiner.cpp:170
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:417
AArch64MCTargetDesc.h
llvm::initializeSVEIntrinsicOptsPass
void initializeSVEIntrinsicOptsPass(PassRegistry &)
llvm::TargetMachine::setGlobalISel
void setGlobalISel(bool Enable)
Definition: TargetMachine.h:257
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:164
llvm::AArch64TargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: AArch64TargetMachine.cpp:532
CFIFixup.h
llvm::createGlobalMergePass
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
Definition: GlobalMerge.cpp:692
llvm::BranchRelaxationPassID
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Definition: BranchRelaxation.cpp:121
EnableLoopDataPrefetch
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
CodeGen.h
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:31
EnableCCMP
static cl::opt< bool > EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)
llvm::cl::BOU_TRUE
@ BOU_TRUE
Definition: CommandLine.h:629
Legalizer.h
llvm::SimplifyCFGOptions
Definition: SimplifyCFGOptions.h:23
llvm::createLICMPass
Pass * createLICMPass()
Definition: LICM.cpp:353
MachineScheduler.h
AArch64Subtarget.h
EnableDeadRegisterElimination
static cl::opt< bool > EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to the zero" " register"), cl::init(true))
llvm::createAArch64AdvSIMDScalar
FunctionPass * createAArch64AdvSIMDScalar()
Definition: AArch64AdvSIMDScalarPass.cpp:409
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:197
SVEVectorBitsMinOpt
static cl::opt< unsigned > SVEVectorBitsMinOpt("aarch64-sve-vector-bits-min", cl::desc("Assume SVE vector registers are at least this big, " "with zero meaning no minimum size is assumed."), cl::init(0), cl::Hidden)
llvm::createAArch64StackTaggingPass
FunctionPass * createAArch64StackTaggingPass(bool IsOptNone)
Definition: AArch64StackTagging.cpp:348
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:143
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
llvm::createAArch64ConditionOptimizerPass
FunctionPass * createAArch64ConditionOptimizerPass()
Definition: AArch64ConditionOptimizer.cpp:133
llvm::AArch64TargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: AArch64TargetMachine.cpp:528
llvm::MachineCombinerID
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
Definition: MachineCombiner.cpp:130
TargetTransformInfo.h
llvm::createSMEABIPass
FunctionPass * createSMEABIPass()
Definition: SMEABIPass.cpp:53
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:672
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::createStoreClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1745
llvm::IRTranslator
Definition: IRTranslator.h:64
llvm::GlobalISelAbortMode::Disable
@ Disable
EnablePromoteConstant
static cl::opt< bool > EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden)
llvm::initializeAArch64ConditionOptimizerPass
void initializeAArch64ConditionOptimizerPass(PassRegistry &)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::CodeGenOpt::Level
Level
Code generation optimization level.
Definition: CodeGen.h:57
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.h:233
llvm::createInterleavedLoadCombinePass
FunctionPass * createInterleavedLoadCombinePass()
InterleavedLoadCombines Pass - This pass identifies interleaved loads and combines them into wide loa...
Definition: InterleavedLoadCombinePass.cpp:1358
llvm::TargetMachine::setSupportsDebugEntryValues
void setSupportsDebugEntryValues(bool Enable)
Definition: TargetMachine.h:267
llvm::createAArch64CleanupLocalDynamicTLSPass
FunctionPass * createAArch64CleanupLocalDynamicTLSPass()
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:264
llvm::initializeSMEABIPass
void initializeSMEABIPass(PassRegistry &)
llvm::cl::desc
Definition: CommandLine.h:411
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:395
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:120
llvm::createTypePromotionLegacyPass
FunctionPass * createTypePromotionLegacyPass()
Create IR Type Promotion pass.
Definition: TypePromotion.cpp:1030
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::createAArch64ConditionalCompares
FunctionPass * createAArch64ConditionalCompares()
Definition: AArch64ConditionalCompares.cpp:804
llvm::createFalkorMarkStridedAccessesPass
FunctionPass * createFalkorMarkStridedAccessesPass()
Definition: AArch64FalkorHWPFFix.cpp:114
TargetRegistry.h
llvm::AArch64TargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: AArch64TargetMachine.cpp:844
llvm::MachineFunctionInfo
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Definition: MachineFunction.h:95
InitializePasses.h
SVEVectorBitsMaxOpt
static cl::opt< unsigned > SVEVectorBitsMaxOpt("aarch64-sve-vector-bits-max", cl::desc("Assume SVE vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:98
llvm::yaml::AArch64FunctionInfo
Definition: AArch64MachineFunctionInfo.h:459
llvm::CodeGenOpt::Default
@ Default
-O2, -Os
Definition: CodeGen.h:60
EnableGISelLoadStoreOptPreLegal
static cl::opt< bool > EnableGISelLoadStoreOptPreLegal("aarch64-enable-gisel-ldst-prelegal", cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"), cl::init(true), cl::Hidden)
llvm::createLoopDataPrefetchPass
FunctionPass * createLoopDataPrefetchPass()
Definition: LoopDataPrefetch.cpp:152
MIParser.h
AArch64TargetInfo.h
llvm::createCFGuardLongjmpPass
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
llvm::AArch64TargetMachine::~AArch64TargetMachine
~AArch64TargetMachine() override
llvm::Localizer
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:43
llvm::AArch64TargetMachine::getSubtargetImpl
const AArch64Subtarget * getSubtargetImpl() const =delete