32#define GET_GICOMBINER_DEPS
33#include "AArch64GenPreLegalizeGICombiner.inc"
34#undef GET_GICOMBINER_DEPS
36#define DEBUG_TYPE "aarch64-prelegalizer-combiner"
39using namespace MIPatternMatch;
43#define GET_GICOMBINER_TYPES
44#include "AArch64GenPreLegalizeGICombiner.inc"
45#undef GET_GICOMBINER_TYPES
50 assert(
MI.getOpcode() == TargetOpcode::G_FCONSTANT);
52 const unsigned DstSize =
MRI.getType(DstReg).getSizeInBits();
53 if (DstSize != 32 && DstSize != 64)
59 return all_of(
MRI.use_nodbg_instructions(DstReg),
65 assert(
MI.getOpcode() == TargetOpcode::G_FCONSTANT);
67 const APFloat &ImmValAPF =
MI.getOperand(1).getFPImm()->getValueAPF();
77 assert(
MI.getOpcode() == TargetOpcode::G_ICMP && KB);
84 LLT LHSTy =
MRI.getType(LHS);
95 LLT WideTy =
MRI.getType(WideReg);
107 assert(
MI.getOpcode() == TargetOpcode::G_ICMP);
109 LLT WideTy =
MRI.getType(WideReg);
113 auto WideZero =
Builder.buildConstant(WideTy, 0);
115 MI.getOperand(2).setReg(WideReg);
116 MI.getOperand(3).setReg(WideZero.getReg(0));
126 std::pair<uint64_t, uint64_t> &MatchInfo) {
127 assert(
MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE);
129 auto &GlobalOp =
MI.getOperand(1);
130 auto *GV = GlobalOp.getGlobal();
131 if (GV->isThreadLocal())
155 for (
auto &UseInstr :
MRI.use_nodbg_instructions(Dst)) {
156 if (UseInstr.getOpcode() != TargetOpcode::G_PTR_ADD)
159 UseInstr.getOperand(2).getReg(),
MRI);
162 MinOffset = std::min(MinOffset, Cst->Value.getZExtValue());
167 uint64_t CurrOffset = GlobalOp.getOffset();
168 uint64_t NewOffset = MinOffset + CurrOffset;
169 if (NewOffset <= CurrOffset)
181 if (NewOffset >= (1 << 20))
184 Type *
T = GV->getValueType();
186 NewOffset > GV->getParent()->getDataLayout().getTypeAllocSize(
T))
188 MatchInfo = std::make_pair(NewOffset, MinOffset);
194 std::pair<uint64_t, uint64_t> &MatchInfo) {
216 std::tie(
Offset, MinOffset) = MatchInfo;
217 B.setInstrAndDebugLoc(*std::next(
MI.getIterator()));
219 auto &GlobalOp =
MI.getOperand(1);
220 auto *GV = GlobalOp.getGlobal();
221 GlobalOp.ChangeToGA(GV,
Offset, GlobalOp.getTargetFlags());
224 MI.getOperand(0).setReg(NewGVDst);
228 B.buildConstant(
LLT::scalar(64), -
static_cast<int64_t
>(MinOffset)));
261 auto &
MRI = *
B.getMRI();
270 LLT WideTy0 =
MRI.getType(Op0Wide);
271 LLT WideTy1 =
MRI.getType(Op1Wide);
273 LLT OpTy =
MRI.getType(ResVal);
280 if (Op0WideDef->
getOpcode() != TargetOpcode::G_ASSERT_ZEXT ||
281 Op1WideDef->
getOpcode() != TargetOpcode::G_ASSERT_ZEXT ||
289 (OpTySize != 8 && OpTySize != 16))
293 Register ResStatus =
MI.getOperand(1).getReg();
294 if (!
MRI.hasOneNonDBGUse(ResStatus))
297 if (CondUser->
getOpcode() != TargetOpcode::G_BRCOND)
305 if (
any_of(
MRI.use_nodbg_instructions(ResVal),
308 (I.getParent() == FailMBB || I.getParent() == CurrentMBB);
313 B.setInstrAndDebugLoc(*
MI.getNextNode());
314 MI.eraseFromParent();
317 Register AddDst =
MRI.cloneVirtualRegister(Op0Wide);
318 B.buildInstr(TargetOpcode::G_ADD, {AddDst}, {Op0Wide, Op1Wide});
322 Register CondBit =
MRI.cloneVirtualRegister(Op0Wide);
325 B.buildConstant(
LLT::scalar(32), OpTySize == 8 ? 1 << 8 : 1 << 16));
331 B.buildZExtOrTrunc(ResVal, AddDst);
335 auto OldR =
U.getParent()->getOperand(0).getReg();
337 U.getParent()->eraseFromParent();
345class AArch64PreLegalizerCombinerImpl :
public Combiner {
349 const AArch64PreLegalizerCombinerImplRuleConfig &RuleConfig;
353 AArch64PreLegalizerCombinerImpl(
356 const AArch64PreLegalizerCombinerImplRuleConfig &RuleConfig,
360 static const char *
getName() {
return "AArch6400PreLegalizerCombiner"; }
367#define GET_GICOMBINER_CLASS_MEMBERS
368#include "AArch64GenPreLegalizeGICombiner.inc"
369#undef GET_GICOMBINER_CLASS_MEMBERS
372#define GET_GICOMBINER_IMPL
373#include "AArch64GenPreLegalizeGICombiner.inc"
374#undef GET_GICOMBINER_IMPL
376AArch64PreLegalizerCombinerImpl::AArch64PreLegalizerCombinerImpl(
379 const AArch64PreLegalizerCombinerImplRuleConfig &RuleConfig,
382 :
Combiner(MF, CInfo, TPC, &KB, CSEInfo),
383 Helper(Observer,
B,
true, &KB, MDT, LI),
384 RuleConfig(RuleConfig), STI(STI),
386#include
"AArch64GenPreLegalizeGICombiner.inc"
391bool AArch64PreLegalizerCombinerImpl::tryCombineAll(
MachineInstr &
MI)
const {
392 if (tryCombineAllImpl(
MI))
395 unsigned Opc =
MI.getOpcode();
397 case TargetOpcode::G_CONCAT_VECTORS:
399 case TargetOpcode::G_SHUFFLE_VECTOR:
401 case TargetOpcode::G_UADDO:
402 return tryToSimplifyUADDO(
MI,
B, Helper, Observer);
403 case TargetOpcode::G_MEMCPY_INLINE:
405 case TargetOpcode::G_MEMCPY:
406 case TargetOpcode::G_MEMMOVE:
407 case TargetOpcode::G_MEMSET: {
410 unsigned MaxLen = CInfo.EnableOpt ? 0 : 32;
414 if (Opc == TargetOpcode::G_MEMSET)
430 AArch64PreLegalizerCombiner();
433 return "AArch64PreLegalizerCombiner";
441 AArch64PreLegalizerCombinerImplRuleConfig RuleConfig;
445void AArch64PreLegalizerCombiner::getAnalysisUsage(
AnalysisUsage &AU)
const {
458AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner()
462 if (!RuleConfig.parseCommandLineOption())
466bool AArch64PreLegalizerCombiner::runOnMachineFunction(
MachineFunction &MF) {
468 MachineFunctionProperties::Property::FailedISel))
470 auto &TPC = getAnalysis<TargetPassConfig>();
474 getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
475 auto *CSEInfo = &
Wrapper.get(TPC.getCSEConfig());
478 const auto *LI =
ST.getLegalizerInfo();
483 GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
486 nullptr, EnableOpt,
F.hasOptSize(),
488 AArch64PreLegalizerCombinerImpl Impl(MF, CInfo, &TPC, *KB, CSEInfo,
489 RuleConfig, ST, MDT, LI);
490 return Impl.combineMachineInstrs();
493char AArch64PreLegalizerCombiner::ID = 0;
495 "Combine AArch64 machine instrs before legalization",
506 return new AArch64PreLegalizerCombiner();
unsigned const MachineRegisterInfo * MRI
#define GET_GICOMBINER_CONSTRUCTOR_INITS
Combine AArch64 machine instrs before legalization
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Provides analysis for continuously CSEing during GISel passes.
This contains common combine transformations that may be used in a combine pass,or by the target else...
Option class for Targets to specify which operations are combined how and when.
This contains the base class for all Combiners generated by TableGen.
Provides analysis for querying information about KnownBits during GISel passes.
Contains matchers for matching SSA Machine Instructions.
This file declares the MachineIRBuilder class.
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
static StringRef getName(Value *V)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target-Independent Code Generator Pass Configuration Options pass.
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
APInt bitcastToAPInt() const
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const
MachineRegisterInfo::replaceRegWith() and inform the observer of the changes.
bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen=0)
Optimize memcpy intrinsics et al, e.g.
bool tryEmitMemcpyInline(MachineInstr &MI)
Emit loads and stores that perform the given memcpy.
bool tryCombineConcatVectors(MachineInstr &MI)
If MI is G_CONCAT_VECTORS, try to combine it.
bool tryCombineShuffleVector(MachineInstr &MI)
Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
virtual bool tryCombineAll(MachineInstr &I) const =0
FunctionPass class - This class is used to implement most global optimizations.
The actual analysis pass wrapper.
Simple wrapper that does the following.
Abstract class that contains various methods for clients to notify about changes.
virtual void changingInstr(MachineInstr &MI)=0
This instruction is about to be mutated in some way.
virtual void changedInstr(MachineInstr &MI)=0
This instruction was mutated in some way.
virtual void erasingInstr(MachineInstr &MI)=0
An instruction is about to be erased.
To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelKnownBitsInfoAnalysis...
unsigned computeNumSignBits(Register R, const APInt &DemandedElts, unsigned Depth=0)
bool isEquality() const
Return true if this predicate is either EQ or NE.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
Helper class to build MachineInstr.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
MachineBasicBlock * getMBB() const
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Target-Independent Code Generator Pass Configuration Options.
The instances of the Type class are immutable: once they are created, they are never changed.
A Use represents the edge between a Value definition and its users.
bool tryEmitBZero(MachineInstr &MI, MachineIRBuilder &MIRBuilder, bool MinSize)
Replace a G_MEMSET with a value of 0 with a G_BZERO instruction if it is supported and beneficial to ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
operand_type_match m_Reg()
SpecificConstantMatch m_SpecificICst(int64_t RequestedValue)
Matches a constant equal to RequestedValue.
UnaryOp_match< SrcTy, TargetOpcode::G_ZEXT > m_GZExt(const SrcTy &Src)
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
UnaryOp_match< SrcTy, TargetOpcode::G_TRUNC > m_GTrunc(const SrcTy &Src)
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createAArch64PreLegalizerCombiner()
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
void initializeAArch64PreLegalizerCombinerPass(PassRegistry &)
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
auto instrs(const MachineBasicBlock &BB)