LLVM  14.0.0git
AArch64PreLegalizerCombiner.cpp
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1 //=== lib/CodeGen/GlobalISel/AArch64PreLegalizerCombiner.cpp --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass does combining of machine instructions at the generic MI level,
10 // before the legalizer.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64GlobalISelUtils.h"
15 #include "AArch64TargetMachine.h"
27 #include "llvm/IR/Instructions.h"
28 #include "llvm/Support/Debug.h"
29 
30 #define DEBUG_TYPE "aarch64-prelegalizer-combiner"
31 
32 using namespace llvm;
33 using namespace MIPatternMatch;
34 
35 /// Return true if a G_FCONSTANT instruction is known to be better-represented
36 /// as a G_CONSTANT.
39  assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT);
40  Register DstReg = MI.getOperand(0).getReg();
41  const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
42  if (DstSize != 32 && DstSize != 64)
43  return false;
44 
45  // When we're storing a value, it doesn't matter what register bank it's on.
46  // Since not all floating point constants can be materialized using a fmov,
47  // it makes more sense to just use a GPR.
48  return all_of(MRI.use_nodbg_instructions(DstReg),
49  [](const MachineInstr &Use) { return Use.mayStore(); });
50 }
51 
52 /// Change a G_FCONSTANT into a G_CONSTANT.
54  assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT);
55  MachineIRBuilder MIB(MI);
56  const APFloat &ImmValAPF = MI.getOperand(1).getFPImm()->getValueAPF();
57  MIB.buildConstant(MI.getOperand(0).getReg(), ImmValAPF.bitcastToAPInt());
58  MI.eraseFromParent();
59 }
60 
61 /// Try to match a G_ICMP of a G_TRUNC with zero, in which the truncated bits
62 /// are sign bits. In this case, we can transform the G_ICMP to directly compare
63 /// the wide value with a zero.
65  GISelKnownBits *KB, Register &MatchInfo) {
66  assert(MI.getOpcode() == TargetOpcode::G_ICMP && KB);
67 
68  auto Pred = (CmpInst::Predicate)MI.getOperand(1).getPredicate();
69  if (!ICmpInst::isEquality(Pred))
70  return false;
71 
72  Register LHS = MI.getOperand(2).getReg();
73  LLT LHSTy = MRI.getType(LHS);
74  if (!LHSTy.isScalar())
75  return false;
76 
77  Register RHS = MI.getOperand(3).getReg();
78  Register WideReg;
79 
80  if (!mi_match(LHS, MRI, m_GTrunc(m_Reg(WideReg))) ||
82  return false;
83 
84  LLT WideTy = MRI.getType(WideReg);
85  if (KB->computeNumSignBits(WideReg) <=
86  WideTy.getSizeInBits() - LHSTy.getSizeInBits())
87  return false;
88 
89  MatchInfo = WideReg;
90  return true;
91 }
92 
95  GISelChangeObserver &Observer,
96  Register &WideReg) {
97  assert(MI.getOpcode() == TargetOpcode::G_ICMP);
98 
99  LLT WideTy = MRI.getType(WideReg);
100  // We're going to directly use the wide register as the LHS, and then use an
101  // equivalent size zero for RHS.
102  Builder.setInstrAndDebugLoc(MI);
103  auto WideZero = Builder.buildConstant(WideTy, 0);
104  Observer.changingInstr(MI);
105  MI.getOperand(2).setReg(WideReg);
106  MI.getOperand(3).setReg(WideZero.getReg(0));
107  Observer.changedInstr(MI);
108  return true;
109 }
110 
111 /// \returns true if it is possible to fold a constant into a G_GLOBAL_VALUE.
112 ///
113 /// e.g.
114 ///
115 /// %g = G_GLOBAL_VALUE @x -> %g = G_GLOBAL_VALUE @x + cst
117  std::pair<uint64_t, uint64_t> &MatchInfo) {
118  assert(MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE);
119  MachineFunction &MF = *MI.getMF();
120  auto &GlobalOp = MI.getOperand(1);
121  auto *GV = GlobalOp.getGlobal();
122  if (GV->isThreadLocal())
123  return false;
124 
125  // Don't allow anything that could represent offsets etc.
127  GV, MF.getTarget()) != AArch64II::MO_NO_FLAG)
128  return false;
129 
130  // Look for a G_GLOBAL_VALUE only used by G_PTR_ADDs against constants:
131  //
132  // %g = G_GLOBAL_VALUE @x
133  // %ptr1 = G_PTR_ADD %g, cst1
134  // %ptr2 = G_PTR_ADD %g, cst2
135  // ...
136  // %ptrN = G_PTR_ADD %g, cstN
137  //
138  // Identify the *smallest* constant. We want to be able to form this:
139  //
140  // %offset_g = G_GLOBAL_VALUE @x + min_cst
141  // %g = G_PTR_ADD %offset_g, -min_cst
142  // %ptr1 = G_PTR_ADD %g, cst1
143  // ...
144  Register Dst = MI.getOperand(0).getReg();
145  uint64_t MinOffset = -1ull;
146  for (auto &UseInstr : MRI.use_nodbg_instructions(Dst)) {
147  if (UseInstr.getOpcode() != TargetOpcode::G_PTR_ADD)
148  return false;
150  UseInstr.getOperand(2).getReg(), MRI);
151  if (!Cst)
152  return false;
153  MinOffset = std::min(MinOffset, Cst->Value.getZExtValue());
154  }
155 
156  // Require that the new offset is larger than the existing one to avoid
157  // infinite loops.
158  uint64_t CurrOffset = GlobalOp.getOffset();
159  uint64_t NewOffset = MinOffset + CurrOffset;
160  if (NewOffset <= CurrOffset)
161  return false;
162 
163  // Check whether folding this offset is legal. It must not go out of bounds of
164  // the referenced object to avoid violating the code model, and must be
165  // smaller than 2^21 because this is the largest offset expressible in all
166  // object formats.
167  //
168  // This check also prevents us from folding negative offsets, which will end
169  // up being treated in the same way as large positive ones. They could also
170  // cause code model violations, and aren't really common enough to matter.
171  if (NewOffset >= (1 << 21))
172  return false;
173 
174  Type *T = GV->getValueType();
175  if (!T->isSized() ||
176  NewOffset > GV->getParent()->getDataLayout().getTypeAllocSize(T))
177  return false;
178  MatchInfo = std::make_pair(NewOffset, MinOffset);
179  return true;
180 }
181 
184  GISelChangeObserver &Observer,
185  std::pair<uint64_t, uint64_t> &MatchInfo) {
186  // Change:
187  //
188  // %g = G_GLOBAL_VALUE @x
189  // %ptr1 = G_PTR_ADD %g, cst1
190  // %ptr2 = G_PTR_ADD %g, cst2
191  // ...
192  // %ptrN = G_PTR_ADD %g, cstN
193  //
194  // To:
195  //
196  // %offset_g = G_GLOBAL_VALUE @x + min_cst
197  // %g = G_PTR_ADD %offset_g, -min_cst
198  // %ptr1 = G_PTR_ADD %g, cst1
199  // ...
200  // %ptrN = G_PTR_ADD %g, cstN
201  //
202  // Then, the original G_PTR_ADDs should be folded later on so that they look
203  // like this:
204  //
205  // %ptrN = G_PTR_ADD %offset_g, cstN - min_cst
206  uint64_t Offset, MinOffset;
207  std::tie(Offset, MinOffset) = MatchInfo;
208  B.setInstrAndDebugLoc(MI);
209  Observer.changingInstr(MI);
210  auto &GlobalOp = MI.getOperand(1);
211  auto *GV = GlobalOp.getGlobal();
212  GlobalOp.ChangeToGA(GV, Offset, GlobalOp.getTargetFlags());
213  Register Dst = MI.getOperand(0).getReg();
214  Register NewGVDst = MRI.cloneVirtualRegister(Dst);
215  MI.getOperand(0).setReg(NewGVDst);
216  Observer.changedInstr(MI);
217  B.buildPtrAdd(
218  Dst, NewGVDst,
219  B.buildConstant(LLT::scalar(64), -static_cast<int64_t>(MinOffset)));
220  return true;
221 }
222 
224  CombinerHelper &Helper,
225  GISelChangeObserver &Observer) {
226  // Try simplify G_UADDO with 8 or 16 bit operands to wide G_ADD and TBNZ if
227  // result is only used in the no-overflow case. It is restricted to cases
228  // where we know that the high-bits of the operands are 0. If there's an
229  // overflow, then the the 9th or 17th bit must be set, which can be checked
230  // using TBNZ.
231  //
232  // Change (for UADDOs on 8 and 16 bits):
233  //
234  // %z0 = G_ASSERT_ZEXT _
235  // %op0 = G_TRUNC %z0
236  // %z1 = G_ASSERT_ZEXT _
237  // %op1 = G_TRUNC %z1
238  // %val, %cond = G_UADDO %op0, %op1
239  // G_BRCOND %cond, %error.bb
240  //
241  // error.bb:
242  // (no successors and no uses of %val)
243  //
244  // To:
245  //
246  // %z0 = G_ASSERT_ZEXT _
247  // %z1 = G_ASSERT_ZEXT _
248  // %add = G_ADD %z0, %z1
249  // %val = G_TRUNC %add
250  // %bit = G_AND %add, 1 << scalar-size-in-bits(%op1)
251  // %cond = G_ICMP NE, %bit, 0
252  // G_BRCOND %cond, %error.bb
253 
254  auto &MRI = *B.getMRI();
255 
256  MachineOperand *DefOp0 = MRI.getOneDef(MI.getOperand(2).getReg());
257  MachineOperand *DefOp1 = MRI.getOneDef(MI.getOperand(3).getReg());
258  Register Op0Wide;
259  Register Op1Wide;
260  if (!mi_match(DefOp0->getParent(), MRI, m_GTrunc(m_Reg(Op0Wide))) ||
261  !mi_match(DefOp1->getParent(), MRI, m_GTrunc(m_Reg(Op1Wide))))
262  return false;
263  LLT WideTy0 = MRI.getType(Op0Wide);
264  LLT WideTy1 = MRI.getType(Op1Wide);
265  Register ResVal = MI.getOperand(0).getReg();
266  LLT OpTy = MRI.getType(ResVal);
267  MachineInstr *Op0WideDef = MRI.getVRegDef(Op0Wide);
268  MachineInstr *Op1WideDef = MRI.getVRegDef(Op1Wide);
269 
270  unsigned OpTySize = OpTy.getScalarSizeInBits();
271  // First check that the G_TRUNC feeding the G_UADDO are no-ops, because the
272  // inputs have been zero-extended.
273  if (Op0WideDef->getOpcode() != TargetOpcode::G_ASSERT_ZEXT ||
274  Op1WideDef->getOpcode() != TargetOpcode::G_ASSERT_ZEXT ||
275  OpTySize != Op0WideDef->getOperand(2).getImm() ||
276  OpTySize != Op1WideDef->getOperand(2).getImm())
277  return false;
278 
279  // Only scalar UADDO with either 8 or 16 bit operands are handled.
280  if (!WideTy0.isScalar() || !WideTy1.isScalar() || WideTy0 != WideTy1 ||
281  OpTySize >= WideTy0.getScalarSizeInBits() ||
282  (OpTySize != 8 && OpTySize != 16))
283  return false;
284 
285  // The overflow-status result must be used by a branch only.
286  Register ResStatus = MI.getOperand(1).getReg();
287  if (!MRI.hasOneNonDBGUse(ResStatus))
288  return false;
289  MachineInstr *CondUser = &*MRI.use_instr_nodbg_begin(ResStatus);
290  if (CondUser->getOpcode() != TargetOpcode::G_BRCOND)
291  return false;
292 
293  // Make sure the computed result is only used in the no-overflow blocks.
294  MachineBasicBlock *CurrentMBB = MI.getParent();
295  MachineBasicBlock *FailMBB = CondUser->getOperand(1).getMBB();
296  if (!FailMBB->succ_empty() || CondUser->getParent() != CurrentMBB)
297  return false;
298  if (any_of(MRI.use_nodbg_instructions(ResVal),
299  [&MI, FailMBB, CurrentMBB](MachineInstr &I) {
300  return &MI != &I &&
301  (I.getParent() == FailMBB || I.getParent() == CurrentMBB);
302  }))
303  return false;
304 
305  // Remove G_ADDO.
306  B.setInstrAndDebugLoc(*MI.getNextNode());
307  MI.eraseFromParent();
308 
309  // Emit wide add.
310  Register AddDst = MRI.cloneVirtualRegister(Op0Wide);
311  B.buildInstr(TargetOpcode::G_ADD, {AddDst}, {Op0Wide, Op1Wide});
312 
313  // Emit check of the 9th or 17th bit and update users (the branch). This will
314  // later be folded to TBNZ.
315  Register CondBit = MRI.cloneVirtualRegister(Op0Wide);
316  B.buildAnd(
317  CondBit, AddDst,
318  B.buildConstant(LLT::scalar(32), OpTySize == 8 ? 1 << 8 : 1 << 16));
319  B.buildICmp(CmpInst::ICMP_NE, ResStatus, CondBit,
320  B.buildConstant(LLT::scalar(32), 0));
321 
322  // Update ZEXts users of the result value. Because all uses are in the
323  // no-overflow case, we know that the top bits are 0 and we can ignore ZExts.
324  B.buildZExtOrTrunc(ResVal, AddDst);
326  Register WideReg;
327  if (mi_match(U.getParent(), MRI, m_GZExt(m_Reg(WideReg)))) {
328  auto OldR = U.getParent()->getOperand(0).getReg();
329  Observer.erasingInstr(*U.getParent());
330  U.getParent()->eraseFromParent();
331  Helper.replaceRegWith(MRI, OldR, AddDst);
332  }
333  }
334 
335  return true;
336 }
337 
339 protected:
341 
342 public:
344  : Helper(Helper) {}
345 };
346 
347 #define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
348 #include "AArch64GenPreLegalizeGICombiner.inc"
349 #undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
350 
351 namespace {
352 #define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
353 #include "AArch64GenPreLegalizeGICombiner.inc"
354 #undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
355 
356 class AArch64PreLegalizerCombinerInfo : public CombinerInfo {
357  GISelKnownBits *KB;
359  AArch64GenPreLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
360 
361 public:
362  AArch64PreLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
364  : CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
365  /*LegalizerInfo*/ nullptr, EnableOpt, OptSize, MinSize),
366  KB(KB), MDT(MDT) {
367  if (!GeneratedRuleCfg.parseCommandLineOption())
368  report_fatal_error("Invalid rule identifier");
369  }
370 
371  virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
372  MachineIRBuilder &B) const override;
373 };
374 
376  MachineInstr &MI,
377  MachineIRBuilder &B) const {
378  CombinerHelper Helper(Observer, B, KB, MDT);
379  AArch64GenPreLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper);
380 
381  if (Generated.tryCombineAll(Observer, MI, B))
382  return true;
383 
384  unsigned Opc = MI.getOpcode();
385  switch (Opc) {
386  case TargetOpcode::G_CONCAT_VECTORS:
387  return Helper.tryCombineConcatVectors(MI);
388  case TargetOpcode::G_SHUFFLE_VECTOR:
389  return Helper.tryCombineShuffleVector(MI);
390  case TargetOpcode::G_UADDO:
391  return tryToSimplifyUADDO(MI, B, Helper, Observer);
392  case TargetOpcode::G_MEMCPY_INLINE:
393  return Helper.tryEmitMemcpyInline(MI);
394  case TargetOpcode::G_MEMCPY:
395  case TargetOpcode::G_MEMMOVE:
396  case TargetOpcode::G_MEMSET: {
397  // If we're at -O0 set a maxlen of 32 to inline, otherwise let the other
398  // heuristics decide.
399  unsigned MaxLen = EnableOpt ? 0 : 32;
400  // Try to inline memcpy type calls if optimizations are enabled.
401  if (Helper.tryCombineMemCpyFamily(MI, MaxLen))
402  return true;
403  if (Opc == TargetOpcode::G_MEMSET)
404  return llvm::AArch64GISelUtils::tryEmitBZero(MI, B, EnableMinSize);
405  return false;
406  }
407  }
408 
409  return false;
410 }
411 
412 #define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
413 #include "AArch64GenPreLegalizeGICombiner.inc"
414 #undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
415 
416 // Pass boilerplate
417 // ================
418 
419 class AArch64PreLegalizerCombiner : public MachineFunctionPass {
420 public:
421  static char ID;
422 
423  AArch64PreLegalizerCombiner();
424 
425  StringRef getPassName() const override { return "AArch64PreLegalizerCombiner"; }
426 
427  bool runOnMachineFunction(MachineFunction &MF) override;
428 
429  void getAnalysisUsage(AnalysisUsage &AU) const override;
430 };
431 } // end anonymous namespace
432 
433 void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
435  AU.setPreservesCFG();
444 }
445 
446 AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner()
448  initializeAArch64PreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
449 }
450 
451 bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
452  if (MF.getProperties().hasProperty(
453  MachineFunctionProperties::Property::FailedISel))
454  return false;
455  auto &TPC = getAnalysis<TargetPassConfig>();
456 
457  // Enable CSE.
459  getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
460  auto *CSEInfo = &Wrapper.get(TPC.getCSEConfig());
461 
462  const Function &F = MF.getFunction();
463  bool EnableOpt =
464  MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
465  GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
466  MachineDominatorTree *MDT = &getAnalysis<MachineDominatorTree>();
467  AArch64PreLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
468  F.hasMinSize(), KB, MDT);
469  Combiner C(PCInfo, &TPC);
470  return C.combineMachineInstrs(MF, CSEInfo);
471 }
472 
474 INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE,
475  "Combine AArch64 machine instrs before legalization",
476  false, false)
480 INITIALIZE_PASS_END(AArch64PreLegalizerCombiner, DEBUG_TYPE,
481  "Combine AArch64 machine instrs before legalization", false,
482  false)
483 
484 
485 namespace llvm {
487  return new AArch64PreLegalizerCombiner();
488 }
489 } // end namespace llvm
MIPatternMatch.h
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:188
llvm::GISelChangeObserver::erasingInstr
virtual void erasingInstr(MachineInstr &MI)=0
An instruction is about to be erased.
CombinerInfo.h
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bool hasProperty(Property P) const
Definition: MachineFunction.h:176
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:22
llvm::GISelCSEAnalysisWrapperPass
The actual analysis pass wrapper.
Definition: CSEInfo.h:220
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:212
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:721
llvm::MIPatternMatch::m_Reg
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Definition: MIPatternMatch.h:210
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Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
T
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Definition: Function.h:62
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Definition: AMDGPUAliasAnalysis.cpp:31
GISelKnownBits.h
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@ ICMP_NE
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Definition: InstrTypes.h:743
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Definition: MachineFunctionPass.h:30
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use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:535
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Definition: MIPatternMatch.h:507
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iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:543
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The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
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bool isEquality() const
Return true if this predicate is either EQ or NE.
Definition: Instructions.h:1285
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Definition: MachineRegisterInfo.h:469
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Definition: ELFObjHandler.cpp:80
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Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
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FunctionPass * createAArch64PreLegalizerCombiner()
Definition: AArch64PreLegalizerCombiner.cpp:486
MachineIRBuilder.h
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Definition: X86PartialReduction.cpp:74
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Definition: CombinerInfo.h:26
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Definition: AArch64PreLegalizerCombiner.cpp:223
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void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
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virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:285
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#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
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static bool applyFoldGlobalOffset(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, GISelChangeObserver &Observer, std::pair< uint64_t, uint64_t > &MatchInfo)
Definition: AArch64PreLegalizerCombiner.cpp:182
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Definition: X86PartialReduction.cpp:73
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Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1592
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#define DEBUG_TYPE
Definition: AArch64PreLegalizerCombiner.cpp:30
AArch64TargetMachine.h
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To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelKnownBitsInfoAnalysis...
Definition: GISelKnownBits.h:113
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Definition: MIPatternMatch.h:497
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Definition: MachineOperand.h:537
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const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
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TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
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INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE, "Combine AArch64 machine instrs before legalization", false, false) INITIALIZE_PASS_END(AArch64PreLegalizerCombiner
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:732
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Definition: MachineOperand.h:49
AArch64PreLegalizerCombinerHelperState
Definition: AArch64PreLegalizerCombiner.cpp:338
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::MIPatternMatch::m_SpecificICst
SpecificConstantMatch m_SpecificICst(int64_t RequestedValue)
Matches a constant equal to RequestedValue.
Definition: MIPatternMatch.h:149
llvm::GISelChangeObserver::changingInstr
virtual void changingInstr(MachineInstr &MI)=0
This instruction is about to be mutated in some way.
llvm::CombinerHelper
Definition: CombinerHelper.h:104
llvm::APFloat::bitcastToAPInt
APInt bitcastToAPInt() const
Definition: APFloat.h:1130
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MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:398
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::None
const NoneType None
Definition: None.h:23
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
AArch64PreLegalizerCombinerHelperState::AArch64PreLegalizerCombinerHelperState
AArch64PreLegalizerCombinerHelperState(CombinerHelper &Helper)
Definition: AArch64PreLegalizerCombiner.cpp:343
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::GISelChangeObserver::changedInstr
virtual void changedInstr(MachineInstr &MI)=0
This instruction was mutated in some way.
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::AArch64GISelUtils::tryEmitBZero
bool tryEmitBZero(MachineInstr &MI, MachineIRBuilder &MIRBuilder, bool MinSize)
Replace a G_MEMSET with a value of 0 with a G_BZERO instruction if it is supported and beneficial to ...
Definition: AArch64GlobalISelUtils.cpp:63
AArch64GlobalISelUtils.h
Combine
Hexagon Vector Combine
Definition: HexagonVectorCombine.cpp:1527
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Definition: APFloat.h:701
llvm::GISelKnownBits::computeNumSignBits
unsigned computeNumSignBits(Register R, const APInt &DemandedElts, unsigned Depth=0)
Definition: GISelKnownBits.cpp:590
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Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
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Definition: Combiner.h:27
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
I
#define I(x, y, z)
Definition: MD5.cpp:58
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iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:585
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@ MO_NO_FLAG
Definition: AArch64BaseInfo.h:673
matchFoldGlobalOffset
static bool matchFoldGlobalOffset(MachineInstr &MI, MachineRegisterInfo &MRI, std::pair< uint64_t, uint64_t > &MatchInfo)
Definition: AArch64PreLegalizerCombiner.cpp:116
TargetPassConfig.h
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MachineOperand * getOneDef(Register Reg) const
Returns the defining operand if there is exactly one operand defining the specified register,...
Definition: MachineRegisterInfo.h:450
llvm::initializeAArch64PreLegalizerCombinerPass
void initializeAArch64PreLegalizerCombinerPass(PassRegistry &)
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
legalization
Combine AArch64 machine instrs before legalization
Definition: AArch64PreLegalizerCombiner.cpp:481
llvm::LLT::isScalar
bool isScalar() const
Definition: LowLevelTypeImpl.h:118
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:650
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Definition: MachineFunction.h:241
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:351
CombinerHelper.h
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MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1599
matchFConstantToConstant
static bool matchFConstantToConstant(MachineInstr &MI, MachineRegisterInfo &MRI)
Return true if a G_FCONSTANT instruction is known to be better-represented as a G_CONSTANT.
Definition: AArch64PreLegalizerCombiner.cpp:37
llvm::getIConstantVRegValWithLookThrough
Optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:401
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:417
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
Combiner.h
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const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::AArch64Subtarget::ClassifyGlobalReference
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
Definition: AArch64Subtarget.cpp:281
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:637
applyFConstantToConstant
static void applyFConstantToConstant(MachineInstr &MI)
Change a G_FCONSTANT into a G_CONSTANT.
Definition: AArch64PreLegalizerCombiner.cpp:53
matchICmpRedundantTrunc
static bool matchICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, GISelKnownBits *KB, Register &MatchInfo)
Try to match a G_ICMP of a G_TRUNC with zero, in which the truncated bits are sign bits.
Definition: AArch64PreLegalizerCombiner.cpp:64
llvm::GISelCSEAnalysisWrapper
Simple wrapper that does the following.
Definition: CSEInfo.h:202
AArch64PreLegalizerCombinerHelperState::Helper
CombinerHelper & Helper
Definition: AArch64PreLegalizerCombiner.cpp:340
Instructions.h
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::MachineRegisterInfo::cloneVirtualRegister
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
Definition: MachineRegisterInfo.cpp:172
applyICmpRedundantTrunc
static bool applyICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &Builder, GISelChangeObserver &Observer, Register &WideReg)
Definition: AArch64PreLegalizerCombiner.cpp:93
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::MIPatternMatch::mi_match
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
Definition: MIPatternMatch.h:25
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:46
MachineFunction.h
combine
vector combine
Definition: VectorCombine.cpp:1218
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
Debug.h
machine
coro Split coroutine into a set of functions driving its state machine
Definition: CoroSplit.cpp:2353
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
MachineDominators.h
llvm::CombinerHelper::replaceRegWith
void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const
MachineRegisterInfo::replaceRegWith() and inform the observer of the changes.
Definition: CombinerHelper.cpp:139
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:39