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IRTranslator.h
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1 //===- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the IRTranslator pass.
10 /// This pass is responsible for translating LLVM IR into MachineInstr.
11 /// It uses target hooks to lower the ABI but aside from that, the pass
12 /// generated code is generic. This is the default translator used for
13 /// GlobalISel.
14 ///
15 /// \todo Replace the comments with actual doxygen comments.
16 //===----------------------------------------------------------------------===//
17 
18 #ifndef LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
19 #define LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
20 
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/Support/Allocator.h"
29 #include <memory>
30 #include <utility>
31 
32 namespace llvm {
33 
34 class AllocaInst;
35 class BasicBlock;
36 class CallInst;
37 class CallLowering;
38 class Constant;
39 class DataLayout;
40 class Instruction;
41 class MachineBasicBlock;
42 class MachineFunction;
43 class MachineInstr;
44 class MachineRegisterInfo;
45 class OptimizationRemarkEmitter;
46 class PHINode;
47 class TargetPassConfig;
48 class User;
49 class Value;
50 
51 // Technically the pass should run on an hypothetical MachineModule,
52 // since it should translate Global into some sort of MachineGlobal.
53 // The MachineGlobal should ultimately just be a transfer of ownership of
54 // the interesting bits that are relevant to represent a global value.
55 // That being said, we could investigate what would it cost to just duplicate
56 // the information from the LLVM IR.
57 // The idea is that ultimately we would be able to free up the memory used
58 // by the LLVM IR as soon as the translation is over.
60 public:
61  static char ID;
62 
63 private:
64  /// Interface used to lower the everything related to calls.
65  const CallLowering *CLI;
66 
67  /// This class contains the mapping between the Values to vreg related data.
68  class ValueToVRegInfo {
69  public:
70  ValueToVRegInfo() = default;
71 
72  using VRegListT = SmallVector<unsigned, 1>;
73  using OffsetListT = SmallVector<uint64_t, 1>;
74 
75  using const_vreg_iterator =
77  using const_offset_iterator =
79 
80  inline const_vreg_iterator vregs_end() const { return ValToVRegs.end(); }
81 
82  VRegListT *getVRegs(const Value &V) {
83  auto It = ValToVRegs.find(&V);
84  if (It != ValToVRegs.end())
85  return It->second;
86 
87  return insertVRegs(V);
88  }
89 
90  OffsetListT *getOffsets(const Value &V) {
91  auto It = TypeToOffsets.find(V.getType());
92  if (It != TypeToOffsets.end())
93  return It->second;
94 
95  return insertOffsets(V);
96  }
97 
98  const_vreg_iterator findVRegs(const Value &V) const {
99  return ValToVRegs.find(&V);
100  }
101 
102  bool contains(const Value &V) const {
103  return ValToVRegs.find(&V) != ValToVRegs.end();
104  }
105 
106  void reset() {
107  ValToVRegs.clear();
108  TypeToOffsets.clear();
109  VRegAlloc.DestroyAll();
110  OffsetAlloc.DestroyAll();
111  }
112 
113  private:
114  VRegListT *insertVRegs(const Value &V) {
115  assert(ValToVRegs.find(&V) == ValToVRegs.end() && "Value already exists");
116 
117  // We placement new using our fast allocator since we never try to free
118  // the vectors until translation is finished.
119  auto *VRegList = new (VRegAlloc.Allocate()) VRegListT();
120  ValToVRegs[&V] = VRegList;
121  return VRegList;
122  }
123 
124  OffsetListT *insertOffsets(const Value &V) {
125  assert(TypeToOffsets.find(V.getType()) == TypeToOffsets.end() &&
126  "Type already exists");
127 
128  auto *OffsetList = new (OffsetAlloc.Allocate()) OffsetListT();
129  TypeToOffsets[V.getType()] = OffsetList;
130  return OffsetList;
131  }
134 
135  // We store pointers to vectors here since references may be invalidated
136  // while we hold them if we stored the vectors directly.
139  };
140 
141  /// Mapping of the values of the current LLVM IR function to the related
142  /// virtual registers and offsets.
143  ValueToVRegInfo VMap;
144 
145  // N.b. it's not completely obvious that this will be sufficient for every
146  // LLVM IR construct (with "invoke" being the obvious candidate to mess up our
147  // lives.
149 
150  // One BasicBlock can be translated to multiple MachineBasicBlocks. For such
151  // BasicBlocks translated to multiple MachineBasicBlocks, MachinePreds retains
152  // a mapping between the edges arriving at the BasicBlock to the corresponding
153  // created MachineBasicBlocks. Some BasicBlocks that get translated to a
154  // single MachineBasicBlock may also end up in this Map.
155  using CFGEdge = std::pair<const BasicBlock *, const BasicBlock *>;
157 
158  // List of stubbed PHI instructions, for values and basic blocks to be filled
159  // in once all MachineBasicBlocks have been created.
161  PendingPHIs;
162 
163  /// Record of what frame index has been allocated to specified allocas for
164  /// this function.
166 
167  SwiftErrorValueTracking SwiftError;
168 
169  /// \name Methods for translating form LLVM IR to MachineInstr.
170  /// \see ::translate for general information on the translate methods.
171  /// @{
172 
173  /// Translate \p Inst into its corresponding MachineInstr instruction(s).
174  /// Insert the newly translated instruction(s) right where the CurBuilder
175  /// is set.
176  ///
177  /// The general algorithm is:
178  /// 1. Look for a virtual register for each operand or
179  /// create one.
180  /// 2 Update the VMap accordingly.
181  /// 2.alt. For constant arguments, if they are compile time constants,
182  /// produce an immediate in the right operand and do not touch
183  /// ValToReg. Actually we will go with a virtual register for each
184  /// constants because it may be expensive to actually materialize the
185  /// constant. Moreover, if the constant spans on several instructions,
186  /// CSE may not catch them.
187  /// => Update ValToVReg and remember that we saw a constant in Constants.
188  /// We will materialize all the constants in finalize.
189  /// Note: we would need to do something so that we can recognize such operand
190  /// as constants.
191  /// 3. Create the generic instruction.
192  ///
193  /// \return true if the translation succeeded.
194  bool translate(const Instruction &Inst);
195 
196  /// Materialize \p C into virtual-register \p Reg. The generic instructions
197  /// performing this materialization will be inserted into the entry block of
198  /// the function.
199  ///
200  /// \return true if the materialization succeeded.
201  bool translate(const Constant &C, unsigned Reg);
202 
203  /// Translate an LLVM bitcast into generic IR. Either a COPY or a G_BITCAST is
204  /// emitted.
205  bool translateBitCast(const User &U, MachineIRBuilder &MIRBuilder);
206 
207  /// Translate an LLVM load instruction into generic IR.
208  bool translateLoad(const User &U, MachineIRBuilder &MIRBuilder);
209 
210  /// Translate an LLVM store instruction into generic IR.
211  bool translateStore(const User &U, MachineIRBuilder &MIRBuilder);
212 
213  /// Translate an LLVM string intrinsic (memcpy, memset, ...).
214  bool translateMemfunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
215  unsigned ID);
216 
217  void getStackGuard(unsigned DstReg, MachineIRBuilder &MIRBuilder);
218 
219  bool translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
220  MachineIRBuilder &MIRBuilder);
221 
222  /// Helper function for translateSimpleIntrinsic.
223  /// \return The generic opcode for \p IntrinsicID if \p IntrinsicID is a
224  /// simple intrinsic (ceil, fabs, etc.). Otherwise, returns
225  /// Intrinsic::not_intrinsic.
226  unsigned getSimpleIntrinsicOpcode(Intrinsic::ID ID);
227 
228  /// Translates the intrinsics defined in getSimpleIntrinsicOpcode.
229  /// \return true if the translation succeeded.
230  bool translateSimpleIntrinsic(const CallInst &CI, Intrinsic::ID ID,
231  MachineIRBuilder &MIRBuilder);
232 
233  bool translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
234  MachineIRBuilder &MIRBuilder);
235 
236  bool translateInlineAsm(const CallInst &CI, MachineIRBuilder &MIRBuilder);
237 
238  // FIXME: temporary function to expose previous interface to call lowering
239  // until it is refactored.
240  /// Combines all component registers of \p V into a single scalar with size
241  /// "max(Offsets) + last size".
242  unsigned packRegs(const Value &V, MachineIRBuilder &MIRBuilder);
243 
244  void unpackRegs(const Value &V, unsigned Src, MachineIRBuilder &MIRBuilder);
245 
246  /// Returns true if the value should be split into multiple LLTs.
247  /// If \p Offsets is given then the split type's offsets will be stored in it.
248  /// If \p Offsets is not empty it will be cleared first.
249  bool valueIsSplit(const Value &V,
251 
252  /// Translate call instruction.
253  /// \pre \p U is a call instruction.
254  bool translateCall(const User &U, MachineIRBuilder &MIRBuilder);
255 
256  bool translateInvoke(const User &U, MachineIRBuilder &MIRBuilder);
257 
258  bool translateCallBr(const User &U, MachineIRBuilder &MIRBuilder);
259 
260  bool translateLandingPad(const User &U, MachineIRBuilder &MIRBuilder);
261 
262  /// Translate one of LLVM's cast instructions into MachineInstrs, with the
263  /// given generic Opcode.
264  bool translateCast(unsigned Opcode, const User &U,
265  MachineIRBuilder &MIRBuilder);
266 
267  /// Translate a phi instruction.
268  bool translatePHI(const User &U, MachineIRBuilder &MIRBuilder);
269 
270  /// Translate a comparison (icmp or fcmp) instruction or constant.
271  bool translateCompare(const User &U, MachineIRBuilder &MIRBuilder);
272 
273  /// Translate an integer compare instruction (or constant).
274  bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) {
275  return translateCompare(U, MIRBuilder);
276  }
277 
278  /// Translate a floating-point compare instruction (or constant).
279  bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) {
280  return translateCompare(U, MIRBuilder);
281  }
282 
283  /// Add remaining operands onto phis we've translated. Executed after all
284  /// MachineBasicBlocks for the function have been created.
285  void finishPendingPhis();
286 
287  /// Translate \p Inst into a binary operation \p Opcode.
288  /// \pre \p U is a binary operation.
289  bool translateBinaryOp(unsigned Opcode, const User &U,
290  MachineIRBuilder &MIRBuilder);
291 
292  /// Translate branch (br) instruction.
293  /// \pre \p U is a branch instruction.
294  bool translateBr(const User &U, MachineIRBuilder &MIRBuilder);
295 
296  bool translateSwitch(const User &U, MachineIRBuilder &MIRBuilder);
297 
298  bool translateIndirectBr(const User &U, MachineIRBuilder &MIRBuilder);
299 
300  bool translateExtractValue(const User &U, MachineIRBuilder &MIRBuilder);
301 
302  bool translateInsertValue(const User &U, MachineIRBuilder &MIRBuilder);
303 
304  bool translateSelect(const User &U, MachineIRBuilder &MIRBuilder);
305 
306  bool translateGetElementPtr(const User &U, MachineIRBuilder &MIRBuilder);
307 
308  bool translateAlloca(const User &U, MachineIRBuilder &MIRBuilder);
309 
310  /// Translate return (ret) instruction.
311  /// The target needs to implement CallLowering::lowerReturn for
312  /// this to succeed.
313  /// \pre \p U is a return instruction.
314  bool translateRet(const User &U, MachineIRBuilder &MIRBuilder);
315 
316  bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder);
317 
318  bool translateFNeg(const User &U, MachineIRBuilder &MIRBuilder);
319 
320  bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) {
321  return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder);
322  }
323  bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) {
324  return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder);
325  }
326  bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) {
327  return translateBinaryOp(TargetOpcode::G_AND, U, MIRBuilder);
328  }
329  bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) {
330  return translateBinaryOp(TargetOpcode::G_MUL, U, MIRBuilder);
331  }
332  bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) {
333  return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder);
334  }
335  bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) {
336  return translateBinaryOp(TargetOpcode::G_XOR, U, MIRBuilder);
337  }
338 
339  bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) {
340  return translateBinaryOp(TargetOpcode::G_UDIV, U, MIRBuilder);
341  }
342  bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) {
343  return translateBinaryOp(TargetOpcode::G_SDIV, U, MIRBuilder);
344  }
345  bool translateURem(const User &U, MachineIRBuilder &MIRBuilder) {
346  return translateBinaryOp(TargetOpcode::G_UREM, U, MIRBuilder);
347  }
348  bool translateSRem(const User &U, MachineIRBuilder &MIRBuilder) {
349  return translateBinaryOp(TargetOpcode::G_SREM, U, MIRBuilder);
350  }
351  bool translateIntToPtr(const User &U, MachineIRBuilder &MIRBuilder) {
352  return translateCast(TargetOpcode::G_INTTOPTR, U, MIRBuilder);
353  }
354  bool translatePtrToInt(const User &U, MachineIRBuilder &MIRBuilder) {
355  return translateCast(TargetOpcode::G_PTRTOINT, U, MIRBuilder);
356  }
357  bool translateTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
358  return translateCast(TargetOpcode::G_TRUNC, U, MIRBuilder);
359  }
360  bool translateFPTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
361  return translateCast(TargetOpcode::G_FPTRUNC, U, MIRBuilder);
362  }
363  bool translateFPExt(const User &U, MachineIRBuilder &MIRBuilder) {
364  return translateCast(TargetOpcode::G_FPEXT, U, MIRBuilder);
365  }
366  bool translateFPToUI(const User &U, MachineIRBuilder &MIRBuilder) {
367  return translateCast(TargetOpcode::G_FPTOUI, U, MIRBuilder);
368  }
369  bool translateFPToSI(const User &U, MachineIRBuilder &MIRBuilder) {
370  return translateCast(TargetOpcode::G_FPTOSI, U, MIRBuilder);
371  }
372  bool translateUIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
373  return translateCast(TargetOpcode::G_UITOFP, U, MIRBuilder);
374  }
375  bool translateSIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
376  return translateCast(TargetOpcode::G_SITOFP, U, MIRBuilder);
377  }
378  bool translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder) {
379  return true;
380  }
381  bool translateSExt(const User &U, MachineIRBuilder &MIRBuilder) {
382  return translateCast(TargetOpcode::G_SEXT, U, MIRBuilder);
383  }
384 
385  bool translateZExt(const User &U, MachineIRBuilder &MIRBuilder) {
386  return translateCast(TargetOpcode::G_ZEXT, U, MIRBuilder);
387  }
388 
389  bool translateShl(const User &U, MachineIRBuilder &MIRBuilder) {
390  return translateBinaryOp(TargetOpcode::G_SHL, U, MIRBuilder);
391  }
392  bool translateLShr(const User &U, MachineIRBuilder &MIRBuilder) {
393  return translateBinaryOp(TargetOpcode::G_LSHR, U, MIRBuilder);
394  }
395  bool translateAShr(const User &U, MachineIRBuilder &MIRBuilder) {
396  return translateBinaryOp(TargetOpcode::G_ASHR, U, MIRBuilder);
397  }
398 
399  bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) {
400  return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder);
401  }
402  bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) {
403  return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder);
404  }
405  bool translateFDiv(const User &U, MachineIRBuilder &MIRBuilder) {
406  return translateBinaryOp(TargetOpcode::G_FDIV, U, MIRBuilder);
407  }
408  bool translateFRem(const User &U, MachineIRBuilder &MIRBuilder) {
409  return translateBinaryOp(TargetOpcode::G_FREM, U, MIRBuilder);
410  }
411 
412  bool translateVAArg(const User &U, MachineIRBuilder &MIRBuilder);
413 
414  bool translateInsertElement(const User &U, MachineIRBuilder &MIRBuilder);
415 
416  bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder);
417 
418  bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder);
419 
420  bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder);
421  bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder);
422 
423  // Stubs to keep the compiler happy while we implement the rest of the
424  // translation.
425  bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) {
426  return false;
427  }
428  bool translateCleanupRet(const User &U, MachineIRBuilder &MIRBuilder) {
429  return false;
430  }
431  bool translateCatchRet(const User &U, MachineIRBuilder &MIRBuilder) {
432  return false;
433  }
434  bool translateCatchSwitch(const User &U, MachineIRBuilder &MIRBuilder) {
435  return false;
436  }
437  bool translateFence(const User &U, MachineIRBuilder &MIRBuilder) {
438  return false;
439  }
440  bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) {
441  return translateCast(TargetOpcode::G_ADDRSPACE_CAST, U, MIRBuilder);
442  }
443  bool translateCleanupPad(const User &U, MachineIRBuilder &MIRBuilder) {
444  return false;
445  }
446  bool translateCatchPad(const User &U, MachineIRBuilder &MIRBuilder) {
447  return false;
448  }
449  bool translateUserOp1(const User &U, MachineIRBuilder &MIRBuilder) {
450  return false;
451  }
452  bool translateUserOp2(const User &U, MachineIRBuilder &MIRBuilder) {
453  return false;
454  }
455 
456  /// @}
457 
458  // Builder for machine instruction a la IRBuilder.
459  // I.e., compared to regular MIBuilder, this one also inserts the instruction
460  // in the current block, it can creates block, etc., basically a kind of
461  // IRBuilder, but for Machine IR.
462  // CSEMIRBuilder CurBuilder;
463  std::unique_ptr<MachineIRBuilder> CurBuilder;
464 
465  // Builder set to the entry block (just after ABI lowering instructions). Used
466  // as a convenient location for Constants.
467  // CSEMIRBuilder EntryBuilder;
468  std::unique_ptr<MachineIRBuilder> EntryBuilder;
469 
470  // The MachineFunction currently being translated.
471  MachineFunction *MF;
472 
473  /// MachineRegisterInfo used to create virtual registers.
474  MachineRegisterInfo *MRI = nullptr;
475 
476  const DataLayout *DL;
477 
478  /// Current target configuration. Controls how the pass handles errors.
479  const TargetPassConfig *TPC;
480 
481  /// Current optimization remark emitter. Used to report failures.
482  std::unique_ptr<OptimizationRemarkEmitter> ORE;
483 
484  // * Insert all the code needed to materialize the constants
485  // at the proper place. E.g., Entry block or dominator block
486  // of each constant depending on how fancy we want to be.
487  // * Clear the different maps.
488  void finalizeFunction();
489 
490  /// Get the VRegs that represent \p Val.
491  /// Non-aggregate types have just one corresponding VReg and the list can be
492  /// used as a single "unsigned". Aggregates get flattened. If such VRegs do
493  /// not exist, they are created.
494  ArrayRef<unsigned> getOrCreateVRegs(const Value &Val);
495 
496  unsigned getOrCreateVReg(const Value &Val) {
497  auto Regs = getOrCreateVRegs(Val);
498  if (Regs.empty())
499  return 0;
500  assert(Regs.size() == 1 &&
501  "attempt to get single VReg for aggregate or void");
502  return Regs[0];
503  }
504 
505  /// Allocate some vregs and offsets in the VMap. Then populate just the
506  /// offsets while leaving the vregs empty.
507  ValueToVRegInfo::VRegListT &allocateVRegs(const Value &Val);
508 
509  /// Get the frame index that represents \p Val.
510  /// If such VReg does not exist, it is created.
511  int getOrCreateFrameIndex(const AllocaInst &AI);
512 
513  /// Get the alignment of the given memory operation instruction. This will
514  /// either be the explicitly specified value or the ABI-required alignment for
515  /// the type being accessed (according to the Module's DataLayout).
516  unsigned getMemOpAlignment(const Instruction &I);
517 
518  /// Get the MachineBasicBlock that represents \p BB. Specifically, the block
519  /// returned will be the head of the translated block (suitable for branch
520  /// destinations).
521  MachineBasicBlock &getMBB(const BasicBlock &BB);
522 
523  /// Record \p NewPred as a Machine predecessor to `Edge.second`, corresponding
524  /// to `Edge.first` at the IR level. This is used when IRTranslation creates
525  /// multiple MachineBasicBlocks for a given IR block and the CFG is no longer
526  /// represented simply by the IR-level CFG.
527  void addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred);
528 
529  /// Returns the Machine IR predecessors for the given IR CFG edge. Usually
530  /// this is just the single MachineBasicBlock corresponding to the predecessor
531  /// in the IR. More complex lowering can result in multiple MachineBasicBlocks
532  /// preceding the original though (e.g. switch instructions).
533  SmallVector<MachineBasicBlock *, 1> getMachinePredBBs(CFGEdge Edge) {
534  auto RemappedEdge = MachinePreds.find(Edge);
535  if (RemappedEdge != MachinePreds.end())
536  return RemappedEdge->second;
537  return SmallVector<MachineBasicBlock *, 4>(1, &getMBB(*Edge.first));
538  }
539 
540 public:
541  // Ctor, nothing fancy.
542  IRTranslator();
543 
544  StringRef getPassName() const override { return "IRTranslator"; }
545 
546  void getAnalysisUsage(AnalysisUsage &AU) const override;
547 
548  // Algo:
549  // CallLowering = MF.subtarget.getCallLowering()
550  // F = MF.getParent()
551  // MIRBuilder.reset(MF)
552  // getMBB(F.getEntryBB())
553  // CallLowering->translateArguments(MIRBuilder, F, ValToVReg)
554  // for each bb in F
555  // getMBB(bb)
556  // for each inst in bb
557  // if (!translate(MIRBuilder, inst, ValToVReg, ConstantToSequence))
558  // report_fatal_error("Don't know how to translate input");
559  // finalize()
560  bool runOnMachineFunction(MachineFunction &MF) override;
561 };
562 
563 } // end namespace llvm
564 
565 #endif // LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Various leaf nodes.
Definition: ISDOpcodes.h:59
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1047
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
Definition: IRTranslator.h:544
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
This file defines the MallocAllocator and BumpPtrAllocator interfaces.
return AArch64::GPR64RegClass contains(Reg)
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Target-Independent Code Generator Pass Configuration Options.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
unsigned const MachineRegisterInfo * MRI
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
This is an important base class in LLVM.
Definition: Constant.h:41
This file implements a version of MachineIRBuilder which CSEs insts within a MachineBasicBlock.
Helper class to build MachineInstr.
Represent the analysis usage information of a pass.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
A BumpPtrAllocator that allows only elements of a specific type to be allocated.
Definition: Allocator.h:441
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
static char ID
Definition: IRTranslator.h:61
could "use" a pointer
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
#define I(x, y, z)
Definition: MD5.cpp:58
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
an instruction to allocate memory on the stack
Definition: Instructions.h:59