28 #define DEBUG_TYPE "aarch64-dead-defs" 30 STATISTIC(NumDeadDefsReplaced,
"Number of dead definitions replaced");
32 #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions" 79 case AArch64::LDADDB:
case AArch64::LDADDH:
80 case AArch64::LDADDW:
case AArch64::LDADDX:
81 case AArch64::LDADDLB:
case AArch64::LDADDLH:
82 case AArch64::LDADDLW:
case AArch64::LDADDLX:
83 case AArch64::LDCLRB:
case AArch64::LDCLRH:
84 case AArch64::LDCLRW:
case AArch64::LDCLRX:
85 case AArch64::LDCLRLB:
case AArch64::LDCLRLH:
86 case AArch64::LDCLRLW:
case AArch64::LDCLRLX:
87 case AArch64::LDEORB:
case AArch64::LDEORH:
88 case AArch64::LDEORW:
case AArch64::LDEORX:
89 case AArch64::LDEORLB:
case AArch64::LDEORLH:
90 case AArch64::LDEORLW:
case AArch64::LDEORLX:
91 case AArch64::LDSETB:
case AArch64::LDSETH:
92 case AArch64::LDSETW:
case AArch64::LDSETX:
93 case AArch64::LDSETLB:
case AArch64::LDSETLH:
94 case AArch64::LDSETLW:
case AArch64::LDSETLX:
95 case AArch64::LDSMAXB:
case AArch64::LDSMAXH:
96 case AArch64::LDSMAXW:
case AArch64::LDSMAXX:
97 case AArch64::LDSMAXLB:
case AArch64::LDSMAXLH:
98 case AArch64::LDSMAXLW:
case AArch64::LDSMAXLX:
99 case AArch64::LDSMINB:
case AArch64::LDSMINH:
100 case AArch64::LDSMINW:
case AArch64::LDSMINX:
101 case AArch64::LDSMINLB:
case AArch64::LDSMINLH:
102 case AArch64::LDSMINLW:
case AArch64::LDSMINLX:
103 case AArch64::LDUMAXB:
case AArch64::LDUMAXH:
104 case AArch64::LDUMAXW:
case AArch64::LDUMAXX:
105 case AArch64::LDUMAXLB:
case AArch64::LDUMAXLH:
106 case AArch64::LDUMAXLW:
case AArch64::LDUMAXLX:
107 case AArch64::LDUMINB:
case AArch64::LDUMINH:
108 case AArch64::LDUMINW:
case AArch64::LDUMINX:
109 case AArch64::LDUMINLB:
case AArch64::LDUMINLH:
110 case AArch64::LDUMINLW:
case AArch64::LDUMINLX:
116 void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
120 if (usesFrameIndex(
MI)) {
127 if (
MI.definesRegister(AArch64::XZR) ||
MI.definesRegister(AArch64::WZR)) {
132 <<
" Ignoring, XZR or WZR already used by the instruction\n");
137 LLVM_DEBUG(
dbgs() <<
" Ignoring, semantics change with xzr/wzr.\n");
150 (!MO.
isDead() && !
MRI->use_nodbg_empty(Reg)))
156 if (
MI.isRegTiedToUseOperand(
I)) {
165 }
else if (RC->
contains(AArch64::WZR))
166 NewReg = AArch64::WZR;
167 else if (RC->
contains(AArch64::XZR))
168 NewReg = AArch64::XZR;
177 ++NumDeadDefsReplaced;
187 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(
MachineFunction &MF) {
194 LLVM_DEBUG(
dbgs() <<
"***** AArch64DeadRegisterDefinitions *****\n");
197 processMachineBasicBlock(MBB);
202 return new AArch64DeadRegisterDefinitions();
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
This class represents lattice values for constants.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Describe properties that are true of each instruction in the target description file.
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
void setIsDead(bool Val=true)
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
void setReg(Register Reg)
Change the register this operand corresponds to.
virtual const TargetInstrInfo * getInstrInfo() const
TargetInstrInfo - Interface to description of machine instruction set.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static bool atomicReadDroppedOnZero(unsigned Opcode)
MachineOperand class - Representation of each machine instruction operand.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
#define AARCH64_DEAD_REG_DEF_NAME
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs", AARCH64_DEAD_REG_DEF_NAME, false, false) static bool usesFrameIndex(const MachineInstr &MI)
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
FunctionPass * createAArch64DeadRegisterDefinitions()
StringRef - Represent a constant reference to a string, i.e.
Register getReg() const
getReg - Returns the register number.
Wrapper class representing virtual and physical registers.