LLVM 19.0.0git
AArch64DeadRegisterDefinitionsPass.cpp
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1//==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file When allowed by the instruction, replace a dead definition of a GPR
9/// with the zero register. This makes the code a bit friendlier towards the
10/// hardware's register renamer.
11//===----------------------------------------------------------------------===//
12
13#include "AArch64.h"
14#include "AArch64RegisterInfo.h"
15#include "AArch64Subtarget.h"
16#include "llvm/ADT/Statistic.h"
24#include "llvm/Support/Debug.h"
26using namespace llvm;
27
28#define DEBUG_TYPE "aarch64-dead-defs"
29
30STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
31
32#define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions"
33
34namespace {
35class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
36private:
39 const TargetInstrInfo *TII;
40 bool Changed;
41 void processMachineBasicBlock(MachineBasicBlock &MBB);
42public:
43 static char ID; // Pass identification, replacement for typeid.
44 AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
47 }
48
50
51 StringRef getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
52
53 void getAnalysisUsage(AnalysisUsage &AU) const override {
54 AU.setPreservesCFG();
56 }
57};
58char AArch64DeadRegisterDefinitions::ID = 0;
59} // end anonymous namespace
60
61INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs",
62 AARCH64_DEAD_REG_DEF_NAME, false, false)
63
64static bool usesFrameIndex(const MachineInstr &MI) {
65 for (const MachineOperand &MO : MI.uses())
66 if (MO.isFI())
67 return true;
68 return false;
69}
70
71// Instructions that lose their 'read' operation for a subesquent fence acquire
72// (DMB LD) once the zero register is used.
73//
74// WARNING: The aquire variants of the instructions are also affected, but they
75// are split out into `atomicBarrierDroppedOnZero()` to support annotations on
76// assembly.
77static bool atomicReadDroppedOnZero(unsigned Opcode) {
78 switch (Opcode) {
79 case AArch64::LDADDB: case AArch64::LDADDH:
80 case AArch64::LDADDW: case AArch64::LDADDX:
81 case AArch64::LDADDLB: case AArch64::LDADDLH:
82 case AArch64::LDADDLW: case AArch64::LDADDLX:
83 case AArch64::LDCLRB: case AArch64::LDCLRH:
84 case AArch64::LDCLRW: case AArch64::LDCLRX:
85 case AArch64::LDCLRLB: case AArch64::LDCLRLH:
86 case AArch64::LDCLRLW: case AArch64::LDCLRLX:
87 case AArch64::LDEORB: case AArch64::LDEORH:
88 case AArch64::LDEORW: case AArch64::LDEORX:
89 case AArch64::LDEORLB: case AArch64::LDEORLH:
90 case AArch64::LDEORLW: case AArch64::LDEORLX:
91 case AArch64::LDSETB: case AArch64::LDSETH:
92 case AArch64::LDSETW: case AArch64::LDSETX:
93 case AArch64::LDSETLB: case AArch64::LDSETLH:
94 case AArch64::LDSETLW: case AArch64::LDSETLX:
95 case AArch64::LDSMAXB: case AArch64::LDSMAXH:
96 case AArch64::LDSMAXW: case AArch64::LDSMAXX:
97 case AArch64::LDSMAXLB: case AArch64::LDSMAXLH:
98 case AArch64::LDSMAXLW: case AArch64::LDSMAXLX:
99 case AArch64::LDSMINB: case AArch64::LDSMINH:
100 case AArch64::LDSMINW: case AArch64::LDSMINX:
101 case AArch64::LDSMINLB: case AArch64::LDSMINLH:
102 case AArch64::LDSMINLW: case AArch64::LDSMINLX:
103 case AArch64::LDUMAXB: case AArch64::LDUMAXH:
104 case AArch64::LDUMAXW: case AArch64::LDUMAXX:
105 case AArch64::LDUMAXLB: case AArch64::LDUMAXLH:
106 case AArch64::LDUMAXLW: case AArch64::LDUMAXLX:
107 case AArch64::LDUMINB: case AArch64::LDUMINH:
108 case AArch64::LDUMINW: case AArch64::LDUMINX:
109 case AArch64::LDUMINLB: case AArch64::LDUMINLH:
110 case AArch64::LDUMINLW: case AArch64::LDUMINLX:
111 return true;
112 }
113 return false;
114}
115
116void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
118 const MachineFunction &MF = *MBB.getParent();
119 for (MachineInstr &MI : MBB) {
120 if (usesFrameIndex(MI)) {
121 // We need to skip this instruction because while it appears to have a
122 // dead def it uses a frame index which might expand into a multi
123 // instruction sequence during EPI.
124 LLVM_DEBUG(dbgs() << " Ignoring, operand is frame index\n");
125 continue;
126 }
127 if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {
128 // It is not allowed to write to the same register (not even the zero
129 // register) twice in a single instruction.
131 dbgs()
132 << " Ignoring, XZR or WZR already used by the instruction\n");
133 continue;
134 }
135
136 if (atomicBarrierDroppedOnZero(MI.getOpcode()) || atomicReadDroppedOnZero(MI.getOpcode())) {
137 LLVM_DEBUG(dbgs() << " Ignoring, semantics change with xzr/wzr.\n");
138 continue;
139 }
140
141 const MCInstrDesc &Desc = MI.getDesc();
142 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
143 MachineOperand &MO = MI.getOperand(I);
144 if (!MO.isReg() || !MO.isDef())
145 continue;
146 // We should not have any relevant physreg defs that are replacable by
147 // zero before register allocation. So we just check for dead vreg defs.
148 Register Reg = MO.getReg();
149 if (!Reg.isVirtual() || (!MO.isDead() && !MRI->use_nodbg_empty(Reg)))
150 continue;
151 assert(!MO.isImplicit() && "Unexpected implicit def!");
152 LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n ";
153 MI.print(dbgs()));
154 // Be careful not to change the register if it's a tied operand.
155 if (MI.isRegTiedToUseOperand(I)) {
156 LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
157 continue;
158 }
159 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
160 unsigned NewReg;
161 if (RC == nullptr) {
162 LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
163 continue;
164 } else if (RC->contains(AArch64::WZR))
165 NewReg = AArch64::WZR;
166 else if (RC->contains(AArch64::XZR))
167 NewReg = AArch64::XZR;
168 else {
169 LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
170 continue;
171 }
172 LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n ");
173 MO.setReg(NewReg);
174 MO.setIsDead();
176 ++NumDeadDefsReplaced;
177 Changed = true;
178 // Only replace one dead register, see check for zero register above.
179 break;
180 }
181 }
182}
183
184// Scan the function for instructions that have a dead definition of a
185// register. Replace that register with the zero register when possible.
186bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
187 if (skipFunction(MF.getFunction()))
188 return false;
189
192 MRI = &MF.getRegInfo();
193 LLVM_DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
194 Changed = false;
195 for (auto &MBB : MF)
196 processMachineBasicBlock(MBB);
197 return Changed;
198}
199
201 return new AArch64DeadRegisterDefinitions();
202}
unsigned const MachineRegisterInfo * MRI
static bool atomicReadDroppedOnZero(unsigned Opcode)
#define AARCH64_DEAD_REG_DEF_NAME
aarch64 promote const
MachineBasicBlock & MBB
#define LLVM_DEBUG(X)
Definition: Debug.h:101
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:269
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
bool isImplicit() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setIsDead(bool Val=true)
void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createAArch64DeadRegisterDefinitions()
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
Description of the encoding of one expression Op.