LLVM  14.0.0git
AArch64PostLegalizerCombiner.cpp
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1 //=== AArch64PostLegalizerCombiner.cpp --------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// Post-legalization combines on generic MachineInstrs.
11 ///
12 /// The combines here must preserve instruction legality.
13 ///
14 /// Lowering combines (e.g. pseudo matching) should be handled by
15 /// AArch64PostLegalizerLowering.
16 ///
17 /// Combines which don't rely on instruction legality should go in the
18 /// AArch64PreLegalizerCombiner.
19 ///
20 //===----------------------------------------------------------------------===//
21 
22 #include "AArch64TargetMachine.h"
36 #include "llvm/Support/Debug.h"
37 
38 #define DEBUG_TYPE "aarch64-postlegalizer-combiner"
39 
40 using namespace llvm;
41 using namespace MIPatternMatch;
42 
43 /// This combine tries do what performExtractVectorEltCombine does in SDAG.
44 /// Rewrite for pairwise fadd pattern
45 /// (s32 (g_extract_vector_elt
46 /// (g_fadd (vXs32 Other)
47 /// (g_vector_shuffle (vXs32 Other) undef <1,X,...> )) 0))
48 /// ->
49 /// (s32 (g_fadd (g_extract_vector_elt (vXs32 Other) 0)
50 /// (g_extract_vector_elt (vXs32 Other) 1))
53  std::tuple<unsigned, LLT, Register> &MatchInfo) {
54  Register Src1 = MI.getOperand(1).getReg();
55  Register Src2 = MI.getOperand(2).getReg();
56  LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
57 
58  auto Cst = getIConstantVRegValWithLookThrough(Src2, MRI);
59  if (!Cst || Cst->Value != 0)
60  return false;
61  // SDAG also checks for FullFP16, but this looks to be beneficial anyway.
62 
63  // Now check for an fadd operation. TODO: expand this for integer add?
64  auto *FAddMI = getOpcodeDef(TargetOpcode::G_FADD, Src1, MRI);
65  if (!FAddMI)
66  return false;
67 
68  // If we add support for integer add, must restrict these types to just s64.
69  unsigned DstSize = DstTy.getSizeInBits();
70  if (DstSize != 16 && DstSize != 32 && DstSize != 64)
71  return false;
72 
73  Register Src1Op1 = FAddMI->getOperand(1).getReg();
74  Register Src1Op2 = FAddMI->getOperand(2).getReg();
75  MachineInstr *Shuffle =
76  getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op2, MRI);
77  MachineInstr *Other = MRI.getVRegDef(Src1Op1);
78  if (!Shuffle) {
79  Shuffle = getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op1, MRI);
80  Other = MRI.getVRegDef(Src1Op2);
81  }
82 
83  // We're looking for a shuffle that moves the second element to index 0.
84  if (Shuffle && Shuffle->getOperand(3).getShuffleMask()[0] == 1 &&
85  Other == MRI.getVRegDef(Shuffle->getOperand(1).getReg())) {
86  std::get<0>(MatchInfo) = TargetOpcode::G_FADD;
87  std::get<1>(MatchInfo) = DstTy;
88  std::get<2>(MatchInfo) = Other->getOperand(0).getReg();
89  return true;
90  }
91  return false;
92 }
93 
96  std::tuple<unsigned, LLT, Register> &MatchInfo) {
97  unsigned Opc = std::get<0>(MatchInfo);
98  assert(Opc == TargetOpcode::G_FADD && "Unexpected opcode!");
99  // We want to generate two extracts of elements 0 and 1, and add them.
100  LLT Ty = std::get<1>(MatchInfo);
101  Register Src = std::get<2>(MatchInfo);
102  LLT s64 = LLT::scalar(64);
103  B.setInstrAndDebugLoc(MI);
104  auto Elt0 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 0));
105  auto Elt1 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 1));
106  B.buildInstr(Opc, {MI.getOperand(0).getReg()}, {Elt0, Elt1});
107  MI.eraseFromParent();
108  return true;
109 }
110 
112  // TODO: check if extended build vector as well.
113  unsigned Opc = MRI.getVRegDef(R)->getOpcode();
114  return Opc == TargetOpcode::G_SEXT || Opc == TargetOpcode::G_SEXT_INREG;
115 }
116 
118  // TODO: check if extended build vector as well.
119  return MRI.getVRegDef(R)->getOpcode() == TargetOpcode::G_ZEXT;
120 }
121 
124  std::function<void(MachineIRBuilder &B, Register DstReg)> &ApplyFn) {
125  assert(MI.getOpcode() == TargetOpcode::G_MUL);
126  Register LHS = MI.getOperand(1).getReg();
127  Register RHS = MI.getOperand(2).getReg();
128  Register Dst = MI.getOperand(0).getReg();
129  const LLT Ty = MRI.getType(LHS);
130 
131  // The below optimizations require a constant RHS.
133  if (!Const)
134  return false;
135 
136  const APInt ConstValue = Const->Value.sextOrSelf(Ty.getSizeInBits());
137  // The following code is ported from AArch64ISelLowering.
138  // Multiplication of a power of two plus/minus one can be done more
139  // cheaply as as shift+add/sub. For now, this is true unilaterally. If
140  // future CPUs have a cheaper MADD instruction, this may need to be
141  // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
142  // 64-bit is 5 cycles, so this is always a win.
143  // More aggressively, some multiplications N0 * C can be lowered to
144  // shift+add+shift if the constant C = A * B where A = 2^N + 1 and B = 2^M,
145  // e.g. 6=3*2=(2+1)*2.
146  // TODO: consider lowering more cases, e.g. C = 14, -6, -14 or even 45
147  // which equals to (1+2)*16-(1+2).
148  // TrailingZeroes is used to test if the mul can be lowered to
149  // shift+add+shift.
150  unsigned TrailingZeroes = ConstValue.countTrailingZeros();
151  if (TrailingZeroes) {
152  // Conservatively do not lower to shift+add+shift if the mul might be
153  // folded into smul or umul.
154  if (MRI.hasOneNonDBGUse(LHS) &&
156  return false;
157  // Conservatively do not lower to shift+add+shift if the mul might be
158  // folded into madd or msub.
159  if (MRI.hasOneNonDBGUse(Dst)) {
161  unsigned UseOpc = UseMI.getOpcode();
162  if (UseOpc == TargetOpcode::G_ADD || UseOpc == TargetOpcode::G_PTR_ADD ||
163  UseOpc == TargetOpcode::G_SUB)
164  return false;
165  }
166  }
167  // Use ShiftedConstValue instead of ConstValue to support both shift+add/sub
168  // and shift+add+shift.
169  APInt ShiftedConstValue = ConstValue.ashr(TrailingZeroes);
170 
171  unsigned ShiftAmt, AddSubOpc;
172  // Is the shifted value the LHS operand of the add/sub?
173  bool ShiftValUseIsLHS = true;
174  // Do we need to negate the result?
175  bool NegateResult = false;
176 
177  if (ConstValue.isNonNegative()) {
178  // (mul x, 2^N + 1) => (add (shl x, N), x)
179  // (mul x, 2^N - 1) => (sub (shl x, N), x)
180  // (mul x, (2^N + 1) * 2^M) => (shl (add (shl x, N), x), M)
181  APInt SCVMinus1 = ShiftedConstValue - 1;
182  APInt CVPlus1 = ConstValue + 1;
183  if (SCVMinus1.isPowerOf2()) {
184  ShiftAmt = SCVMinus1.logBase2();
185  AddSubOpc = TargetOpcode::G_ADD;
186  } else if (CVPlus1.isPowerOf2()) {
187  ShiftAmt = CVPlus1.logBase2();
188  AddSubOpc = TargetOpcode::G_SUB;
189  } else
190  return false;
191  } else {
192  // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
193  // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
194  APInt CVNegPlus1 = -ConstValue + 1;
195  APInt CVNegMinus1 = -ConstValue - 1;
196  if (CVNegPlus1.isPowerOf2()) {
197  ShiftAmt = CVNegPlus1.logBase2();
198  AddSubOpc = TargetOpcode::G_SUB;
199  ShiftValUseIsLHS = false;
200  } else if (CVNegMinus1.isPowerOf2()) {
201  ShiftAmt = CVNegMinus1.logBase2();
202  AddSubOpc = TargetOpcode::G_ADD;
203  NegateResult = true;
204  } else
205  return false;
206  }
207 
208  if (NegateResult && TrailingZeroes)
209  return false;
210 
211  ApplyFn = [=](MachineIRBuilder &B, Register DstReg) {
212  auto Shift = B.buildConstant(LLT::scalar(64), ShiftAmt);
213  auto ShiftedVal = B.buildShl(Ty, LHS, Shift);
214 
215  Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS;
216  Register AddSubRHS = ShiftValUseIsLHS ? LHS : ShiftedVal.getReg(0);
217  auto Res = B.buildInstr(AddSubOpc, {Ty}, {AddSubLHS, AddSubRHS});
218  assert(!(NegateResult && TrailingZeroes) &&
219  "NegateResult and TrailingZeroes cannot both be true for now.");
220  // Negate the result.
221  if (NegateResult) {
222  B.buildSub(DstReg, B.buildConstant(Ty, 0), Res);
223  return;
224  }
225  // Shift the result.
226  if (TrailingZeroes) {
227  B.buildShl(DstReg, Res, B.buildConstant(LLT::scalar(64), TrailingZeroes));
228  return;
229  }
230  B.buildCopy(DstReg, Res.getReg(0));
231  };
232  return true;
233 }
234 
237  std::function<void(MachineIRBuilder &B, Register DstReg)> &ApplyFn) {
238  B.setInstrAndDebugLoc(MI);
239  ApplyFn(B, MI.getOperand(0).getReg());
240  MI.eraseFromParent();
241  return true;
242 }
243 
244 /// Try to fold a G_MERGE_VALUES of 2 s32 sources, where the second source
245 /// is a zero, into a G_ZEXT of the first.
247  auto &Merge = cast<GMerge>(MI);
248  LLT SrcTy = MRI.getType(Merge.getSourceReg(0));
249  if (SrcTy != LLT::scalar(32) || Merge.getNumSources() != 2)
250  return false;
251  return mi_match(Merge.getSourceReg(1), MRI, m_SpecificICst(0));
252 }
253 
255  MachineIRBuilder &B, GISelChangeObserver &Observer) {
256  // Mutate %d(s64) = G_MERGE_VALUES %a(s32), 0(s32)
257  // ->
258  // %d(s64) = G_ZEXT %a(s32)
259  Observer.changingInstr(MI);
260  MI.setDesc(B.getTII().get(TargetOpcode::G_ZEXT));
261  MI.RemoveOperand(2);
262  Observer.changedInstr(MI);
263 }
264 
265 /// \returns True if a G_ANYEXT instruction \p MI should be mutated to a G_ZEXT
266 /// instruction.
268  // If this is coming from a scalar compare then we can use a G_ZEXT instead of
269  // a G_ANYEXT:
270  //
271  // %cmp:_(s32) = G_[I|F]CMP ... <-- produces 0/1.
272  // %ext:_(s64) = G_ANYEXT %cmp(s32)
273  //
274  // By doing this, we can leverage more KnownBits combines.
275  assert(MI.getOpcode() == TargetOpcode::G_ANYEXT);
276  Register Dst = MI.getOperand(0).getReg();
277  Register Src = MI.getOperand(1).getReg();
278  return MRI.getType(Dst).isScalar() &&
279  mi_match(Src, MRI,
280  m_any_of(m_GICmp(m_Pred(), m_Reg(), m_Reg()),
281  m_GFCmp(m_Pred(), m_Reg(), m_Reg())));
282 }
283 
286  GISelChangeObserver &Observer) {
287  Observer.changingInstr(MI);
288  MI.setDesc(B.getTII().get(TargetOpcode::G_ZEXT));
289  Observer.changedInstr(MI);
290 }
291 
292 /// Match a 128b store of zero and split it into two 64 bit stores, for
293 /// size/performance reasons.
295  GStore &Store = cast<GStore>(MI);
296  if (!Store.isSimple())
297  return false;
298  LLT ValTy = MRI.getType(Store.getValueReg());
299  if (!ValTy.isVector() || ValTy.getSizeInBits() != 128)
300  return false;
301  if (ValTy.getSizeInBits() != Store.getMemSizeInBits())
302  return false; // Don't split truncating stores.
303  if (!MRI.hasOneNonDBGUse(Store.getValueReg()))
304  return false;
305  auto MaybeCst = isConstantOrConstantSplatVector(
306  *MRI.getVRegDef(Store.getValueReg()), MRI);
307  return MaybeCst && MaybeCst->isZero();
308 }
309 
312  GISelChangeObserver &Observer) {
313  B.setInstrAndDebugLoc(MI);
314  GStore &Store = cast<GStore>(MI);
315  assert(MRI.getType(Store.getValueReg()).isVector() &&
316  "Expected a vector store value");
317  LLT NewTy = LLT::scalar(64);
318  Register PtrReg = Store.getPointerReg();
319  auto Zero = B.buildConstant(NewTy, 0);
320  auto HighPtr = B.buildPtrAdd(MRI.getType(PtrReg), PtrReg,
321  B.buildConstant(LLT::scalar(64), 8));
322  auto &MF = *MI.getMF();
323  auto *LowMMO = MF.getMachineMemOperand(&Store.getMMO(), 0, NewTy);
324  auto *HighMMO = MF.getMachineMemOperand(&Store.getMMO(), 8, NewTy);
325  B.buildStore(Zero, PtrReg, *LowMMO);
326  B.buildStore(Zero, HighPtr, *HighMMO);
327  Store.eraseFromParent();
328 }
329 
330 #define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
331 #include "AArch64GenPostLegalizeGICombiner.inc"
332 #undef AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
333 
334 namespace {
335 #define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
336 #include "AArch64GenPostLegalizeGICombiner.inc"
337 #undef AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
338 
339 class AArch64PostLegalizerCombinerInfo : public CombinerInfo {
340  GISelKnownBits *KB;
342 
343 public:
344  AArch64GenPostLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
345 
346  AArch64PostLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
347  GISelKnownBits *KB,
349  : CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
350  /*LegalizerInfo*/ nullptr, EnableOpt, OptSize, MinSize),
351  KB(KB), MDT(MDT) {
352  if (!GeneratedRuleCfg.parseCommandLineOption())
353  report_fatal_error("Invalid rule identifier");
354  }
355 
356  virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
357  MachineIRBuilder &B) const override;
358 };
359 
361  MachineInstr &MI,
362  MachineIRBuilder &B) const {
363  const auto *LI =
364  MI.getParent()->getParent()->getSubtarget().getLegalizerInfo();
365  CombinerHelper Helper(Observer, B, KB, MDT, LI);
366  AArch64GenPostLegalizerCombinerHelper Generated(GeneratedRuleCfg);
367  return Generated.tryCombineAll(Observer, MI, B, Helper);
368 }
369 
370 #define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
371 #include "AArch64GenPostLegalizeGICombiner.inc"
372 #undef AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
373 
374 class AArch64PostLegalizerCombiner : public MachineFunctionPass {
375 public:
376  static char ID;
377 
378  AArch64PostLegalizerCombiner(bool IsOptNone = false);
379 
380  StringRef getPassName() const override {
381  return "AArch64PostLegalizerCombiner";
382  }
383 
384  bool runOnMachineFunction(MachineFunction &MF) override;
385  void getAnalysisUsage(AnalysisUsage &AU) const override;
386 
387 private:
388  bool IsOptNone;
389 };
390 } // end anonymous namespace
391 
392 void AArch64PostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
394  AU.setPreservesCFG();
398  if (!IsOptNone) {
403  }
405 }
406 
407 AArch64PostLegalizerCombiner::AArch64PostLegalizerCombiner(bool IsOptNone)
408  : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
409  initializeAArch64PostLegalizerCombinerPass(*PassRegistry::getPassRegistry());
410 }
411 
412 bool AArch64PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
413  if (MF.getProperties().hasProperty(
414  MachineFunctionProperties::Property::FailedISel))
415  return false;
417  MachineFunctionProperties::Property::Legalized) &&
418  "Expected a legalized function?");
419  auto *TPC = &getAnalysis<TargetPassConfig>();
420  const Function &F = MF.getFunction();
421  bool EnableOpt =
422  MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
423  GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
424  MachineDominatorTree *MDT =
425  IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
426  AArch64PostLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
427  F.hasMinSize(), KB, MDT);
429  getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
430  auto *CSEInfo = &Wrapper.get(TPC->getCSEConfig());
431  Combiner C(PCInfo, TPC);
432  return C.combineMachineInstrs(MF, CSEInfo);
433 }
434 
436 INITIALIZE_PASS_BEGIN(AArch64PostLegalizerCombiner, DEBUG_TYPE,
437  "Combine AArch64 MachineInstrs after legalization", false,
438  false)
441 INITIALIZE_PASS_END(AArch64PostLegalizerCombiner, DEBUG_TYPE,
442  "Combine AArch64 MachineInstrs after legalization", false,
443  false)
444 
445 namespace llvm {
447  return new AArch64PostLegalizerCombiner(IsOptNone);
448 }
449 } // end namespace llvm
MIPatternMatch.h
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Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:188
CombinerInfo.h
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Definition: AArch64PostLegalizerCombiner.cpp:51
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bool hasProperty(Property P) const
Definition: MachineFunction.h:176
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INITIALIZE_PASS_BEGIN(AArch64PostLegalizerCombiner, DEBUG_TYPE, "Combine AArch64 MachineInstrs after legalization", false, false) INITIALIZE_PASS_END(AArch64PostLegalizerCombiner
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Definition: APInt.h:425
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Definition: AArch64PostLegalizerCombiner.cpp:310
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Definition: README.txt:468
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Combine AArch64 MachineInstrs after legalization
Definition: AArch64PostLegalizerCombiner.cpp:442
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Definition: CombinerInfo.h:26
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Definition: APInt.h:317
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static bool matchSplitStoreZero128(MachineInstr &MI, MachineRegisterInfo &MRI)
Match a 128b store of zero and split it into two 64 bit stores, for size/performance reasons.
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Get the function properties.
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Definition: Utils.cpp:1125
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Matches a constant equal to RequestedValue.
Definition: MIPatternMatch.h:149
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Definition: CombinerHelper.h:104
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unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.h:1539
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Definition: MachineRegisterInfo.cpp:398
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bind_ty< CmpInst::Predicate > m_Pred(CmpInst::Predicate &P)
Definition: MIPatternMatch.h:312
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const NoneType None
Definition: None.h:23
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
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APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition: APInt.h:791
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Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::GISelChangeObserver::changedInstr
virtual void changedInstr(MachineInstr &MI)=0
This instruction was mutated in some way.
llvm::GStore
Represents a G_STORE.
Definition: GenericMachineInstrs.h:129
Combine
Hexagon Vector Combine
Definition: HexagonVectorCombine.cpp:1527
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::Combiner
Definition: Combiner.h:27
llvm::MachineRegisterInfo::use_instr_begin
use_instr_iterator use_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:477
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::APInt::logBase2
unsigned logBase2() const
Definition: APInt.h:1648
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:122
TargetPassConfig.h
MachineFunctionPass.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::createAArch64PostLegalizerCombiner
FunctionPass * createAArch64PostLegalizerCombiner(bool IsOptNone)
Definition: AArch64PostLegalizerCombiner.cpp:446
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition: MachineOperand.h:593
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print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::LLT::isScalar
bool isScalar() const
Definition: LowLevelTypeImpl.h:118
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
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Definition: MachineFunction.h:241
CombinerHelper.h
llvm::initializeAArch64PostLegalizerCombinerPass
void initializeAArch64PostLegalizerCombinerPass(PassRegistry &)
llvm::getIConstantVRegValWithLookThrough
Optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:401
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:417
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
Combiner.h
applyFoldMergeToZext
void applyFoldMergeToZext(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, GISelChangeObserver &Observer)
Definition: AArch64PostLegalizerCombiner.cpp:254
llvm::MIPatternMatch::m_any_of
Or< Preds... > m_any_of(Preds &&... preds)
Definition: MIPatternMatch.h:254
matchMutateAnyExtToZExt
static bool matchMutateAnyExtToZExt(MachineInstr &MI, MachineRegisterInfo &MRI)
Definition: AArch64PostLegalizerCombiner.cpp:267
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
applyExtractVecEltPairwiseAdd
bool applyExtractVecEltPairwiseAdd(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, std::tuple< unsigned, LLT, Register > &MatchInfo)
Definition: AArch64PostLegalizerCombiner.cpp:94
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::MIPatternMatch::m_GFCmp
CompareOp_match< Pred, LHS, RHS, TargetOpcode::G_FCMP > m_GFCmp(const Pred &P, const LHS &L, const RHS &R)
Definition: MIPatternMatch.h:590
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:637
llvm::GISelCSEAnalysisWrapper
Simple wrapper that does the following.
Definition: CSEInfo.h:202
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::MIPatternMatch::mi_match
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
Definition: MIPatternMatch.h:25
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
GISelChangeObserver.h
applyMutateAnyExtToZExt
static void applyMutateAnyExtToZExt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, GISelChangeObserver &Observer)
Definition: AArch64PostLegalizerCombiner.cpp:284
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:46
combine
vector combine
Definition: VectorCombine.cpp:1218
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
Debug.h
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1198
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:572
MachineDominators.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:39
isSignExtended
static bool isSignExtended(Register R, MachineRegisterInfo &MRI)
Definition: AArch64PostLegalizerCombiner.cpp:111