LLVM  12.0.0git
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AArch64PostLegalizerCombiner.cpp File Reference

Post-legalization combines on generic MachineInstrs. More...

#include "AArch64TargetMachine.h"
#include "llvm/CodeGen/GlobalISel/Combiner.h"
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/Support/Debug.h"
#include "AArch64GenPostLegalizeGICombiner.inc"
Include dependency graph for AArch64PostLegalizerCombiner.cpp:

Go to the source code of this file.

Namespaces

 llvm
 This class represents lattice values for constants.
 

Macros

#define DEBUG_TYPE   "aarch64-postlegalizer-combiner"
 
#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
 
#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
 
#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
 

Functions

bool matchExtractVecEltPairwiseAdd (MachineInstr &MI, MachineRegisterInfo &MRI, std::tuple< unsigned, LLT, Register > &MatchInfo)
 This combine tries do what performExtractVectorEltCombine does in SDAG. More...
 
bool applyExtractVecEltPairwiseAdd (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, std::tuple< unsigned, LLT, Register > &MatchInfo)
 
static bool isSignExtended (Register R, MachineRegisterInfo &MRI)
 
static bool isZeroExtended (Register R, MachineRegisterInfo &MRI)
 
bool matchAArch64MulConstCombine (MachineInstr &MI, MachineRegisterInfo &MRI, std::function< void(MachineIRBuilder &B, Register DstReg)> &ApplyFn)
 
bool applyAArch64MulConstCombine (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, std::function< void(MachineIRBuilder &B, Register DstReg)> &ApplyFn)
 
 INITIALIZE_PASS_BEGIN (AArch64PostLegalizerCombiner, DEBUG_TYPE, "Combine AArch64 MachineInstrs after legalization", false, false) INITIALIZE_PASS_END(AArch64PostLegalizerCombiner
 
FunctionPassllvm::createAArch64PostLegalizerCombiner (bool IsOptNone)
 

Variables

 DEBUG_TYPE
 
Combine AArch64 MachineInstrs after legalization
 
Combine AArch64 MachineInstrs after false
 

Detailed Description

Post-legalization combines on generic MachineInstrs.

The combines here must preserve instruction legality.

Lowering combines (e.g. pseudo matching) should be handled by AArch64PostLegalizerLowering.

Combines which don't rely on instruction legality should go in the AArch64PreLegalizerCombiner.

Definition in file AArch64PostLegalizerCombiner.cpp.

Macro Definition Documentation

◆ AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP

#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP

Definition at line 280 of file AArch64PostLegalizerCombiner.cpp.

◆ AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS

#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS

Definition at line 240 of file AArch64PostLegalizerCombiner.cpp.

◆ AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H

#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H

Definition at line 245 of file AArch64PostLegalizerCombiner.cpp.

◆ DEBUG_TYPE

#define DEBUG_TYPE   "aarch64-postlegalizer-combiner"

Definition at line 36 of file AArch64PostLegalizerCombiner.cpp.

Function Documentation

◆ applyAArch64MulConstCombine()

bool applyAArch64MulConstCombine ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B,
std::function< void(MachineIRBuilder &B, Register DstReg)> &  ApplyFn 
)

◆ applyExtractVecEltPairwiseAdd()

bool applyExtractVecEltPairwiseAdd ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B,
std::tuple< unsigned, LLT, Register > &  MatchInfo 
)

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN ( AArch64PostLegalizerCombiner  ,
DEBUG_TYPE  ,
"Combine AArch64 MachineInstrs after legalization ,
false  ,
false   
)

◆ isSignExtended()

static bool isSignExtended ( Register  R,
MachineRegisterInfo MRI 
)
static

◆ isZeroExtended()

static bool isZeroExtended ( Register  R,
MachineRegisterInfo MRI 
)
static

◆ matchAArch64MulConstCombine()

bool matchAArch64MulConstCombine ( MachineInstr MI,
MachineRegisterInfo MRI,
std::function< void(MachineIRBuilder &B, Register DstReg)> &  ApplyFn 
)

◆ matchExtractVecEltPairwiseAdd()

bool matchExtractVecEltPairwiseAdd ( MachineInstr MI,
MachineRegisterInfo MRI,
std::tuple< unsigned, LLT, Register > &  MatchInfo 
)

This combine tries do what performExtractVectorEltCombine does in SDAG.

Rewrite for pairwise fadd pattern (s32 (g_extract_vector_elt (g_fadd (vXs32 Other) (g_vector_shuffle (vXs32 Other) undef <1,X,...> )) 0)) -> (s32 (g_fadd (g_extract_vector_elt (vXs32 Other) 0) (g_extract_vector_elt (vXs32 Other) 1))

Definition at line 48 of file AArch64PostLegalizerCombiner.cpp.

References llvm::getConstantVRegValWithLookThrough(), llvm::getOpcodeDef(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getShuffleMask(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::MachineRegisterInfo::getVRegDef(), and Other.

Variable Documentation

◆ DEBUG_TYPE

DEBUG_TYPE

Definition at line 346 of file AArch64PostLegalizerCombiner.cpp.

◆ false

Combine AArch64 MachineInstrs after false

Definition at line 346 of file AArch64PostLegalizerCombiner.cpp.

◆ legalization

Combine AArch64 MachineInstrs after legalization

Definition at line 346 of file AArch64PostLegalizerCombiner.cpp.