LLVM  15.0.0git
CodeGenPassBuilder.h
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1 //===- Construction of codegen pass pipelines ------------------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// Interfaces for registering analysis passes, producing common pass manager
11 /// configurations, and parsing of pass pipelines.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_CODEGENPASSBUILDER_H
16 #define LLVM_CODEGEN_CODEGENPASSBUILDER_H
17 
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
33 #include "llvm/IR/PassManager.h"
34 #include "llvm/IR/Verifier.h"
35 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/Support/CodeGen.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/Error.h"
52 #include <cassert>
53 #include <type_traits>
54 #include <utility>
55 
56 namespace llvm {
57 
58 // FIXME: Dummy target independent passes definitions that have not yet been
59 // ported to new pass manager. Once they do, remove these.
60 #define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
61  struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
62  template <typename... Ts> PASS_NAME(Ts &&...) {} \
63  PreservedAnalyses run(Function &, FunctionAnalysisManager &) { \
64  return PreservedAnalyses::all(); \
65  } \
66  };
67 #define DUMMY_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
68  struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
69  template <typename... Ts> PASS_NAME(Ts &&...) {} \
70  PreservedAnalyses run(Module &, ModuleAnalysisManager &) { \
71  return PreservedAnalyses::all(); \
72  } \
73  };
74 #define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
75  struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
76  template <typename... Ts> PASS_NAME(Ts &&...) {} \
77  Error run(Module &, MachineFunctionAnalysisManager &) { \
78  return Error::success(); \
79  } \
80  PreservedAnalyses run(MachineFunction &, \
81  MachineFunctionAnalysisManager &) { \
82  llvm_unreachable("this api is to make new PM api happy"); \
83  } \
84  static AnalysisKey Key; \
85  };
86 #define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
87  struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
88  template <typename... Ts> PASS_NAME(Ts &&...) {} \
89  PreservedAnalyses run(MachineFunction &, \
90  MachineFunctionAnalysisManager &) { \
91  return PreservedAnalyses::all(); \
92  } \
93  static AnalysisKey Key; \
94  };
95 #include "MachinePassRegistry.def"
96 
97 /// This class provides access to building LLVM's passes.
98 ///
99 /// Its members provide the baseline state available to passes during their
100 /// construction. The \c MachinePassRegistry.def file specifies how to construct
101 /// all of the built-in passes, and those may reference these members during
102 /// construction.
103 template <typename DerivedT> class CodeGenPassBuilder {
104 public:
107  : TM(TM), Opt(Opts), PIC(PIC) {
108  // Target could set CGPassBuilderOption::MISchedPostRA to true to achieve
109  // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID)
110 
111  // Target should override TM.Options.EnableIPRA in their target-specific
112  // LLVMTM ctor. See TargetMachine::setGlobalISel for example.
113  if (Opt.EnableIPRA)
115 
118 
119  if (!Opt.OptimizeRegAlloc)
121  }
122 
124  raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
125  CodeGenFileType FileType) const;
126 
130  std::pair<StringRef, bool> getPassNameFromLegacyName(StringRef) const;
131 
136  }
137 
139  return PIC;
140  }
141 
142 protected:
143  template <typename PassT> using has_key_t = decltype(PassT::Key);
144 
145  template <typename PassT>
146  using is_module_pass_t = decltype(std::declval<PassT &>().run(
147  std::declval<Module &>(), std::declval<ModuleAnalysisManager &>()));
148 
149  template <typename PassT>
150  using is_function_pass_t = decltype(std::declval<PassT &>().run(
151  std::declval<Function &>(), std::declval<FunctionAnalysisManager &>()));
152 
153  // Function object to maintain state while adding codegen IR passes.
154  class AddIRPass {
155  public:
156  AddIRPass(ModulePassManager &MPM, bool DebugPM, bool Check = true)
157  : MPM(MPM) {
158  if (Check)
159  AddingFunctionPasses = false;
160  }
163  }
164 
165  // Add Function Pass
166  template <typename PassT>
167  std::enable_if_t<is_detected<is_function_pass_t, PassT>::value>
168  operator()(PassT &&Pass) {
169  if (AddingFunctionPasses && !*AddingFunctionPasses)
170  AddingFunctionPasses = true;
171  FPM.addPass(std::forward<PassT>(Pass));
172  }
173 
174  // Add Module Pass
175  template <typename PassT>
176  std::enable_if_t<is_detected<is_module_pass_t, PassT>::value &&
178  operator()(PassT &&Pass) {
179  assert((!AddingFunctionPasses || !*AddingFunctionPasses) &&
180  "could not add module pass after adding function pass");
181  MPM.addPass(std::forward<PassT>(Pass));
182  }
183 
184  private:
185  ModulePassManager &MPM;
187  // The codegen IR pipeline are mostly function passes with the exceptions of
188  // a few loop and module passes. `AddingFunctionPasses` make sures that
189  // we could only add module passes at the beginning of the pipeline. Once
190  // we begin adding function passes, we could no longer add module passes.
191  // This special-casing introduces less adaptor passes. If we have the need
192  // of adding module passes after function passes, we could change the
193  // implementation to accommodate that.
194  Optional<bool> AddingFunctionPasses;
195  };
196 
197  // Function object to maintain state while adding codegen machine passes.
199  public:
201 
202  template <typename PassT> void operator()(PassT &&Pass) {
203  static_assert(
205  "Machine function pass must define a static member variable `Key`.");
206  for (auto &C : BeforeCallbacks)
207  if (!C(&PassT::Key))
208  return;
209  PM.addPass(std::forward<PassT>(Pass));
210  for (auto &C : AfterCallbacks)
211  C(&PassT::Key);
212  }
213 
214  template <typename PassT> void insertPass(AnalysisKey *ID, PassT Pass) {
215  AfterCallbacks.emplace_back(
216  [this, ID, Pass = std::move(Pass)](AnalysisKey *PassID) {
217  if (PassID == ID)
218  this->PM.addPass(std::move(Pass));
219  });
220  }
221 
223  BeforeCallbacks.emplace_back(
224  [ID](AnalysisKey *PassID) { return PassID != ID; });
225  }
226 
228 
229  private:
231  SmallVector<llvm::unique_function<bool(AnalysisKey *)>, 4> BeforeCallbacks;
232  SmallVector<llvm::unique_function<void(AnalysisKey *)>, 4> AfterCallbacks;
233  };
234 
238 
239  /// Target override these hooks to parse target-specific analyses.
243  std::pair<StringRef, bool> getTargetPassNameFromLegacyName(StringRef) const {
244  return {"", false};
245  }
246 
247  template <typename TMC> TMC &getTM() const { return static_cast<TMC &>(TM); }
249 
250  /// Check whether or not GlobalISel should abort on error.
251  /// When this is disabled, GlobalISel will fall back on SDISel instead of
252  /// erroring out.
255  }
256 
257  /// Check whether or not a diagnostic should be emitted when GlobalISel
258  /// uses the fallback path. In other words, it will emit a diagnostic
259  /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
262  }
263 
264  /// addInstSelector - This method should install an instruction selector pass,
265  /// which converts from LLVM code to machine instructions.
267  return make_error<StringError>("addInstSelector is not overridden",
269  }
270 
271  /// Add passes that optimize instruction level parallelism for out-of-order
272  /// targets. These passes are run while the machine code is still in SSA
273  /// form, so they can use MachineTraceMetrics to control their heuristics.
274  ///
275  /// All passes added here should preserve the MachineDominatorTree,
276  /// MachineLoopInfo, and MachineTraceMetrics analyses.
277  void addILPOpts(AddMachinePass &) const {}
278 
279  /// This method may be implemented by targets that want to run passes
280  /// immediately before register allocation.
282 
283  /// addPreRewrite - Add passes to the optimized register allocation pipeline
284  /// after register allocation is complete, but before virtual registers are
285  /// rewritten to physical registers.
286  ///
287  /// These passes must preserve VirtRegMap and LiveIntervals, and when running
288  /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
289  /// When these passes run, VirtRegMap contains legal physreg assignments for
290  /// all virtual registers.
291  ///
292  /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
293  /// be honored. This is also not generally used for the the fast variant,
294  /// where the allocation and rewriting are done in one pass.
295  void addPreRewrite(AddMachinePass &) const {}
296 
297  /// Add passes to be run immediately after virtual registers are rewritten
298  /// to physical registers.
300 
301  /// This method may be implemented by targets that want to run passes after
302  /// register allocation pass pipeline but before prolog-epilog insertion.
304 
305  /// This method may be implemented by targets that want to run passes after
306  /// prolog-epilog insertion and before the second instruction scheduling pass.
307  void addPreSched2(AddMachinePass &) const {}
308 
309  /// This pass may be implemented by targets that want to run passes
310  /// immediately before machine code is emitted.
312 
313  /// Targets may add passes immediately before machine code is emitted in this
314  /// callback. This is called even later than `addPreEmitPass`.
315  // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
316  // position and remove the `2` suffix here as this callback is what
317  // `addPreEmitPass` *should* be but in reality isn't.
319 
320  /// {{@ For GlobalISel
321  ///
322 
323  /// addPreISel - This method should add any "last minute" LLVM->LLVM
324  /// passes (which are run just before instruction selector).
325  void addPreISel(AddIRPass &) const {
326  llvm_unreachable("addPreISel is not overridden");
327  }
328 
329  /// This method should install an IR translator pass, which converts from
330  /// LLVM code to machine instructions with possibly generic opcodes.
332  return make_error<StringError>("addIRTranslator is not overridden",
334  }
335 
336  /// This method may be implemented by targets that want to run passes
337  /// immediately before legalization.
339 
340  /// This method should install a legalize pass, which converts the instruction
341  /// sequence into one that can be selected by the target.
343  return make_error<StringError>("addLegalizeMachineIR is not overridden",
345  }
346 
347  /// This method may be implemented by targets that want to run passes
348  /// immediately before the register bank selection.
350 
351  /// This method should install a register bank selector pass, which
352  /// assigns register banks to virtual registers without a register
353  /// class or register banks.
355  return make_error<StringError>("addRegBankSelect is not overridden",
357  }
358 
359  /// This method may be implemented by targets that want to run passes
360  /// immediately before the (global) instruction selection.
362 
363  /// This method should install a (global) instruction selector pass, which
364  /// converts possibly generic instructions to fully target-specific
365  /// instructions, thereby constraining all generic virtual registers to
366  /// register classes.
368  return make_error<StringError>(
369  "addGlobalInstructionSelect is not overridden",
371  }
372  /// @}}
373 
374  /// High level function that adds all passes necessary to go from llvm IR
375  /// representation to the MI representation.
376  /// Adds IR based lowering and target specific optimization passes and finally
377  /// the core instruction selection passes.
378  void addISelPasses(AddIRPass &) const;
379 
380  /// Add the actual instruction selection passes. This does not include
381  /// preparation passes on IR.
382  Error addCoreISelPasses(AddMachinePass &) const;
383 
384  /// Add the complete, standard set of LLVM CodeGen passes.
385  /// Fully developed targets will not generally override this.
386  Error addMachinePasses(AddMachinePass &) const;
387 
388  /// Add passes to lower exception handling for the code generator.
389  void addPassesToHandleExceptions(AddIRPass &) const;
390 
391  /// Add common target configurable passes that perform LLVM IR to IR
392  /// transforms following machine independent optimization.
393  void addIRPasses(AddIRPass &) const;
394 
395  /// Add pass to prepare the LLVM IR for code generation. This should be done
396  /// before exception handling preparation passes.
397  void addCodeGenPrepare(AddIRPass &) const;
398 
399  /// Add common passes that perform LLVM IR to IR transforms in preparation for
400  /// instruction selection.
401  void addISelPrepare(AddIRPass &) const;
402 
403  /// Methods with trivial inline returns are convenient points in the common
404  /// codegen pass pipeline where targets may insert passes. Methods with
405  /// out-of-line standard implementations are major CodeGen stages called by
406  /// addMachinePasses. Some targets may override major stages when inserting
407  /// passes is insufficient, but maintaining overriden stages is more work.
408  ///
409 
410  /// addMachineSSAOptimization - Add standard passes that optimize machine
411  /// instructions in SSA form.
412  void addMachineSSAOptimization(AddMachinePass &) const;
413 
414  /// addFastRegAlloc - Add the minimum set of target-independent passes that
415  /// are required for fast register allocation.
416  Error addFastRegAlloc(AddMachinePass &) const;
417 
418  /// addOptimizedRegAlloc - Add passes related to register allocation.
419  /// LLVMTargetMachine provides standard regalloc passes for most targets.
420  void addOptimizedRegAlloc(AddMachinePass &) const;
421 
422  /// Add passes that optimize machine instructions after register allocation.
423  void addMachineLateOptimization(AddMachinePass &) const;
424 
425  /// addGCPasses - Add late codegen passes that analyze code for garbage
426  /// collection. This should return true if GC info should be printed after
427  /// these passes.
428  void addGCPasses(AddMachinePass &) const {}
429 
430  /// Add standard basic block placement passes.
431  void addBlockPlacement(AddMachinePass &) const;
432 
433  using CreateMCStreamer =
434  std::function<Expected<std::unique_ptr<MCStreamer>>(MCContext &)>;
436  llvm_unreachable("addAsmPrinter is not overridden");
437  }
438 
439  /// Utilities for targets to add passes to the pass manager.
440  ///
441 
442  /// createTargetRegisterAllocator - Create the register allocator pass for
443  /// this target at the current optimization level.
444  void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const;
445 
446  /// addMachinePasses helper to create the target-selected or overriden
447  /// regalloc pass.
448  void addRegAllocPass(AddMachinePass &, bool Optimized) const;
449 
450  /// Add core register alloator passes which do the actual register assignment
451  /// and rewriting. \returns true if any passes were added.
452  Error addRegAssignmentFast(AddMachinePass &) const;
453  Error addRegAssignmentOptimized(AddMachinePass &) const;
454 
455 private:
456  DerivedT &derived() { return static_cast<DerivedT &>(*this); }
457  const DerivedT &derived() const {
458  return static_cast<const DerivedT &>(*this);
459  }
460 };
461 
462 template <typename Derived>
465  raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
466  CodeGenFileType FileType) const {
467  AddIRPass addIRPass(MPM, Opt.DebugPM);
468  addISelPasses(addIRPass);
469 
470  AddMachinePass addPass(MFPM);
471  if (auto Err = addCoreISelPasses(addPass))
472  return std::move(Err);
473 
474  if (auto Err = derived().addMachinePasses(addPass))
475  return std::move(Err);
476 
477  derived().addAsmPrinter(
478  addPass, [this, &Out, DwoOut, FileType](MCContext &Ctx) {
479  return this->TM.createMCStreamer(Out, DwoOut, FileType, Ctx);
480  });
481 
482  addPass(FreeMachineFunctionPass());
483  return Error::success();
484 }
485 
487  AAManager AA;
488 
489  // The order in which these are registered determines their priority when
490  // being queried.
491 
492  switch (UseCFLAA) {
494  AA.registerFunctionAnalysis<CFLSteensAA>();
495  break;
496  case CFLAAType::Andersen:
497  AA.registerFunctionAnalysis<CFLAndersAA>();
498  break;
499  case CFLAAType::Both:
500  AA.registerFunctionAnalysis<CFLAndersAA>();
501  AA.registerFunctionAnalysis<CFLSteensAA>();
502  break;
503  default:
504  break;
505  }
506 
507  // Basic AliasAnalysis support.
508  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
509  // BasicAliasAnalysis wins if they disagree. This is intended to help
510  // support "obvious" type-punning idioms.
511  AA.registerFunctionAnalysis<TypeBasedAA>();
512  AA.registerFunctionAnalysis<ScopedNoAliasAA>();
513  AA.registerFunctionAnalysis<BasicAA>();
514 
515  return AA;
516 }
517 
518 template <typename Derived>
520  ModuleAnalysisManager &MAM) const {
521 #define MODULE_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \
522  MAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; });
523 #include "MachinePassRegistry.def"
524  derived().registerTargetAnalysis(MAM);
525 }
526 
527 template <typename Derived>
529  FunctionAnalysisManager &FAM) const {
530  FAM.registerPass([this] { return registerAAAnalyses(this->Opt.UseCFLAA); });
531 
532 #define FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \
533  FAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; });
534 #include "MachinePassRegistry.def"
535  derived().registerTargetAnalysis(FAM);
536 }
537 
538 template <typename Derived>
540  MachineFunctionAnalysisManager &MFAM) const {
541 #define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \
542  MFAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; });
543 #include "MachinePassRegistry.def"
544  derived().registerTargetAnalysis(MFAM);
545 }
546 
547 // FIXME: For new PM, use pass name directly in commandline seems good.
548 // Translate stringfied pass name to its old commandline name. Returns the
549 // matching legacy name and a boolean value indicating if the pass is a machine
550 // pass.
551 template <typename Derived>
552 std::pair<StringRef, bool>
554  std::pair<StringRef, bool> Ret;
555  if (Name.empty())
556  return Ret;
557 
558 #define FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
559  if (Name == NAME) \
560  Ret = {#PASS_NAME, false};
561 #define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
562  if (Name == NAME) \
563  Ret = {#PASS_NAME, false};
564 #define MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
565  if (Name == NAME) \
566  Ret = {#PASS_NAME, false};
567 #define DUMMY_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
568  if (Name == NAME) \
569  Ret = {#PASS_NAME, false};
570 #define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
571  if (Name == NAME) \
572  Ret = {#PASS_NAME, true};
573 #define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
574  if (Name == NAME) \
575  Ret = {#PASS_NAME, true};
576 #define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
577  if (Name == NAME) \
578  Ret = {#PASS_NAME, true};
579 #define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
580  if (Name == NAME) \
581  Ret = {#PASS_NAME, true};
582 #include "llvm/CodeGen/MachinePassRegistry.def"
583 
584  if (Ret.first.empty())
585  Ret = derived().getTargetPassNameFromLegacyName(Name);
586 
587  if (Ret.first.empty())
589  Twine("\" pass could not be found."));
590 
591  return Ret;
592 }
593 
594 template <typename Derived>
596  if (TM.useEmulatedTLS())
597  addPass(LowerEmuTLSPass());
598 
599  addPass(PreISelIntrinsicLoweringPass());
600 
601  derived().addIRPasses(addPass);
602  derived().addCodeGenPrepare(addPass);
603  addPassesToHandleExceptions(addPass);
604  derived().addISelPrepare(addPass);
605 }
606 
607 /// Add common target configurable passes that perform LLVM IR to IR transforms
608 /// following machine independent optimization.
609 template <typename Derived>
611  // Before running any passes, run the verifier to determine if the input
612  // coming from the front-end and/or optimizer is valid.
613  if (!Opt.DisableVerify)
614  addPass(VerifierPass());
615 
616  // Run loop strength reduction before anything else.
617  if (getOptLevel() != CodeGenOpt::None && !Opt.DisableLSR) {
619  LoopStrengthReducePass(), /*UseMemorySSA*/ true, Opt.DebugPM));
620  // FIXME: use -stop-after so we could remove PrintLSR
621  if (Opt.PrintLSR)
622  addPass(PrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
623  }
624 
625  if (getOptLevel() != CodeGenOpt::None) {
626  // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
627  // loads and compares. ExpandMemCmpPass then tries to expand those calls
628  // into optimally-sized loads and compares. The transforms are enabled by a
629  // target lowering hook.
630  if (!Opt.DisableMergeICmps)
631  addPass(MergeICmpsPass());
632  addPass(ExpandMemCmpPass());
633  }
634 
635  // Run GC lowering passes for builtin collectors
636  // TODO: add a pass insertion point here
637  addPass(GCLoweringPass());
638  addPass(ShadowStackGCLoweringPass());
639  addPass(LowerConstantIntrinsicsPass());
640 
641  // Make sure that no unreachable blocks are instruction selected.
642  addPass(UnreachableBlockElimPass());
643 
644  // Prepare expensive constants for SelectionDAG.
645  if (getOptLevel() != CodeGenOpt::None && !Opt.DisableConstantHoisting)
646  addPass(ConstantHoistingPass());
647 
648  // Replace calls to LLVM intrinsics (e.g., exp, log) operating on vector
649  // operands with calls to the corresponding functions in a vector library.
650  if (getOptLevel() != CodeGenOpt::None)
651  addPass(ReplaceWithVeclib());
652 
653  if (getOptLevel() != CodeGenOpt::None && !Opt.DisablePartialLibcallInlining)
654  addPass(PartiallyInlineLibCallsPass());
655 
656  // Instrument function entry and exit, e.g. with calls to mcount().
657  addPass(EntryExitInstrumenterPass(/*PostInlining=*/true));
658 
659  // Add scalarization of target's unsupported masked memory intrinsics pass.
660  // the unsupported intrinsic will be replaced with a chain of basic blocks,
661  // that stores/loads element one-by-one if the appropriate mask bit is set.
662  addPass(ScalarizeMaskedMemIntrinPass());
663 
664  // Expand reduction intrinsics into shuffle sequences if the target wants to.
665  addPass(ExpandReductionsPass());
666 
667  // Convert conditional moves to conditional jumps when profitable.
668  if (getOptLevel() != CodeGenOpt::None && !Opt.DisableSelectOptimize)
669  addPass(SelectOptimizePass());
670 }
671 
672 /// Turn exception handling constructs into something the code generators can
673 /// handle.
674 template <typename Derived>
676  AddIRPass &addPass) const {
677  const MCAsmInfo *MCAI = TM.getMCAsmInfo();
678  assert(MCAI && "No MCAsmInfo");
679  switch (MCAI->getExceptionHandlingType()) {
681  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
682  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
683  // catch info can get misplaced when a selector ends up more than one block
684  // removed from the parent invoke(s). This could happen when a landing
685  // pad is shared by multiple invokes and is also a target of a normal
686  // edge from elsewhere.
687  addPass(SjLjEHPreparePass());
692  addPass(DwarfEHPass(getOptLevel()));
693  break;
695  // We support using both GCC-style and MSVC-style exceptions on Windows, so
696  // add both preparation passes. Each pass will only actually run if it
697  // recognizes the personality function.
698  addPass(WinEHPass());
699  addPass(DwarfEHPass(getOptLevel()));
700  break;
702  // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
703  // on catchpads and cleanuppads because it does not outline them into
704  // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
705  // should remove PHIs there.
706  addPass(WinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
707  addPass(WasmEHPass());
708  break;
710  addPass(LowerInvokePass());
711 
712  // The lower invoke pass may create unreachable code. Remove it.
713  addPass(UnreachableBlockElimPass());
714  break;
715  }
716 }
717 
718 /// Add pass to prepare the LLVM IR for code generation. This should be done
719 /// before exception handling preparation passes.
720 template <typename Derived>
722  if (getOptLevel() != CodeGenOpt::None && !Opt.DisableCGP)
723  addPass(CodeGenPreparePass());
724  // TODO: Default ctor'd RewriteSymbolPass is no-op.
725  // addPass(RewriteSymbolPass());
726 }
727 
728 /// Add common passes that perform LLVM IR to IR transforms in preparation for
729 /// instruction selection.
730 template <typename Derived>
732  derived().addPreISel(addPass);
733 
734  // Add both the safe stack and the stack protection passes: each of them will
735  // only protect functions that have corresponding attributes.
736  addPass(SafeStackPass());
737  addPass(StackProtectorPass());
738 
739  if (Opt.PrintISelInput)
740  addPass(PrintFunctionPass(dbgs(),
741  "\n\n*** Final LLVM Code input to ISel ***\n"));
742 
743  // All passes which modify the LLVM IR are now complete; run the verifier
744  // to ensure that the IR is valid.
745  if (!Opt.DisableVerify)
746  addPass(VerifierPass());
747 }
748 
749 template <typename Derived>
751  AddMachinePass &addPass) const {
752  // Enable FastISel with -fast-isel, but allow that to be overridden.
753  TM.setO0WantsFastISel(Opt.EnableFastISelOption.value_or(true));
754 
755  // Determine an instruction selector.
756  enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
757  SelectorType Selector;
758 
759  if (Opt.EnableFastISelOption && *Opt.EnableFastISelOption == true)
760  Selector = SelectorType::FastISel;
761  else if ((Opt.EnableGlobalISelOption &&
762  *Opt.EnableGlobalISelOption == true) ||
763  (TM.Options.EnableGlobalISel &&
764  (!Opt.EnableGlobalISelOption ||
765  *Opt.EnableGlobalISelOption == false)))
766  Selector = SelectorType::GlobalISel;
767  else if (TM.getOptLevel() == CodeGenOpt::None && TM.getO0WantsFastISel())
768  Selector = SelectorType::FastISel;
769  else
770  Selector = SelectorType::SelectionDAG;
771 
772  // Set consistently TM.Options.EnableFastISel and EnableGlobalISel.
773  if (Selector == SelectorType::FastISel) {
774  TM.setFastISel(true);
775  TM.setGlobalISel(false);
776  } else if (Selector == SelectorType::GlobalISel) {
777  TM.setFastISel(false);
778  TM.setGlobalISel(true);
779  }
780 
781  // Add instruction selector passes.
782  if (Selector == SelectorType::GlobalISel) {
783  if (auto Err = derived().addIRTranslator(addPass))
784  return std::move(Err);
785 
786  derived().addPreLegalizeMachineIR(addPass);
787 
788  if (auto Err = derived().addLegalizeMachineIR(addPass))
789  return std::move(Err);
790 
791  // Before running the register bank selector, ask the target if it
792  // wants to run some passes.
793  derived().addPreRegBankSelect(addPass);
794 
795  if (auto Err = derived().addRegBankSelect(addPass))
796  return std::move(Err);
797 
798  derived().addPreGlobalInstructionSelect(addPass);
799 
800  if (auto Err = derived().addGlobalInstructionSelect(addPass))
801  return std::move(Err);
802 
803  // Pass to reset the MachineFunction if the ISel failed.
804  addPass(ResetMachineFunctionPass(reportDiagnosticWhenGlobalISelFallback(),
805  isGlobalISelAbortEnabled()));
806 
807  // Provide a fallback path when we do not want to abort on
808  // not-yet-supported input.
809  if (!isGlobalISelAbortEnabled())
810  if (auto Err = derived().addInstSelector(addPass))
811  return std::move(Err);
812 
813  } else if (auto Err = derived().addInstSelector(addPass))
814  return std::move(Err);
815 
816  // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
817  // FinalizeISel.
818  addPass(FinalizeISelPass());
819 
820  // // Print the instruction selected machine code...
821  // printAndVerify("After Instruction Selection");
822 
823  return Error::success();
824 }
825 
826 /// Add the complete set of target-independent postISel code generator passes.
827 ///
828 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
829 /// with nontrivial configuration or multiple passes are broken out below in
830 /// add%Stage routines.
831 ///
832 /// Any CodeGenPassBuilder<Derived>::addXX routine may be overriden by the
833 /// Target. The addPre/Post methods with empty header implementations allow
834 /// injecting target-specific fixups just before or after major stages.
835 /// Additionally, targets have the flexibility to change pass order within a
836 /// stage by overriding default implementation of add%Stage routines below. Each
837 /// technique has maintainability tradeoffs because alternate pass orders are
838 /// not well supported. addPre/Post works better if the target pass is easily
839 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
840 /// the target should override the stage instead.
841 template <typename Derived>
843  AddMachinePass &addPass) const {
844  // Add passes that optimize machine instructions in SSA form.
845  if (getOptLevel() != CodeGenOpt::None) {
846  derived().addMachineSSAOptimization(addPass);
847  } else {
848  // If the target requests it, assign local variables to stack slots relative
849  // to one another and simplify frame index references where possible.
850  addPass(LocalStackSlotPass());
851  }
852 
853  if (TM.Options.EnableIPRA)
854  addPass(RegUsageInfoPropagationPass());
855 
856  // Run pre-ra passes.
857  derived().addPreRegAlloc(addPass);
858 
859  // Run register allocation and passes that are tightly coupled with it,
860  // including phi elimination and scheduling.
861  if (*Opt.OptimizeRegAlloc) {
862  derived().addOptimizedRegAlloc(addPass);
863  } else {
864  if (auto Err = derived().addFastRegAlloc(addPass))
865  return Err;
866  }
867 
868  // Run post-ra passes.
869  derived().addPostRegAlloc(addPass);
870 
871  addPass(RemoveRedundantDebugValuesPass());
872 
873  // Insert prolog/epilog code. Eliminate abstract frame index references...
874  if (getOptLevel() != CodeGenOpt::None) {
875  addPass(PostRAMachineSinkingPass());
876  addPass(ShrinkWrapPass());
877  }
878 
879  addPass(PrologEpilogInserterPass());
880 
881  /// Add passes that optimize machine instructions after register allocation.
882  if (getOptLevel() != CodeGenOpt::None)
883  derived().addMachineLateOptimization(addPass);
884 
885  // Expand pseudo instructions before second scheduling pass.
886  addPass(ExpandPostRAPseudosPass());
887 
888  // Run pre-sched2 passes.
889  derived().addPreSched2(addPass);
890 
891  if (Opt.EnableImplicitNullChecks)
892  addPass(ImplicitNullChecksPass());
893 
894  // Second pass scheduler.
895  // Let Target optionally insert this pass by itself at some other
896  // point.
897  if (getOptLevel() != CodeGenOpt::None &&
898  !TM.targetSchedulesPostRAScheduling()) {
899  if (Opt.MISchedPostRA)
900  addPass(PostMachineSchedulerPass());
901  else
902  addPass(PostRASchedulerPass());
903  }
904 
905  // GC
906  derived().addGCPasses(addPass);
907 
908  // Basic block placement.
909  if (getOptLevel() != CodeGenOpt::None)
910  derived().addBlockPlacement(addPass);
911 
912  // Insert before XRay Instrumentation.
913  addPass(FEntryInserterPass());
914 
915  addPass(XRayInstrumentationPass());
916  addPass(PatchableFunctionPass());
917 
918  derived().addPreEmitPass(addPass);
919 
920  if (TM.Options.EnableIPRA)
921  // Collect register usage information and produce a register mask of
922  // clobbered registers, to be used to optimize call sites.
923  addPass(RegUsageInfoCollectorPass());
924 
925  addPass(FuncletLayoutPass());
926 
927  addPass(StackMapLivenessPass());
928  addPass(LiveDebugValuesPass());
929 
930  if (TM.Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
931  Opt.EnableMachineOutliner != RunOutliner::NeverOutline) {
932  bool RunOnAllFunctions =
933  (Opt.EnableMachineOutliner == RunOutliner::AlwaysOutline);
934  bool AddOutliner = RunOnAllFunctions || TM.Options.SupportsDefaultOutlining;
935  if (AddOutliner)
936  addPass(MachineOutlinerPass(RunOnAllFunctions));
937  }
938 
939  // Add passes that directly emit MI after all other MI passes.
940  derived().addPreEmitPass2(addPass);
941 
942  return Error::success();
943 }
944 
945 /// Add passes that optimize machine instructions in SSA form.
946 template <typename Derived>
948  AddMachinePass &addPass) const {
949  // Pre-ra tail duplication.
950  addPass(EarlyTailDuplicatePass());
951 
952  // Optimize PHIs before DCE: removing dead PHI cycles may make more
953  // instructions dead.
954  addPass(OptimizePHIsPass());
955 
956  // This pass merges large allocas. StackSlotColoring is a different pass
957  // which merges spill slots.
958  addPass(StackColoringPass());
959 
960  // If the target requests it, assign local variables to stack slots relative
961  // to one another and simplify frame index references where possible.
962  addPass(LocalStackSlotPass());
963 
964  // With optimization, dead code should already be eliminated. However
965  // there is one known exception: lowered code for arguments that are only
966  // used by tail calls, where the tail calls reuse the incoming stack
967  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
968  addPass(DeadMachineInstructionElimPass());
969 
970  // Allow targets to insert passes that improve instruction level parallelism,
971  // like if-conversion. Such passes will typically need dominator trees and
972  // loop info, just like LICM and CSE below.
973  derived().addILPOpts(addPass);
974 
975  addPass(EarlyMachineLICMPass());
976  addPass(MachineCSEPass());
977 
978  addPass(MachineSinkingPass());
979 
980  addPass(PeepholeOptimizerPass());
981  // Clean-up the dead code that may have been generated by peephole
982  // rewriting.
983  addPass(DeadMachineInstructionElimPass());
984 }
985 
986 //===---------------------------------------------------------------------===//
987 /// Register Allocation Pass Configuration
988 //===---------------------------------------------------------------------===//
989 
990 /// Instantiate the default register allocator pass for this target for either
991 /// the optimized or unoptimized allocation path. This will be added to the pass
992 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
993 /// in the optimized case.
994 ///
995 /// A target that uses the standard regalloc pass order for fast or optimized
996 /// allocation may still override this for per-target regalloc
997 /// selection. But -regalloc=... always takes precedence.
998 template <typename Derived>
1000  AddMachinePass &addPass, bool Optimized) const {
1001  if (Optimized)
1002  addPass(RAGreedyPass());
1003  else
1004  addPass(RAFastPass());
1005 }
1006 
1007 /// Find and instantiate the register allocation pass requested by this target
1008 /// at the current optimization level. Different register allocators are
1009 /// defined as separate passes because they may require different analysis.
1010 template <typename Derived>
1012  bool Optimized) const {
1013  if (Opt.RegAlloc == RegAllocType::Default)
1014  // With no -regalloc= override, ask the target for a regalloc pass.
1015  derived().addTargetRegisterAllocator(addPass, Optimized);
1016  else if (Opt.RegAlloc == RegAllocType::Basic)
1017  addPass(RABasicPass());
1018  else if (Opt.RegAlloc == RegAllocType::Fast)
1019  addPass(RAFastPass());
1020  else if (Opt.RegAlloc == RegAllocType::Greedy)
1021  addPass(RAGreedyPass());
1022  else if (Opt.RegAlloc == RegAllocType::PBQP)
1023  addPass(RAPBQPPass());
1024  else
1025  llvm_unreachable("unknonwn register allocator type");
1026 }
1027 
1028 template <typename Derived>
1030  AddMachinePass &addPass) const {
1031  if (Opt.RegAlloc != RegAllocType::Default &&
1032  Opt.RegAlloc != RegAllocType::Fast)
1033  return make_error<StringError>(
1034  "Must use fast (default) register allocator for unoptimized regalloc.",
1036 
1037  addRegAllocPass(addPass, false);
1038  return Error::success();
1039 }
1040 
1041 template <typename Derived>
1043  AddMachinePass &addPass) const {
1044  // Add the selected register allocation pass.
1045  addRegAllocPass(addPass, true);
1046 
1047  // Allow targets to change the register assignments before rewriting.
1048  derived().addPreRewrite(addPass);
1049 
1050  // Finally rewrite virtual registers.
1051  addPass(VirtRegRewriterPass());
1052  // Perform stack slot coloring and post-ra machine LICM.
1053  //
1054  // FIXME: Re-enable coloring with register when it's capable of adding
1055  // kill markers.
1056  addPass(StackSlotColoringPass());
1057 
1058  return Error::success();
1059 }
1060 
1061 /// Add the minimum set of target-independent passes that are required for
1062 /// register allocation. No coalescing or scheduling.
1063 template <typename Derived>
1065  AddMachinePass &addPass) const {
1066  addPass(PHIEliminationPass());
1067  addPass(TwoAddressInstructionPass());
1068  return derived().addRegAssignmentFast(addPass);
1069 }
1070 
1071 /// Add standard target-independent passes that are tightly coupled with
1072 /// optimized register allocation, including coalescing, machine instruction
1073 /// scheduling, and register allocation itself.
1074 template <typename Derived>
1076  AddMachinePass &addPass) const {
1077  addPass(DetectDeadLanesPass());
1078 
1079  addPass(ProcessImplicitDefsPass());
1080 
1081  // Edge splitting is smarter with machine loop info.
1082  addPass(PHIEliminationPass());
1083 
1084  // Eventually, we want to run LiveIntervals before PHI elimination.
1085  if (Opt.EarlyLiveIntervals)
1086  addPass(LiveIntervalsPass());
1087 
1088  addPass(TwoAddressInstructionPass());
1089  addPass(RegisterCoalescerPass());
1090 
1091  // The machine scheduler may accidentally create disconnected components
1092  // when moving subregister definitions around, avoid this by splitting them to
1093  // separate vregs before. Splitting can also improve reg. allocation quality.
1094  addPass(RenameIndependentSubregsPass());
1095 
1096  // PreRA instruction scheduling.
1097  addPass(MachineSchedulerPass());
1098 
1099  if (derived().addRegAssignmentOptimized(addPass)) {
1100  // Allow targets to expand pseudo instructions depending on the choice of
1101  // registers before MachineCopyPropagation.
1102  derived().addPostRewrite(addPass);
1103 
1104  // Copy propagate to forward register uses and try to eliminate COPYs that
1105  // were not coalesced.
1106  addPass(MachineCopyPropagationPass());
1107 
1108  // Run post-ra machine LICM to hoist reloads / remats.
1109  //
1110  // FIXME: can this move into MachineLateOptimization?
1111  addPass(MachineLICMPass());
1112  }
1113 }
1114 
1115 //===---------------------------------------------------------------------===//
1116 /// Post RegAlloc Pass Configuration
1117 //===---------------------------------------------------------------------===//
1118 
1119 /// Add passes that optimize machine instructions after register allocation.
1120 template <typename Derived>
1122  AddMachinePass &addPass) const {
1123  // Branch folding must be run after regalloc and prolog/epilog insertion.
1124  addPass(BranchFolderPass());
1125 
1126  // Tail duplication.
1127  // Note that duplicating tail just increases code size and degrades
1128  // performance for targets that require Structured Control Flow.
1129  // In addition it can also make CFG irreducible. Thus we disable it.
1130  if (!TM.requiresStructuredCFG())
1131  addPass(TailDuplicatePass());
1132 
1133  // Copy propagation.
1134  addPass(MachineCopyPropagationPass());
1135 }
1136 
1137 /// Add standard basic block placement passes.
1138 template <typename Derived>
1140  AddMachinePass &addPass) const {
1141  addPass(MachineBlockPlacementPass());
1142  // Run a separate pass to collect block placement statistics.
1143  if (Opt.EnableBlockPlacementStats)
1144  addPass(MachineBlockPlacementStatsPass());
1145 }
1146 
1147 } // namespace llvm
1148 
1149 #endif // LLVM_CODEGEN_CODEGENPASSBUILDER_H
TypeBasedAliasAnalysis.h
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:186
llvm::BasicAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: BasicAliasAnalysis.h:161
llvm::EntryExitInstrumenterPass
Definition: EntryExitInstrumenter.h:24
llvm::ScopedNoAliasAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: ScopedNoAliasAA.h:53
llvm::AAManager
A manager for alias analyses.
Definition: AliasAnalysis.h:1303
llvm::PrintFunctionPass
Pass for printing a Function as LLVM's text IR assembly.
Definition: IRPrintingPasses.h:75
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::RegAllocType::PBQP
@ PBQP
llvm::PreISelIntrinsicLoweringPass
Definition: PreISelIntrinsicLowering.h:22
llvm::CodeGenPassBuilder::getPassInstrumentationCallbacks
PassInstrumentationCallbacks * getPassInstrumentationCallbacks() const
Definition: CodeGenPassBuilder.h:138
llvm::CodeGenPassBuilder::AddIRPass::~AddIRPass
~AddIRPass()
Definition: CodeGenPassBuilder.h:161
llvm::CodeGenPassBuilder::isGlobalISelAbortEnabled
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Definition: CodeGenPassBuilder.h:253
llvm::ExpandReductionsPass
Definition: ExpandReductions.h:16
MCTargetOptions.h
llvm::CodeGenPassBuilder
This class provides access to building LLVM's passes.
Definition: CodeGenPassBuilder.h:103
llvm::CodeGenPassBuilder::addTargetRegisterAllocator
void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const
Utilities for targets to add passes to the pass manager.
Definition: CodeGenPassBuilder.h:999
llvm::CodeGenPassBuilder::AddMachinePass::insertPass
void insertPass(AnalysisKey *ID, PassT Pass)
Definition: CodeGenPassBuilder.h:214
llvm::CodeGenPassBuilder::addGCPasses
void addGCPasses(AddMachinePass &) const
addGCPasses - Add late codegen passes that analyze code for garbage collection.
Definition: CodeGenPassBuilder.h:428
llvm::ReplaceWithVeclib
Definition: ReplaceWithVeclib.h:24
llvm::unique_function
unique_function is a type-erasing functor similar to std::function.
Definition: FunctionExtras.h:56
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
llvm::CodeGenPassBuilder::addILPOpts
void addILPOpts(AddMachinePass &) const
Add passes that optimize instruction level parallelism for out-of-order targets.
Definition: CodeGenPassBuilder.h:277
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
StringRef.h
llvm::PassManager::addPass
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT &&Pass)
Definition: PassManager.h:550
llvm::CodeGenPassBuilder::CodeGenPassBuilder
CodeGenPassBuilder(LLVMTargetMachine &TM, CGPassBuilderOption Opts, PassInstrumentationCallbacks *PIC)
Definition: CodeGenPassBuilder.h:105
llvm::CodeGenPassBuilder::CreateMCStreamer
std::function< Expected< std::unique_ptr< MCStreamer > >(MCContext &)> CreateMCStreamer
Definition: CodeGenPassBuilder.h:434
llvm::CodeGenPassBuilder::addInstSelector
Error addInstSelector(AddMachinePass &) const
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
Definition: CodeGenPassBuilder.h:266
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::RegAllocType::Basic
@ Basic
ErrorHandling.h
llvm::CodeGenPassBuilder::addPostRewrite
void addPostRewrite(AddMachinePass &) const
Add passes to be run immediately after virtual registers are rewritten to physical registers.
Definition: CodeGenPassBuilder.h:299
llvm::Error::success
static ErrorSuccess success()
Create a success value.
Definition: Error.h:329
llvm::CodeGenPassBuilder::registerTargetAnalysis
void registerTargetAnalysis(ModuleAnalysisManager &) const
Target override these hooks to parse target-specific analyses.
Definition: CodeGenPassBuilder.h:240
CGPassBuilderOption.h
Error.h
llvm::VerifierPass
Create a verifier pass.
Definition: Verifier.h:137
FAM
FunctionAnalysisManager FAM
Definition: PassBuilderBindings.cpp:59
llvm::CodeGenPassBuilder::addISelPrepare
void addISelPrepare(AddIRPass &) const
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
Definition: CodeGenPassBuilder.h:731
llvm::CodeGenPassBuilder::addIRTranslator
Error addIRTranslator(AddMachinePass &) const
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
Definition: CodeGenPassBuilder.h:331
llvm::RegAllocType::Fast
@ Fast
llvm::CFLAAType::Andersen
@ Andersen
llvm::CodeGenPassBuilder::addMachinePasses
Error addMachinePasses(AddMachinePass &) const
Add the complete, standard set of LLVM CodeGen passes.
Definition: CodeGenPassBuilder.h:842
llvm::CodeGenPassBuilder::addOptimizedRegAlloc
void addOptimizedRegAlloc(AddMachinePass &) const
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: CodeGenPassBuilder.h:1075
llvm::CodeGenPassBuilder::AddIRPass::operator()
std::enable_if_t< is_detected< is_module_pass_t, PassT >::value &&!is_detected< is_function_pass_t, PassT >::value > operator()(PassT &&Pass)
Definition: CodeGenPassBuilder.h:178
llvm::UseCFLAA
static cl::opt<::CFLAAType > UseCFLAA("use-cfl-aa", cl::init(::CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis"), cl::values(clEnumValN(::CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(::CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(::CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(::CFLAAType::Both, "both", "Enable both variants of CFL-AA")))
llvm::ExceptionHandling::ARM
@ ARM
ARM EHABI.
llvm::Optional< bool >
llvm::RunOutliner::NeverOutline
@ NeverOutline
PartiallyInlineLibCalls.h
llvm::CFLAAType::Both
@ Both
llvm::CodeGenPassBuilder::getOptLevel
CodeGenOpt::Level getOptLevel() const
Definition: CodeGenPassBuilder.h:248
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::LoopStrengthReducePass
Performs Loop Strength Reduce Pass.
Definition: LoopStrengthReduce.h:33
BasicAliasAnalysis.h
llvm::ScalarizeMaskedMemIntrinPass
Definition: ScalarizeMaskedMemIntrin.h:23
llvm::is_detected
typename detail::detector< void, Op, Args... >::value_t is_detected
Detects if a given trait holds for some set of arguments 'Args'.
Definition: STLExtras.h:97
llvm::ExceptionHandling::AIX
@ AIX
AIX Exception Handling.
llvm::TypeBasedAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: TypeBasedAliasAnalysis.h:59
AliasAnalysis.h
llvm::CodeGenPassBuilder::addCodeGenPrepare
void addCodeGenPrepare(AddIRPass &) const
Add pass to prepare the LLVM IR for code generation.
Definition: CodeGenPassBuilder.h:721
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::CodeGenPassBuilder::addPreLegalizeMachineIR
void addPreLegalizeMachineIR(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before legalization.
Definition: CodeGenPassBuilder.h:338
llvm::CodeGenPassBuilder::addPreEmitPass2
void addPreEmitPass2(AddMachinePass &) const
Targets may add passes immediately before machine code is emitted in this callback.
Definition: CodeGenPassBuilder.h:318
llvm::registerAAAnalyses
static AAManager registerAAAnalyses(CFLAAType UseCFLAA)
Definition: CodeGenPassBuilder.h:486
TargetMachine.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetOptions::EnableIPRA
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
Definition: TargetOptions.h:297
MAM
ModuleAnalysisManager MAM
Definition: PassBuilderBindings.cpp:61
llvm::CodeGenPassBuilder::registerTargetAnalysis
void registerTargetAnalysis(FunctionAnalysisManager &) const
Definition: CodeGenPassBuilder.h:241
LowerInvoke.h
Check
#define Check(C,...)
Definition: Lint.cpp:170
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:486
llvm::CodeGenPassBuilder::registerFunctionAnalyses
void registerFunctionAnalyses(FunctionAnalysisManager &) const
Definition: CodeGenPassBuilder.h:528
llvm::MachineFunctionAnalysisManager::FAM
FunctionAnalysisManager * FAM
Definition: MachinePassManager.h:99
llvm::CodeGenPassBuilder::registerAnalyses
void registerAnalyses(MachineFunctionAnalysisManager &MFAM) const
Definition: CodeGenPassBuilder.h:132
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
IRPrintingPasses.h
llvm::ExceptionHandling::Wasm
@ Wasm
WebAssembly Exception Handling.
llvm::CodeGenPassBuilder::is_function_pass_t
decltype(std::declval< PassT & >().run(std::declval< Function & >(), std::declval< FunctionAnalysisManager & >())) is_function_pass_t
Definition: CodeGenPassBuilder.h:151
llvm::CodeGenPassBuilder::addIRPasses
void addIRPasses(AddIRPass &) const
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: CodeGenPassBuilder.h:610
llvm::CodeGenPassBuilder::addPassesToHandleExceptions
void addPassesToHandleExceptions(AddIRPass &) const
Add passes to lower exception handling for the code generator.
Definition: CodeGenPassBuilder.h:675
llvm::CodeGenPassBuilder::is_module_pass_t
decltype(std::declval< PassT & >().run(std::declval< Module & >(), std::declval< ModuleAnalysisManager & >())) is_module_pass_t
Definition: CodeGenPassBuilder.h:147
llvm::CGPassBuilderOption
Definition: CGPassBuilderOption.h:29
ConstantHoisting.h
llvm::CFLSteensAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: CFLSteensAliasAnalysis.h:109
CFLAndersAliasAnalysis.h
llvm::MachineFunctionAnalysisManager
An AnalysisManager<MachineFunction> that also exposes IR analysis results.
Definition: MachinePassManager.h:41
ScopedNoAliasAA.h
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::CodeGenPassBuilder::AddIRPass::AddIRPass
AddIRPass(ModulePassManager &MPM, bool DebugPM, bool Check=true)
Definition: CodeGenPassBuilder.h:156
llvm::CodeGenPassBuilder::addRegAssignmentOptimized
Error addRegAssignmentOptimized(AddMachinePass &) const
Definition: CodeGenPassBuilder.h:1042
llvm::dxil::PointerTypeAnalysis::run
PointerTypeMap run(const Module &M)
Compute the PointerTypeMap for the module M.
Definition: PointerTypeAnalysis.cpp:101
llvm::MachO::FileType
FileType
Defines the file type this file represents.
Definition: InterfaceFile.h:53
llvm::CodeGenPassBuilder::AddIRPass
Definition: CodeGenPassBuilder.h:154
llvm::CodeGenPassBuilder::addFastRegAlloc
Error addFastRegAlloc(AddMachinePass &) const
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: CodeGenPassBuilder.h:1064
llvm::CodeGenPassBuilder::AddMachinePass::AddMachinePass
AddMachinePass(MachineFunctionPassManager &PM)
Definition: CodeGenPassBuilder.h:200
llvm::CodeGenPassBuilder::registerTargetAnalysis
void registerTargetAnalysis(MachineFunctionAnalysisManager &) const
Definition: CodeGenPassBuilder.h:242
llvm::createModuleToFunctionPassAdaptor
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:1224
llvm::CodeGenPassBuilder::has_key_t
decltype(PassT::Key) has_key_t
Definition: CodeGenPassBuilder.h:143
llvm::CodeGenPassBuilder::addGlobalInstructionSelect
Error addGlobalInstructionSelect(AddMachinePass &) const
This method should install a (global) instruction selector pass, which converts possibly generic inst...
Definition: CodeGenPassBuilder.h:367
llvm::raw_pwrite_stream
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:418
llvm::LowerInvokePass
Definition: LowerInvoke.h:22
llvm::CodeGenPassBuilder::AddMachinePass
Definition: CodeGenPassBuilder.h:198
llvm::CodeGenPassBuilder::reportDiagnosticWhenGlobalISelFallback
bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
Definition: CodeGenPassBuilder.h:260
llvm::CodeGenPassBuilder::getTargetPassNameFromLegacyName
std::pair< StringRef, bool > getTargetPassNameFromLegacyName(StringRef) const
Definition: CodeGenPassBuilder.h:243
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MachineFunctionAnalysisManager::MAM
ModuleAnalysisManager * MAM
Definition: MachinePassManager.h:100
llvm::AnalysisKey
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:69
llvm::CodeGenPassBuilder::addRegAssignmentFast
Error addRegAssignmentFast(AddMachinePass &) const
Add core register alloator passes which do the actual register assignment and rewriting.
Definition: CodeGenPassBuilder.h:1029
llvm::UnreachableBlockElimPass
Definition: UnreachableBlockElim.h:29
llvm::CodeGenPassBuilder::addISelPasses
void addISelPasses(AddIRPass &) const
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
Definition: CodeGenPassBuilder.h:595
llvm::createFunctionToLoopPassAdaptor
std::enable_if_t< is_detected< HasRunOnLoopT, LoopPassT >::value, FunctionToLoopPassAdaptor > createFunctionToLoopPassAdaptor(LoopPassT &&Pass, bool UseMemorySSA=false, bool UseBlockFrequencyInfo=false, bool UseBranchProbabilityInfo=false)
A function to deduce a loop pass type and wrap it in the templated adaptor.
Definition: LoopPassManager.h:472
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::CGPassBuilderOption::EnableGlobalISelAbort
Optional< GlobalISelAbortMode > EnableGlobalISelAbort
Definition: CGPassBuilderOption.h:53
llvm::RegAllocType::Greedy
@ Greedy
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
LoopPassManager.h
llvm::CodeGenPassBuilder::registerModuleAnalyses
void registerModuleAnalyses(ModuleAnalysisManager &) const
Definition: CodeGenPassBuilder.h:519
llvm::CodeGenPassBuilder::buildPipeline
Error buildPipeline(ModulePassManager &MPM, MachineFunctionPassManager &MFPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType) const
Definition: CodeGenPassBuilder.h:463
llvm::CFLAAType::Steensgaard
@ Steensgaard
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::CodeGenPassBuilder::addBlockPlacement
void addBlockPlacement(AddMachinePass &) const
Add standard basic block placement passes.
Definition: CodeGenPassBuilder.h:1139
MCAsmInfo.h
llvm::CodeGenPassBuilder::Opt
CGPassBuilderOption Opt
Definition: CodeGenPassBuilder.h:236
llvm::CodeGenFileType
CodeGenFileType
These enums are meant to be passed into addPassesToEmitFile to indicate what type of file to emit,...
Definition: CodeGen.h:63
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::CodeGenPassBuilder::addPreEmitPass
void addPreEmitPass(AddMachinePass &) const
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Definition: CodeGenPassBuilder.h:311
llvm::CodeGenPassBuilder::addPreGlobalInstructionSelect
void addPreGlobalInstructionSelect(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before the (global) ins...
Definition: CodeGenPassBuilder.h:361
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::RunOutliner::AlwaysOutline
@ AlwaysOutline
llvm::GlobalISelAbortMode::DisableWithDiag
@ DisableWithDiag
llvm::CodeGenPassBuilder::addAsmPrinter
void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const
Definition: CodeGenPassBuilder.h:435
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
llvm::CodeGenPassBuilder::addLegalizeMachineIR
Error addLegalizeMachineIR(AddMachinePass &) const
This method should install a legalize pass, which converts the instruction sequence into one that can...
Definition: CodeGenPassBuilder.h:342
llvm::CodeGenPassBuilder::AddMachinePass::operator()
void operator()(PassT &&Pass)
Definition: CodeGenPassBuilder.h:202
llvm::PassManager< Module >
MergeICmps.h
llvm::CodeGenPassBuilder::addPreRewrite
void addPreRewrite(AddMachinePass &) const
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
Definition: CodeGenPassBuilder.h:295
llvm::CodeGenPassBuilder::addPostRegAlloc
void addPostRegAlloc(AddMachinePass &) const
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Definition: CodeGenPassBuilder.h:303
MachinePassManager.h
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
Verifier.h
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
LoopStrengthReduce.h
llvm::CodeGenPassBuilder::PIC
PassInstrumentationCallbacks * PIC
Definition: CodeGenPassBuilder.h:237
llvm::inconvertibleErrorCode
std::error_code inconvertibleErrorCode()
The value returned by this function can be returned from convertToErrorCode for Error values where no...
Definition: Error.cpp:77
llvm::CodeGenPassBuilder::registerMachineFunctionAnalyses
void registerMachineFunctionAnalyses(MachineFunctionAnalysisManager &) const
Definition: CodeGenPassBuilder.h:539
llvm::CGPassBuilderOption::OptimizeRegAlloc
Optional< bool > OptimizeRegAlloc
Definition: CGPassBuilderOption.h:30
llvm::CodeGenPassBuilder::addRegBankSelect
Error addRegBankSelect(AddMachinePass &) const
This method should install a register bank selector pass, which assigns register banks to virtual reg...
Definition: CodeGenPassBuilder.h:354
llvm::TargetOptions::GlobalISelAbort
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
Definition: TargetOptions.h:239
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::ExceptionHandling::WinEH
@ WinEH
Windows Exception Handling.
PassManager.h
llvm::PartiallyInlineLibCallsPass
Definition: PartiallyInlineLibCalls.h:22
LowerConstantIntrinsics.h
llvm::CodeGenPassBuilder::AddMachinePass::releasePM
MachineFunctionPassManager releasePM()
Definition: CodeGenPassBuilder.h:227
llvm::MachineFunctionPassManager::addPass
void addPass(PassT &&Pass)
Definition: MachinePassManager.h:155
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:411
ScalarizeMaskedMemIntrin.h
UnreachableBlockElim.h
llvm::AnalysisManager::registerPass
bool registerPass(PassBuilderT &&PassBuilder)
Register an analysis pass with the manager.
Definition: PassManager.h:842
llvm::MachineFunctionPassManager
MachineFunctionPassManager adds/removes below features to/from the base PassManager template instanti...
Definition: MachinePassManager.h:132
llvm::CodeGenPassBuilder::addCoreISelPasses
Error addCoreISelPasses(AddMachinePass &) const
Add the actual instruction selection passes.
Definition: CodeGenPassBuilder.h:750
llvm::ExceptionHandling::None
@ None
No exception support.
AA
CodeGen.h
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:777
llvm::GlobalISelAbortMode::Enable
@ Enable
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
SmallVector.h
ExpandReductions.h
llvm::CodeGenPassBuilder::addPreRegBankSelect
void addPreRegBankSelect(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before the register ban...
Definition: CodeGenPassBuilder.h:349
llvm::LowerConstantIntrinsicsPass
Definition: LowerConstantIntrinsics.h:24
llvm::PassInstrumentationCallbacks
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
Definition: PassInstrumentation.h:66
ReplaceWithVeclib.h
llvm::CFLAAType
CFLAAType
Definition: CGPassBuilderOption.h:25
TargetTransformInfo.h
llvm::CodeGenPassBuilder::addMachineSSAOptimization
void addMachineSSAOptimization(AddMachinePass &) const
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Definition: CodeGenPassBuilder.h:947
llvm::CodeGenPassBuilder::AddIRPass::operator()
std::enable_if_t< is_detected< is_function_pass_t, PassT >::value > operator()(PassT &&Pass)
Definition: CodeGenPassBuilder.h:168
llvm::CodeGenPassBuilder::addRegAllocPass
void addRegAllocPass(AddMachinePass &, bool Optimized) const
addMachinePasses helper to create the target-selected or overriden regalloc pass.
Definition: CodeGenPassBuilder.h:1011
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:42
llvm::CFLAndersAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: CFLAndersAliasAnalysis.h:94
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::CodeGenPassBuilder::getTM
TMC & getTM() const
Definition: CodeGenPassBuilder.h:247
llvm::CodeGenPassBuilder::addPreISel
void addPreISel(AddIRPass &) const
{{@ For GlobalISel
Definition: CodeGenPassBuilder.h:325
EntryExitInstrumenter.h
llvm::RegAllocType::Default
@ Default
llvm::CodeGenPassBuilder::addMachineLateOptimization
void addMachineLateOptimization(AddMachinePass &) const
Add passes that optimize machine instructions after register allocation.
Definition: CodeGenPassBuilder.h:1121
llvm::CGPassBuilderOption::EnableIPRA
Optional< bool > EnableIPRA
Definition: CGPassBuilderOption.h:31
llvm::CodeGenPassBuilder::AddMachinePass::disablePass
void disablePass(AnalysisKey *ID)
Definition: CodeGenPassBuilder.h:222
llvm::ConstantHoistingPass
Definition: ConstantHoisting.h:123
llvm::CodeGenPassBuilder::addPreRegAlloc
void addPreRegAlloc(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before register allocat...
Definition: CodeGenPassBuilder.h:281
MPM
ModulePassManager MPM
Definition: PassBuilderBindings.cpp:70
llvm::ExceptionHandling::DwarfCFI
@ DwarfCFI
DWARF-like instruction based exceptions.
Debug.h
llvm::MergeICmpsPass
Definition: MergeICmps.h:18
llvm::CodeGenPassBuilder::addPreSched2
void addPreSched2(AddMachinePass &) const
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Definition: CodeGenPassBuilder.h:307
PreISelIntrinsicLowering.h
CFLSteensAliasAnalysis.h
llvm::CodeGenPassBuilder::getPassNameFromLegacyName
std::pair< StringRef, bool > getPassNameFromLegacyName(StringRef) const
Definition: CodeGenPassBuilder.h:553
llvm::CodeGenPassBuilder::TM
LLVMTargetMachine & TM
Definition: CodeGenPassBuilder.h:235
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38