LLVM 19.0.0git
CodeGenPassBuilder.h
Go to the documentation of this file.
1//===- Construction of codegen pass pipelines ------------------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// Interfaces for producing common pass manager configurations.
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_PASSES_CODEGENPASSBUILDER_H
15#define LLVM_PASSES_CODEGENPASSBUILDER_H
16
18#include "llvm/ADT/StringRef.h"
53#include "llvm/IR/PassManager.h"
54#include "llvm/IR/Verifier.h"
56#include "llvm/MC/MCAsmInfo.h"
59#include "llvm/Support/Debug.h"
60#include "llvm/Support/Error.h"
74#include <cassert>
75#include <type_traits>
76#include <utility>
77
78namespace llvm {
79
80// FIXME: Dummy target independent passes definitions that have not yet been
81// ported to new pass manager. Once they do, remove these.
82#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME) \
83 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
84 template <typename... Ts> PASS_NAME(Ts &&...) {} \
85 PreservedAnalyses run(Function &, FunctionAnalysisManager &) { \
86 return PreservedAnalyses::all(); \
87 } \
88 };
89#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME) \
90 struct PASS_NAME : public MachinePassInfoMixin<PASS_NAME> { \
91 template <typename... Ts> PASS_NAME(Ts &&...) {} \
92 PreservedAnalyses run(Module &, ModuleAnalysisManager &) { \
93 return PreservedAnalyses::all(); \
94 } \
95 };
96#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME) \
97 struct PASS_NAME : public MachinePassInfoMixin<PASS_NAME> { \
98 template <typename... Ts> PASS_NAME(Ts &&...) {} \
99 PreservedAnalyses run(MachineFunction &, \
100 MachineFunctionAnalysisManager &) { \
101 return PreservedAnalyses::all(); \
102 } \
103 };
104#include "llvm/Passes/MachinePassRegistry.def"
105
106/// This class provides access to building LLVM's passes.
107///
108/// Its members provide the baseline state available to passes during their
109/// construction. The \c MachinePassRegistry.def file specifies how to construct
110/// all of the built-in passes, and those may reference these members during
111/// construction.
112template <typename DerivedT> class CodeGenPassBuilder {
113public:
116 : TM(TM), Opt(Opts), PIC(PIC) {
117 // Target could set CGPassBuilderOption::MISchedPostRA to true to achieve
118 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID)
119
120 // Target should override TM.Options.EnableIPRA in their target-specific
121 // LLVMTM ctor. See TargetMachine::setGlobalISel for example.
122 if (Opt.EnableIPRA)
124
127
130 }
131
133 raw_pwrite_stream *DwoOut,
134 CodeGenFileType FileType) const;
135
137 return PIC;
138 }
139
140protected:
141 template <typename PassT>
142 using is_module_pass_t = decltype(std::declval<PassT &>().run(
143 std::declval<Module &>(), std::declval<ModuleAnalysisManager &>()));
144
145 template <typename PassT>
146 using is_function_pass_t = decltype(std::declval<PassT &>().run(
147 std::declval<Function &>(), std::declval<FunctionAnalysisManager &>()));
148
149 template <typename PassT>
150 using is_machine_function_pass_t = decltype(std::declval<PassT &>().run(
151 std::declval<MachineFunction &>(),
152 std::declval<MachineFunctionAnalysisManager &>()));
153
154 // Function object to maintain state while adding codegen IR passes.
155 // TODO: add a Function -> MachineFunction adaptor and merge
156 // AddIRPass/AddMachinePass so we can have a function pipeline that runs both
157 // function passes and machine function passes.
158 class AddIRPass {
159 public:
160 AddIRPass(ModulePassManager &MPM, const DerivedT &PB) : MPM(MPM), PB(PB) {}
162 if (!FPM.isEmpty())
163 MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
164 }
165
166 template <typename PassT>
167 void operator()(PassT &&Pass, StringRef Name = PassT::name()) {
170 "Only module pass and function pass are supported.");
171
172 if (!PB.runBeforeAdding(Name))
173 return;
174
175 // Add Function Pass
177 FPM.addPass(std::forward<PassT>(Pass));
178
179 for (auto &C : PB.AfterCallbacks)
180 C(Name);
181 } else {
182 // Add Module Pass
183 if (!FPM.isEmpty()) {
184 MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
185 FPM = FunctionPassManager();
186 }
187
188 MPM.addPass(std::forward<PassT>(Pass));
189
190 for (auto &C : PB.AfterCallbacks)
191 C(Name);
192 }
193 }
194
195 private:
198 const DerivedT &PB;
199 };
200
201 // Function object to maintain state while adding codegen machine passes.
203 public:
204 AddMachinePass(ModulePassManager &MPM, const DerivedT &PB)
205 : MPM(MPM), PB(PB) {}
207 if (!MFPM.isEmpty())
209 }
210
211 template <typename PassT>
212 void operator()(PassT &&Pass, bool Force = false,
213 StringRef Name = PassT::name()) {
216 "Only module pass and function pass are supported.");
217
218 if (!Force && !PB.runBeforeAdding(Name))
219 return;
220
221 // Add Function Pass
223 MFPM.addPass(std::forward<PassT>(Pass));
224
225 for (auto &C : PB.AfterCallbacks)
226 C(Name);
227 } else {
228 // Add Module Pass
229 if (!MFPM.isEmpty()) {
230 MPM.addPass(
233 }
234
235 MPM.addPass(std::forward<PassT>(Pass));
236
237 for (auto &C : PB.AfterCallbacks)
238 C(Name);
239 }
240 }
241
242 private:
245 const DerivedT &PB;
246 };
247
251
252 template <typename TMC> TMC &getTM() const { return static_cast<TMC &>(TM); }
254
255 /// Check whether or not GlobalISel should abort on error.
256 /// When this is disabled, GlobalISel will fall back on SDISel instead of
257 /// erroring out.
260 }
261
262 /// Check whether or not a diagnostic should be emitted when GlobalISel
263 /// uses the fallback path. In other words, it will emit a diagnostic
264 /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
267 }
268
269 /// addInstSelector - This method should install an instruction selector pass,
270 /// which converts from LLVM code to machine instructions.
272 return make_error<StringError>("addInstSelector is not overridden",
274 }
275
276 /// Target can override this to add GlobalMergePass before all IR passes.
278
279 /// Add passes that optimize instruction level parallelism for out-of-order
280 /// targets. These passes are run while the machine code is still in SSA
281 /// form, so they can use MachineTraceMetrics to control their heuristics.
282 ///
283 /// All passes added here should preserve the MachineDominatorTree,
284 /// MachineLoopInfo, and MachineTraceMetrics analyses.
285 void addILPOpts(AddMachinePass &) const {}
286
287 /// This method may be implemented by targets that want to run passes
288 /// immediately before register allocation.
290
291 /// addPreRewrite - Add passes to the optimized register allocation pipeline
292 /// after register allocation is complete, but before virtual registers are
293 /// rewritten to physical registers.
294 ///
295 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
296 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
297 /// When these passes run, VirtRegMap contains legal physreg assignments for
298 /// all virtual registers.
299 ///
300 /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
301 /// be honored. This is also not generally used for the fast variant,
302 /// where the allocation and rewriting are done in one pass.
304
305 /// Add passes to be run immediately after virtual registers are rewritten
306 /// to physical registers.
308
309 /// This method may be implemented by targets that want to run passes after
310 /// register allocation pass pipeline but before prolog-epilog insertion.
312
313 /// This method may be implemented by targets that want to run passes after
314 /// prolog-epilog insertion and before the second instruction scheduling pass.
316
317 /// This pass may be implemented by targets that want to run passes
318 /// immediately before machine code is emitted.
320
321 /// Targets may add passes immediately before machine code is emitted in this
322 /// callback. This is called even later than `addPreEmitPass`.
323 // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
324 // position and remove the `2` suffix here as this callback is what
325 // `addPreEmitPass` *should* be but in reality isn't.
327
328 /// {{@ For GlobalISel
329 ///
330
331 /// addPreISel - This method should add any "last minute" LLVM->LLVM
332 /// passes (which are run just before instruction selector).
333 void addPreISel(AddIRPass &) const {
334 llvm_unreachable("addPreISel is not overridden");
335 }
336
337 /// This method should install an IR translator pass, which converts from
338 /// LLVM code to machine instructions with possibly generic opcodes.
340 return make_error<StringError>("addIRTranslator is not overridden",
342 }
343
344 /// This method may be implemented by targets that want to run passes
345 /// immediately before legalization.
347
348 /// This method should install a legalize pass, which converts the instruction
349 /// sequence into one that can be selected by the target.
351 return make_error<StringError>("addLegalizeMachineIR is not overridden",
353 }
354
355 /// This method may be implemented by targets that want to run passes
356 /// immediately before the register bank selection.
358
359 /// This method should install a register bank selector pass, which
360 /// assigns register banks to virtual registers without a register
361 /// class or register banks.
363 return make_error<StringError>("addRegBankSelect is not overridden",
365 }
366
367 /// This method may be implemented by targets that want to run passes
368 /// immediately before the (global) instruction selection.
370
371 /// This method should install a (global) instruction selector pass, which
372 /// converts possibly generic instructions to fully target-specific
373 /// instructions, thereby constraining all generic virtual registers to
374 /// register classes.
376 return make_error<StringError>(
377 "addGlobalInstructionSelect is not overridden",
379 }
380 /// @}}
381
382 /// High level function that adds all passes necessary to go from llvm IR
383 /// representation to the MI representation.
384 /// Adds IR based lowering and target specific optimization passes and finally
385 /// the core instruction selection passes.
386 void addISelPasses(AddIRPass &) const;
387
388 /// Add the actual instruction selection passes. This does not include
389 /// preparation passes on IR.
390 Error addCoreISelPasses(AddMachinePass &) const;
391
392 /// Add the complete, standard set of LLVM CodeGen passes.
393 /// Fully developed targets will not generally override this.
394 Error addMachinePasses(AddMachinePass &) const;
395
396 /// Add passes to lower exception handling for the code generator.
397 void addPassesToHandleExceptions(AddIRPass &) const;
398
399 /// Add common target configurable passes that perform LLVM IR to IR
400 /// transforms following machine independent optimization.
401 void addIRPasses(AddIRPass &) const;
402
403 /// Add pass to prepare the LLVM IR for code generation. This should be done
404 /// before exception handling preparation passes.
405 void addCodeGenPrepare(AddIRPass &) const;
406
407 /// Add common passes that perform LLVM IR to IR transforms in preparation for
408 /// instruction selection.
409 void addISelPrepare(AddIRPass &) const;
410
411 /// Methods with trivial inline returns are convenient points in the common
412 /// codegen pass pipeline where targets may insert passes. Methods with
413 /// out-of-line standard implementations are major CodeGen stages called by
414 /// addMachinePasses. Some targets may override major stages when inserting
415 /// passes is insufficient, but maintaining overriden stages is more work.
416 ///
417
418 /// addMachineSSAOptimization - Add standard passes that optimize machine
419 /// instructions in SSA form.
420 void addMachineSSAOptimization(AddMachinePass &) const;
421
422 /// addFastRegAlloc - Add the minimum set of target-independent passes that
423 /// are required for fast register allocation.
424 Error addFastRegAlloc(AddMachinePass &) const;
425
426 /// addOptimizedRegAlloc - Add passes related to register allocation.
427 /// LLVMTargetMachine provides standard regalloc passes for most targets.
428 void addOptimizedRegAlloc(AddMachinePass &) const;
429
430 /// Add passes that optimize machine instructions after register allocation.
431 void addMachineLateOptimization(AddMachinePass &) const;
432
433 /// addGCPasses - Add late codegen passes that analyze code for garbage
434 /// collection. This should return true if GC info should be printed after
435 /// these passes.
437
438 /// Add standard basic block placement passes.
439 void addBlockPlacement(AddMachinePass &) const;
440
442 std::function<Expected<std::unique_ptr<MCStreamer>>(MCContext &)>;
444 llvm_unreachable("addAsmPrinter is not overridden");
445 }
446
447 /// Utilities for targets to add passes to the pass manager.
448 ///
449
450 /// createTargetRegisterAllocator - Create the register allocator pass for
451 /// this target at the current optimization level.
452 void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const;
453
454 /// addMachinePasses helper to create the target-selected or overriden
455 /// regalloc pass.
456 void addRegAllocPass(AddMachinePass &, bool Optimized) const;
457
458 /// Add core register alloator passes which do the actual register assignment
459 /// and rewriting. \returns true if any passes were added.
460 Error addRegAssignmentFast(AddMachinePass &) const;
461 Error addRegAssignmentOptimized(AddMachinePass &) const;
462
463private:
464 DerivedT &derived() { return static_cast<DerivedT &>(*this); }
465 const DerivedT &derived() const {
466 return static_cast<const DerivedT &>(*this);
467 }
468
469 bool runBeforeAdding(StringRef Name) const {
470 bool ShouldAdd = true;
471 for (auto &C : BeforeCallbacks)
472 ShouldAdd &= C(Name);
473 return ShouldAdd;
474 }
475
476 void setStartStopPasses(const TargetPassConfig::StartStopInfo &Info) const;
477
478 Error verifyStartStop(const TargetPassConfig::StartStopInfo &Info) const;
479
480 mutable SmallVector<llvm::unique_function<bool(StringRef)>, 4>
481 BeforeCallbacks;
482 mutable SmallVector<llvm::unique_function<void(StringRef)>, 4> AfterCallbacks;
483
484 /// Helper variable for `-start-before/-start-after/-stop-before/-stop-after`
485 mutable bool Started = true;
486 mutable bool Stopped = true;
487};
488
489template <typename Derived>
492 CodeGenFileType FileType) const {
493 auto StartStopInfo = TargetPassConfig::getStartStopInfo(*PIC);
494 if (!StartStopInfo)
495 return StartStopInfo.takeError();
496 setStartStopPasses(*StartStopInfo);
497
499 bool PrintMIR = !PrintAsm && FileType != CodeGenFileType::Null;
500
501 {
502 AddIRPass addIRPass(MPM, derived());
505 addISelPasses(addIRPass);
506 }
507
508 AddMachinePass addPass(MPM, derived());
509
510 if (PrintMIR)
511 addPass(PrintMIRPreparePass(Out), /*Force=*/true);
512
513 if (auto Err = addCoreISelPasses(addPass))
514 return std::move(Err);
515
516 if (auto Err = derived().addMachinePasses(addPass))
517 return std::move(Err);
518
519 if (PrintAsm) {
520 derived().addAsmPrinter(
521 addPass, [this, &Out, DwoOut, FileType](MCContext &Ctx) {
522 return this->TM.createMCStreamer(Out, DwoOut, FileType, Ctx);
523 });
524 }
525
526 if (PrintMIR)
527 addPass(PrintMIRPass(Out), /*Force=*/true);
528
529 addPass(FreeMachineFunctionPass());
530 return verifyStartStop(*StartStopInfo);
531}
532
533template <typename Derived>
536 if (!Info.StartPass.empty()) {
537 Started = false;
538 BeforeCallbacks.emplace_back([this, &Info, AfterFlag = Info.StartAfter,
539 Count = 0u](StringRef ClassName) mutable {
540 if (Count == Info.StartInstanceNum) {
541 if (AfterFlag) {
542 AfterFlag = false;
543 Started = true;
544 }
545 return Started;
546 }
547
548 auto PassName = PIC->getPassNameForClassName(ClassName);
549 if (Info.StartPass == PassName && ++Count == Info.StartInstanceNum)
550 Started = !Info.StartAfter;
551
552 return Started;
553 });
554 }
555
556 if (!Info.StopPass.empty()) {
557 Stopped = false;
558 BeforeCallbacks.emplace_back([this, &Info, AfterFlag = Info.StopAfter,
559 Count = 0u](StringRef ClassName) mutable {
560 if (Count == Info.StopInstanceNum) {
561 if (AfterFlag) {
562 AfterFlag = false;
563 Stopped = true;
564 }
565 return !Stopped;
566 }
567
568 auto PassName = PIC->getPassNameForClassName(ClassName);
569 if (Info.StopPass == PassName && ++Count == Info.StopInstanceNum)
570 Stopped = !Info.StopAfter;
571 return !Stopped;
572 });
573 }
574}
575
576template <typename Derived>
577Error CodeGenPassBuilder<Derived>::verifyStartStop(
578 const TargetPassConfig::StartStopInfo &Info) const {
579 if (Started && Stopped)
580 return Error::success();
581
582 if (!Started)
583 return make_error<StringError>(
584 "Can't find start pass \"" +
585 PIC->getPassNameForClassName(Info.StartPass) + "\".",
586 std::make_error_code(std::errc::invalid_argument));
587 if (!Stopped)
588 return make_error<StringError>(
589 "Can't find stop pass \"" +
590 PIC->getPassNameForClassName(Info.StopPass) + "\".",
591 std::make_error_code(std::errc::invalid_argument));
592 return Error::success();
593}
594
595template <typename Derived>
597 derived().addGlobalMergePass(addPass);
598 if (TM.useEmulatedTLS())
599 addPass(LowerEmuTLSPass());
600
602
603 derived().addIRPasses(addPass);
604 derived().addCodeGenPrepare(addPass);
605 addPassesToHandleExceptions(addPass);
606 derived().addISelPrepare(addPass);
607}
608
609/// Add common target configurable passes that perform LLVM IR to IR transforms
610/// following machine independent optimization.
611template <typename Derived>
613 // Before running any passes, run the verifier to determine if the input
614 // coming from the front-end and/or optimizer is valid.
615 if (!Opt.DisableVerify)
616 addPass(VerifierPass());
617
618 // Run loop strength reduction before anything else.
619 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) {
621 /*UseMemorySSA=*/true));
622 // FIXME: use -stop-after so we could remove PrintLSR
623 if (Opt.PrintLSR)
624 addPass(PrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
625 }
626
627 if (getOptLevel() != CodeGenOptLevel::None) {
628 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
629 // loads and compares. ExpandMemCmpPass then tries to expand those calls
630 // into optimally-sized loads and compares. The transforms are enabled by a
631 // target lowering hook.
632 if (!Opt.DisableMergeICmps)
633 addPass(MergeICmpsPass());
634 addPass(ExpandMemCmpPass(&TM));
635 }
636
637 // Run GC lowering passes for builtin collectors
638 // TODO: add a pass insertion point here
639 addPass(GCLoweringPass());
640 addPass(ShadowStackGCLoweringPass());
642
643 // Make sure that no unreachable blocks are instruction selected.
644 addPass(UnreachableBlockElimPass());
645
646 // Prepare expensive constants for SelectionDAG.
647 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableConstantHoisting)
648 addPass(ConstantHoistingPass());
649
650 // Replace calls to LLVM intrinsics (e.g., exp, log) operating on vector
651 // operands with calls to the corresponding functions in a vector library.
652 if (getOptLevel() != CodeGenOptLevel::None)
653 addPass(ReplaceWithVeclib());
654
655 if (getOptLevel() != CodeGenOptLevel::None &&
658
659 // Instrument function entry and exit, e.g. with calls to mcount().
660 addPass(EntryExitInstrumenterPass(/*PostInlining=*/true));
661
662 // Add scalarization of target's unsupported masked memory intrinsics pass.
663 // the unsupported intrinsic will be replaced with a chain of basic blocks,
664 // that stores/loads element one-by-one if the appropriate mask bit is set.
666
667 // Expand reduction intrinsics into shuffle sequences if the target wants to.
668 addPass(ExpandReductionsPass());
669
670 // Convert conditional moves to conditional jumps when profitable.
671 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableSelectOptimize)
672 addPass(SelectOptimizePass(&TM));
673}
674
675/// Turn exception handling constructs into something the code generators can
676/// handle.
677template <typename Derived>
679 AddIRPass &addPass) const {
680 const MCAsmInfo *MCAI = TM.getMCAsmInfo();
681 assert(MCAI && "No MCAsmInfo");
682 switch (MCAI->getExceptionHandlingType()) {
683 case ExceptionHandling::SjLj:
684 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
685 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
686 // catch info can get misplaced when a selector ends up more than one block
687 // removed from the parent invoke(s). This could happen when a landing
688 // pad is shared by multiple invokes and is also a target of a normal
689 // edge from elsewhere.
690 addPass(SjLjEHPreparePass(&TM));
691 [[fallthrough]];
692 case ExceptionHandling::DwarfCFI:
693 case ExceptionHandling::ARM:
694 case ExceptionHandling::AIX:
695 case ExceptionHandling::ZOS:
696 addPass(DwarfEHPreparePass(&TM));
697 break;
698 case ExceptionHandling::WinEH:
699 // We support using both GCC-style and MSVC-style exceptions on Windows, so
700 // add both preparation passes. Each pass will only actually run if it
701 // recognizes the personality function.
702 addPass(WinEHPreparePass());
703 addPass(DwarfEHPreparePass(&TM));
704 break;
705 case ExceptionHandling::Wasm:
706 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
707 // on catchpads and cleanuppads because it does not outline them into
708 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
709 // should remove PHIs there.
710 addPass(WinEHPreparePass(/*DemoteCatchSwitchPHIOnly=*/false));
711 addPass(WasmEHPreparePass());
712 break;
713 case ExceptionHandling::None:
714 addPass(LowerInvokePass());
715
716 // The lower invoke pass may create unreachable code. Remove it.
717 addPass(UnreachableBlockElimPass());
718 break;
719 }
720}
721
722/// Add pass to prepare the LLVM IR for code generation. This should be done
723/// before exception handling preparation passes.
724template <typename Derived>
726 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableCGP)
727 addPass(CodeGenPreparePass(&TM));
728 // TODO: Default ctor'd RewriteSymbolPass is no-op.
729 // addPass(RewriteSymbolPass());
730}
731
732/// Add common passes that perform LLVM IR to IR transforms in preparation for
733/// instruction selection.
734template <typename Derived>
736 derived().addPreISel(addPass);
737
738 addPass(CallBrPreparePass());
739 // Add both the safe stack and the stack protection passes: each of them will
740 // only protect functions that have corresponding attributes.
741 addPass(SafeStackPass(&TM));
742 addPass(StackProtectorPass(&TM));
743
744 if (Opt.PrintISelInput)
745 addPass(PrintFunctionPass(dbgs(),
746 "\n\n*** Final LLVM Code input to ISel ***\n"));
747
748 // All passes which modify the LLVM IR are now complete; run the verifier
749 // to ensure that the IR is valid.
750 if (!Opt.DisableVerify)
751 addPass(VerifierPass());
752}
753
754template <typename Derived>
756 AddMachinePass &addPass) const {
757 // Enable FastISel with -fast-isel, but allow that to be overridden.
758 TM.setO0WantsFastISel(Opt.EnableFastISelOption.value_or(true));
759
760 // Determine an instruction selector.
761 enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
762 SelectorType Selector;
763
764 if (Opt.EnableFastISelOption && *Opt.EnableFastISelOption == true)
765 Selector = SelectorType::FastISel;
766 else if ((Opt.EnableGlobalISelOption &&
767 *Opt.EnableGlobalISelOption == true) ||
768 (TM.Options.EnableGlobalISel &&
770 *Opt.EnableGlobalISelOption == false)))
771 Selector = SelectorType::GlobalISel;
772 else if (TM.getOptLevel() == CodeGenOptLevel::None && TM.getO0WantsFastISel())
773 Selector = SelectorType::FastISel;
774 else
775 Selector = SelectorType::SelectionDAG;
776
777 // Set consistently TM.Options.EnableFastISel and EnableGlobalISel.
778 if (Selector == SelectorType::FastISel) {
779 TM.setFastISel(true);
780 TM.setGlobalISel(false);
781 } else if (Selector == SelectorType::GlobalISel) {
782 TM.setFastISel(false);
783 TM.setGlobalISel(true);
784 }
785
786 // Add instruction selector passes.
787 if (Selector == SelectorType::GlobalISel) {
788 if (auto Err = derived().addIRTranslator(addPass))
789 return std::move(Err);
790
791 derived().addPreLegalizeMachineIR(addPass);
792
793 if (auto Err = derived().addLegalizeMachineIR(addPass))
794 return std::move(Err);
795
796 // Before running the register bank selector, ask the target if it
797 // wants to run some passes.
798 derived().addPreRegBankSelect(addPass);
799
800 if (auto Err = derived().addRegBankSelect(addPass))
801 return std::move(Err);
802
803 derived().addPreGlobalInstructionSelect(addPass);
804
805 if (auto Err = derived().addGlobalInstructionSelect(addPass))
806 return std::move(Err);
807
808 // Pass to reset the MachineFunction if the ISel failed.
809 addPass(ResetMachineFunctionPass(reportDiagnosticWhenGlobalISelFallback(),
810 isGlobalISelAbortEnabled()));
811
812 // Provide a fallback path when we do not want to abort on
813 // not-yet-supported input.
814 if (!isGlobalISelAbortEnabled())
815 if (auto Err = derived().addInstSelector(addPass))
816 return std::move(Err);
817
818 } else if (auto Err = derived().addInstSelector(addPass))
819 return std::move(Err);
820
821 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
822 // FinalizeISel.
823 addPass(FinalizeISelPass());
824
825 // // Print the instruction selected machine code...
826 // printAndVerify("After Instruction Selection");
827
828 return Error::success();
829}
830
831/// Add the complete set of target-independent postISel code generator passes.
832///
833/// This can be read as the standard order of major LLVM CodeGen stages. Stages
834/// with nontrivial configuration or multiple passes are broken out below in
835/// add%Stage routines.
836///
837/// Any CodeGenPassBuilder<Derived>::addXX routine may be overriden by the
838/// Target. The addPre/Post methods with empty header implementations allow
839/// injecting target-specific fixups just before or after major stages.
840/// Additionally, targets have the flexibility to change pass order within a
841/// stage by overriding default implementation of add%Stage routines below. Each
842/// technique has maintainability tradeoffs because alternate pass orders are
843/// not well supported. addPre/Post works better if the target pass is easily
844/// tied to a common pass. But if it has subtle dependencies on multiple passes,
845/// the target should override the stage instead.
846template <typename Derived>
848 AddMachinePass &addPass) const {
849 // Add passes that optimize machine instructions in SSA form.
850 if (getOptLevel() != CodeGenOptLevel::None) {
851 derived().addMachineSSAOptimization(addPass);
852 } else {
853 // If the target requests it, assign local variables to stack slots relative
854 // to one another and simplify frame index references where possible.
855 addPass(LocalStackSlotPass());
856 }
857
858 if (TM.Options.EnableIPRA)
859 addPass(RegUsageInfoPropagationPass());
860
861 // Run pre-ra passes.
862 derived().addPreRegAlloc(addPass);
863
864 // Run register allocation and passes that are tightly coupled with it,
865 // including phi elimination and scheduling.
866 if (*Opt.OptimizeRegAlloc) {
867 derived().addOptimizedRegAlloc(addPass);
868 } else {
869 if (auto Err = derived().addFastRegAlloc(addPass))
870 return Err;
871 }
872
873 // Run post-ra passes.
874 derived().addPostRegAlloc(addPass);
875
876 addPass(RemoveRedundantDebugValuesPass());
877
878 // Insert prolog/epilog code. Eliminate abstract frame index references...
879 if (getOptLevel() != CodeGenOptLevel::None) {
880 addPass(PostRAMachineSinkingPass());
881 addPass(ShrinkWrapPass());
882 }
883
884 addPass(PrologEpilogInserterPass());
885
886 /// Add passes that optimize machine instructions after register allocation.
887 if (getOptLevel() != CodeGenOptLevel::None)
888 derived().addMachineLateOptimization(addPass);
889
890 // Expand pseudo instructions before second scheduling pass.
891 addPass(ExpandPostRAPseudosPass());
892
893 // Run pre-sched2 passes.
894 derived().addPreSched2(addPass);
895
897 addPass(ImplicitNullChecksPass());
898
899 // Second pass scheduler.
900 // Let Target optionally insert this pass by itself at some other
901 // point.
902 if (getOptLevel() != CodeGenOptLevel::None &&
903 !TM.targetSchedulesPostRAScheduling()) {
904 if (Opt.MISchedPostRA)
905 addPass(PostMachineSchedulerPass());
906 else
907 addPass(PostRASchedulerPass());
908 }
909
910 // GC
911 derived().addGCPasses(addPass);
912
913 // Basic block placement.
914 if (getOptLevel() != CodeGenOptLevel::None)
915 derived().addBlockPlacement(addPass);
916
917 // Insert before XRay Instrumentation.
918 addPass(FEntryInserterPass());
919
920 addPass(XRayInstrumentationPass());
921 addPass(PatchableFunctionPass());
922
923 derived().addPreEmitPass(addPass);
924
925 if (TM.Options.EnableIPRA)
926 // Collect register usage information and produce a register mask of
927 // clobbered registers, to be used to optimize call sites.
928 addPass(RegUsageInfoCollectorPass());
929
930 addPass(FuncletLayoutPass());
931
932 addPass(StackMapLivenessPass());
933 addPass(LiveDebugValuesPass());
934 addPass(MachineSanitizerBinaryMetadata());
935
936 if (TM.Options.EnableMachineOutliner &&
937 getOptLevel() != CodeGenOptLevel::None &&
938 Opt.EnableMachineOutliner != RunOutliner::NeverOutline) {
939 bool RunOnAllFunctions =
940 (Opt.EnableMachineOutliner == RunOutliner::AlwaysOutline);
941 bool AddOutliner = RunOnAllFunctions || TM.Options.SupportsDefaultOutlining;
942 if (AddOutliner)
943 addPass(MachineOutlinerPass(RunOnAllFunctions));
944 }
945
946 // Add passes that directly emit MI after all other MI passes.
947 derived().addPreEmitPass2(addPass);
948
949 return Error::success();
950}
951
952/// Add passes that optimize machine instructions in SSA form.
953template <typename Derived>
955 AddMachinePass &addPass) const {
956 // Pre-ra tail duplication.
957 addPass(EarlyTailDuplicatePass());
958
959 // Optimize PHIs before DCE: removing dead PHI cycles may make more
960 // instructions dead.
961 addPass(OptimizePHIsPass());
962
963 // This pass merges large allocas. StackSlotColoring is a different pass
964 // which merges spill slots.
965 addPass(StackColoringPass());
966
967 // If the target requests it, assign local variables to stack slots relative
968 // to one another and simplify frame index references where possible.
969 addPass(LocalStackSlotPass());
970
971 // With optimization, dead code should already be eliminated. However
972 // there is one known exception: lowered code for arguments that are only
973 // used by tail calls, where the tail calls reuse the incoming stack
974 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
976
977 // Allow targets to insert passes that improve instruction level parallelism,
978 // like if-conversion. Such passes will typically need dominator trees and
979 // loop info, just like LICM and CSE below.
980 derived().addILPOpts(addPass);
981
982 addPass(EarlyMachineLICMPass());
983 addPass(MachineCSEPass());
984
985 addPass(MachineSinkingPass());
986
987 addPass(PeepholeOptimizerPass());
988 // Clean-up the dead code that may have been generated by peephole
989 // rewriting.
991}
992
993//===---------------------------------------------------------------------===//
994/// Register Allocation Pass Configuration
995//===---------------------------------------------------------------------===//
996
997/// Instantiate the default register allocator pass for this target for either
998/// the optimized or unoptimized allocation path. This will be added to the pass
999/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1000/// in the optimized case.
1001///
1002/// A target that uses the standard regalloc pass order for fast or optimized
1003/// allocation may still override this for per-target regalloc
1004/// selection. But -regalloc=... always takes precedence.
1005template <typename Derived>
1007 AddMachinePass &addPass, bool Optimized) const {
1008 if (Optimized)
1009 addPass(RAGreedyPass());
1010 else
1011 addPass(RAFastPass());
1012}
1013
1014/// Find and instantiate the register allocation pass requested by this target
1015/// at the current optimization level. Different register allocators are
1016/// defined as separate passes because they may require different analysis.
1017template <typename Derived>
1019 bool Optimized) const {
1020 // TODO: Parse Opt.RegAlloc to add register allocator.
1021}
1022
1023template <typename Derived>
1025 AddMachinePass &addPass) const {
1026 // TODO: Ensure allocator is default or fast.
1027 addRegAllocPass(addPass, false);
1028 return Error::success();
1029}
1030
1031template <typename Derived>
1033 AddMachinePass &addPass) const {
1034 // Add the selected register allocation pass.
1035 addRegAllocPass(addPass, true);
1036
1037 // Allow targets to change the register assignments before rewriting.
1038 derived().addPreRewrite(addPass);
1039
1040 // Finally rewrite virtual registers.
1041 addPass(VirtRegRewriterPass());
1042 // Perform stack slot coloring and post-ra machine LICM.
1043 //
1044 // FIXME: Re-enable coloring with register when it's capable of adding
1045 // kill markers.
1046 addPass(StackSlotColoringPass());
1047
1048 return Error::success();
1049}
1050
1051/// Add the minimum set of target-independent passes that are required for
1052/// register allocation. No coalescing or scheduling.
1053template <typename Derived>
1055 AddMachinePass &addPass) const {
1056 addPass(PHIEliminationPass());
1057 addPass(TwoAddressInstructionPass());
1058 return derived().addRegAssignmentFast(addPass);
1059}
1060
1061/// Add standard target-independent passes that are tightly coupled with
1062/// optimized register allocation, including coalescing, machine instruction
1063/// scheduling, and register allocation itself.
1064template <typename Derived>
1066 AddMachinePass &addPass) const {
1067 addPass(DetectDeadLanesPass());
1068
1069 addPass(InitUndefPass());
1070
1071 addPass(ProcessImplicitDefsPass());
1072
1073 // Edge splitting is smarter with machine loop info.
1074 addPass(PHIEliminationPass());
1075
1076 // Eventually, we want to run LiveIntervals before PHI elimination.
1077 if (Opt.EarlyLiveIntervals)
1078 addPass(LiveIntervalsPass());
1079
1080 addPass(TwoAddressInstructionPass());
1081 addPass(RegisterCoalescerPass());
1082
1083 // The machine scheduler may accidentally create disconnected components
1084 // when moving subregister definitions around, avoid this by splitting them to
1085 // separate vregs before. Splitting can also improve reg. allocation quality.
1086 addPass(RenameIndependentSubregsPass());
1087
1088 // PreRA instruction scheduling.
1089 addPass(MachineSchedulerPass());
1090
1091 if (derived().addRegAssignmentOptimized(addPass)) {
1092 // Allow targets to expand pseudo instructions depending on the choice of
1093 // registers before MachineCopyPropagation.
1094 derived().addPostRewrite(addPass);
1095
1096 // Copy propagate to forward register uses and try to eliminate COPYs that
1097 // were not coalesced.
1098 addPass(MachineCopyPropagationPass());
1099
1100 // Run post-ra machine LICM to hoist reloads / remats.
1101 //
1102 // FIXME: can this move into MachineLateOptimization?
1103 addPass(MachineLICMPass());
1104 }
1105}
1106
1107//===---------------------------------------------------------------------===//
1108/// Post RegAlloc Pass Configuration
1109//===---------------------------------------------------------------------===//
1110
1111/// Add passes that optimize machine instructions after register allocation.
1112template <typename Derived>
1114 AddMachinePass &addPass) const {
1115 // Branch folding must be run after regalloc and prolog/epilog insertion.
1116 addPass(BranchFolderPass());
1117
1118 // Tail duplication.
1119 // Note that duplicating tail just increases code size and degrades
1120 // performance for targets that require Structured Control Flow.
1121 // In addition it can also make CFG irreducible. Thus we disable it.
1122 if (!TM.requiresStructuredCFG())
1123 addPass(TailDuplicatePass());
1124
1125 // Cleanup of redundant (identical) address/immediate loads.
1126 addPass(MachineLateInstrsCleanupPass());
1127
1128 // Copy propagation.
1129 addPass(MachineCopyPropagationPass());
1130}
1131
1132/// Add standard basic block placement passes.
1133template <typename Derived>
1135 AddMachinePass &addPass) const {
1136 addPass(MachineBlockPlacementPass());
1137 // Run a separate pass to collect block placement statistics.
1139 addPass(MachineBlockPlacementStatsPass());
1140}
1141
1142} // namespace llvm
1143
1144#endif // LLVM_PASSES_CODEGENPASSBUILDER_H
This is the interface for LLVM's primary stateless and local alias analysis.
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Defines an IR pass for CodeGen Prepare.
std::string Name
This file defines passes to print out IR in various granularities.
This file contains the declaration of the InterleavedAccessPass class, its corresponding pass name is...
This header provides classes for managing a pipeline of passes over loops in LLVM IR.
The header file for the LowerConstantIntrinsics pass as used by the new pass manager.
if(VerifyEach)
ModulePassManager MPM
const char LLVMTargetMachineRef TM
PassInstrumentationCallbacks PIC
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
This header defines various interfaces for pass management in LLVM.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This is the interface for a metadata-based scoped no-alias analysis.
This file contains the declaration of the SelectOptimizePass class, its corresponding pass name is se...
This file defines the SmallVector class.
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
This is the interface for a metadata-based TBAA.
static const char PassName[]
AddIRPass(ModulePassManager &MPM, const DerivedT &PB)
void operator()(PassT &&Pass, StringRef Name=PassT::name())
AddMachinePass(ModulePassManager &MPM, const DerivedT &PB)
void operator()(PassT &&Pass, bool Force=false, StringRef Name=PassT::name())
This class provides access to building LLVM's passes.
Error addLegalizeMachineIR(AddMachinePass &) const
This method should install a legalize pass, which converts the instruction sequence into one that can...
void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const
void addISelPasses(AddIRPass &) const
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
Error addInstSelector(AddMachinePass &) const
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
PassInstrumentationCallbacks * getPassInstrumentationCallbacks() const
void addPreEmitPass(AddMachinePass &) const
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Error addIRTranslator(AddMachinePass &) const
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
Error addGlobalInstructionSelect(AddMachinePass &) const
This method should install a (global) instruction selector pass, which converts possibly generic inst...
void addPostRewrite(AddMachinePass &) const
Add passes to be run immediately after virtual registers are rewritten to physical registers.
Error addRegBankSelect(AddMachinePass &) const
This method should install a register bank selector pass, which assigns register banks to virtual reg...
void addPreSched2(AddMachinePass &) const
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
void addPreLegalizeMachineIR(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before legalization.
Error buildPipeline(ModulePassManager &MPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType) const
void addOptimizedRegAlloc(AddMachinePass &) const
addOptimizedRegAlloc - Add passes related to register allocation.
decltype(std::declval< PassT & >().run(std::declval< Function & >(), std::declval< FunctionAnalysisManager & >())) is_function_pass_t
void addGCPasses(AddMachinePass &) const
addGCPasses - Add late codegen passes that analyze code for garbage collection.
void addMachineSSAOptimization(AddMachinePass &) const
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Error addRegAssignmentOptimized(AddMachinePass &) const
Error addCoreISelPasses(AddMachinePass &) const
Add the actual instruction selection passes.
PassInstrumentationCallbacks * PIC
void addPassesToHandleExceptions(AddIRPass &) const
Add passes to lower exception handling for the code generator.
void addPreGlobalInstructionSelect(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before the (global) ins...
void addMachineLateOptimization(AddMachinePass &) const
Add passes that optimize machine instructions after register allocation.
void addISelPrepare(AddIRPass &) const
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
void addPostRegAlloc(AddMachinePass &) const
This method may be implemented by targets that want to run passes after register allocation pass pipe...
void addGlobalMergePass(AddIRPass &) const
Target can override this to add GlobalMergePass before all IR passes.
void addCodeGenPrepare(AddIRPass &) const
Add pass to prepare the LLVM IR for code generation.
bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
void addPreISel(AddIRPass &) const
{{@ For GlobalISel
void addPreRegBankSelect(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before the register ban...
decltype(std::declval< PassT & >().run(std::declval< Module & >(), std::declval< ModuleAnalysisManager & >())) is_module_pass_t
void addBlockPlacement(AddMachinePass &) const
Add standard basic block placement passes.
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
CodeGenOptLevel getOptLevel() const
void addPreEmitPass2(AddMachinePass &) const
Targets may add passes immediately before machine code is emitted in this callback.
std::function< Expected< std::unique_ptr< MCStreamer > >(MCContext &)> CreateMCStreamer
void addIRPasses(AddIRPass &) const
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
decltype(std::declval< PassT & >().run(std::declval< MachineFunction & >(), std::declval< MachineFunctionAnalysisManager & >())) is_machine_function_pass_t
void addRegAllocPass(AddMachinePass &, bool Optimized) const
addMachinePasses helper to create the target-selected or overriden regalloc pass.
void addILPOpts(AddMachinePass &) const
Add passes that optimize instruction level parallelism for out-of-order targets.
Error addRegAssignmentFast(AddMachinePass &) const
Add core register alloator passes which do the actual register assignment and rewriting.
void addPreRewrite(AddMachinePass &) const
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
Error addMachinePasses(AddMachinePass &) const
Add the complete, standard set of LLVM CodeGen passes.
CodeGenPassBuilder(LLVMTargetMachine &TM, CGPassBuilderOption Opts, PassInstrumentationCallbacks *PIC)
void addPreRegAlloc(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before register allocat...
void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const
Utilities for targets to add passes to the pass manager.
Error addFastRegAlloc(AddMachinePass &) const
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
LowerIntrinsics - This pass rewrites calls to the llvm.gcread or llvm.gcwrite intrinsics,...
Definition: GCMetadata.h:195
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Expected< std::unique_ptr< MCStreamer > > createMCStreamer(raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType, MCContext &Ctx)
Performs Loop Strength Reduce Pass.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:787
Context object for machine code objects.
Definition: MCContext.h:76
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
StringRef getPassNameForClassName(StringRef ClassName)
Get the pass name for a given pass class name.
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT &&Pass)
Definition: PassManager.h:273
bool isEmpty() const
Returns if the pass manager contains any passes.
Definition: PassManager.h:296
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
Pass (for the new pass manager) for printing a Function as LLVM's text IR assembly.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetOptions Options
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
static Expected< StartStopInfo > getStartStopInfo(PassInstrumentationCallbacks &PIC)
Returns pass name in -stop-before or -stop-after NOTE: New pass manager migration only.
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
Create a verifier pass.
Definition: Verifier.h:132
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:444
unique_function is a type-erasing functor similar to std::function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
PassManager< Function > FunctionPassManager
Convenience typedef for a pass manager over functions.
Definition: PassManager.h:315
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:943
std::error_code inconvertibleErrorCode()
The value returned by this function can be returned from convertToErrorCode for Error values where no...
Definition: Error.cpp:90
PassManager< MachineFunction > MachineFunctionPassManager
Convenience typedef for a pass manager over functions.
typename detail::detector< void, Op, Args... >::value_t is_detected
Detects if a given trait holds for some set of arguments 'Args'.
Definition: STLExtras.h:79
CodeGenFileType
These enums are meant to be passed into addPassesToEmitFile to indicate what type of file to emit,...
Definition: CodeGen.h:83
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
ModuleToMachineFunctionPassAdaptor createModuleToMachineFunctionPassAdaptor(MachineFunctionPassT &&Pass)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
Definition: SmallVector.h:1135
std::enable_if_t< is_detected< HasRunOnLoopT, LoopPassT >::value, FunctionToLoopPassAdaptor > createFunctionToLoopPassAdaptor(LoopPassT &&Pass, bool UseMemorySSA=false, bool UseBlockFrequencyInfo=false, bool UseBranchProbabilityInfo=false)
A function to deduce a loop pass type and wrap it in the templated adaptor.
std::optional< bool > EnableGlobalISelOption
std::optional< bool > EnableIPRA
std::optional< bool > OptimizeRegAlloc
std::optional< bool > EnableFastISelOption
std::optional< GlobalISelAbortMode > EnableGlobalISelAbort
A utility pass template to force an analysis result to be available.
Definition: PassManager.h:969