LLVM  14.0.0git
CodeGenPassBuilder.h
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1 //===- Construction of codegen pass pipelines ------------------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// Interfaces for registering analysis passes, producing common pass manager
11 /// configurations, and parsing of pass pipelines.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_CODEGENPASSBUILDER_H
16 #define LLVM_CODEGEN_CODEGENPASSBUILDER_H
17 
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringRef.h"
35 #include "llvm/IR/PassManager.h"
36 #include "llvm/IR/Verifier.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/Error.h"
46 #include "llvm/Transforms/Scalar.h"
54 #include "llvm/Transforms/Utils.h"
57 #include <cassert>
58 #include <type_traits>
59 #include <utility>
60 
61 namespace llvm {
62 
63 // FIXME: Dummy target independent passes definitions that have not yet been
64 // ported to new pass manager. Once they do, remove these.
65 #define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
66  struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
67  template <typename... Ts> PASS_NAME(Ts &&...) {} \
68  PreservedAnalyses run(Function &, FunctionAnalysisManager &) { \
69  return PreservedAnalyses::all(); \
70  } \
71  };
72 #define DUMMY_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
73  struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
74  template <typename... Ts> PASS_NAME(Ts &&...) {} \
75  PreservedAnalyses run(Module &, ModuleAnalysisManager &) { \
76  return PreservedAnalyses::all(); \
77  } \
78  };
79 #define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
80  struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
81  template <typename... Ts> PASS_NAME(Ts &&...) {} \
82  Error run(Module &, MachineFunctionAnalysisManager &) { \
83  return Error::success(); \
84  } \
85  PreservedAnalyses run(MachineFunction &, \
86  MachineFunctionAnalysisManager &) { \
87  llvm_unreachable("this api is to make new PM api happy"); \
88  } \
89  static AnalysisKey Key; \
90  };
91 #define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
92  struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
93  template <typename... Ts> PASS_NAME(Ts &&...) {} \
94  PreservedAnalyses run(MachineFunction &, \
95  MachineFunctionAnalysisManager &) { \
96  return PreservedAnalyses::all(); \
97  } \
98  static AnalysisKey Key; \
99  };
100 #include "MachinePassRegistry.def"
101 
102 /// This class provides access to building LLVM's passes.
103 ///
104 /// Its members provide the baseline state available to passes during their
105 /// construction. The \c MachinePassRegistry.def file specifies how to construct
106 /// all of the built-in passes, and those may reference these members during
107 /// construction.
108 template <typename DerivedT> class CodeGenPassBuilder {
109 public:
112  : TM(TM), Opt(Opts), PIC(PIC) {
113  // Target could set CGPassBuilderOption::MISchedPostRA to true to achieve
114  // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID)
115 
116  // Target should override TM.Options.EnableIPRA in their target-specific
117  // LLVMTM ctor. See TargetMachine::setGlobalISel for example.
118  if (Opt.EnableIPRA)
120 
123 
124  if (!Opt.OptimizeRegAlloc)
126  }
127 
129  raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
130  CodeGenFileType FileType) const;
131 
135  std::pair<StringRef, bool> getPassNameFromLegacyName(StringRef) const;
136 
141  }
142 
144  return PIC;
145  }
146 
147 protected:
148  template <typename PassT> using has_key_t = decltype(PassT::Key);
149 
150  template <typename PassT>
151  using is_module_pass_t = decltype(std::declval<PassT &>().run(
152  std::declval<Module &>(), std::declval<ModuleAnalysisManager &>()));
153 
154  template <typename PassT>
155  using is_function_pass_t = decltype(std::declval<PassT &>().run(
156  std::declval<Function &>(), std::declval<FunctionAnalysisManager &>()));
157 
158  // Function object to maintain state while adding codegen IR passes.
159  class AddIRPass {
160  public:
161  AddIRPass(ModulePassManager &MPM, bool DebugPM, bool Check = true)
162  : MPM(MPM), FPM() {
163  if (Check)
164  AddingFunctionPasses = false;
165  }
168  }
169 
170  // Add Function Pass
171  template <typename PassT>
172  std::enable_if_t<is_detected<is_function_pass_t, PassT>::value>
173  operator()(PassT &&Pass) {
174  if (AddingFunctionPasses && !*AddingFunctionPasses)
175  AddingFunctionPasses = true;
176  FPM.addPass(std::forward<PassT>(Pass));
177  }
178 
179  // Add Module Pass
180  template <typename PassT>
181  std::enable_if_t<is_detected<is_module_pass_t, PassT>::value &&
183  operator()(PassT &&Pass) {
184  assert((!AddingFunctionPasses || !*AddingFunctionPasses) &&
185  "could not add module pass after adding function pass");
186  MPM.addPass(std::forward<PassT>(Pass));
187  }
188 
189  private:
190  ModulePassManager &MPM;
192  // The codegen IR pipeline are mostly function passes with the exceptions of
193  // a few loop and module passes. `AddingFunctionPasses` make sures that
194  // we could only add module passes at the beginning of the pipeline. Once
195  // we begin adding function passes, we could no longer add module passes.
196  // This special-casing introduces less adaptor passes. If we have the need
197  // of adding module passes after function passes, we could change the
198  // implementation to accommodate that.
199  Optional<bool> AddingFunctionPasses;
200  };
201 
202  // Function object to maintain state while adding codegen machine passes.
204  public:
206 
207  template <typename PassT> void operator()(PassT &&Pass) {
208  static_assert(
210  "Machine function pass must define a static member variable `Key`.");
211  for (auto &C : BeforeCallbacks)
212  if (!C(&PassT::Key))
213  return;
214  PM.addPass(std::forward<PassT>(Pass));
215  for (auto &C : AfterCallbacks)
216  C(&PassT::Key);
217  }
218 
219  template <typename PassT> void insertPass(AnalysisKey *ID, PassT Pass) {
220  AfterCallbacks.emplace_back(
221  [this, ID, Pass = std::move(Pass)](AnalysisKey *PassID) {
222  if (PassID == ID)
223  this->PM.addPass(std::move(Pass));
224  });
225  }
226 
228  BeforeCallbacks.emplace_back(
229  [ID](AnalysisKey *PassID) { return PassID != ID; });
230  }
231 
233 
234  private:
236  SmallVector<llvm::unique_function<bool(AnalysisKey *)>, 4> BeforeCallbacks;
237  SmallVector<llvm::unique_function<void(AnalysisKey *)>, 4> AfterCallbacks;
238  };
239 
243 
244  /// Target override these hooks to parse target-specific analyses.
248  std::pair<StringRef, bool> getTargetPassNameFromLegacyName(StringRef) const {
249  return {"", false};
250  }
251 
252  template <typename TMC> TMC &getTM() const { return static_cast<TMC &>(TM); }
254 
255  /// Check whether or not GlobalISel should abort on error.
256  /// When this is disabled, GlobalISel will fall back on SDISel instead of
257  /// erroring out.
260  }
261 
262  /// Check whether or not a diagnostic should be emitted when GlobalISel
263  /// uses the fallback path. In other words, it will emit a diagnostic
264  /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
267  }
268 
269  /// addInstSelector - This method should install an instruction selector pass,
270  /// which converts from LLVM code to machine instructions.
272  return make_error<StringError>("addInstSelector is not overridden",
274  }
275 
276  /// Add passes that optimize instruction level parallelism for out-of-order
277  /// targets. These passes are run while the machine code is still in SSA
278  /// form, so they can use MachineTraceMetrics to control their heuristics.
279  ///
280  /// All passes added here should preserve the MachineDominatorTree,
281  /// MachineLoopInfo, and MachineTraceMetrics analyses.
282  void addILPOpts(AddMachinePass &) const {}
283 
284  /// This method may be implemented by targets that want to run passes
285  /// immediately before register allocation.
287 
288  /// addPreRewrite - Add passes to the optimized register allocation pipeline
289  /// after register allocation is complete, but before virtual registers are
290  /// rewritten to physical registers.
291  ///
292  /// These passes must preserve VirtRegMap and LiveIntervals, and when running
293  /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
294  /// When these passes run, VirtRegMap contains legal physreg assignments for
295  /// all virtual registers.
296  ///
297  /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
298  /// be honored. This is also not generally used for the the fast variant,
299  /// where the allocation and rewriting are done in one pass.
300  void addPreRewrite(AddMachinePass &) const {}
301 
302  /// Add passes to be run immediately after virtual registers are rewritten
303  /// to physical registers.
305 
306  /// This method may be implemented by targets that want to run passes after
307  /// register allocation pass pipeline but before prolog-epilog insertion.
309 
310  /// This method may be implemented by targets that want to run passes after
311  /// prolog-epilog insertion and before the second instruction scheduling pass.
312  void addPreSched2(AddMachinePass &) const {}
313 
314  /// This pass may be implemented by targets that want to run passes
315  /// immediately before machine code is emitted.
317 
318  /// Targets may add passes immediately before machine code is emitted in this
319  /// callback. This is called even later than `addPreEmitPass`.
320  // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
321  // position and remove the `2` suffix here as this callback is what
322  // `addPreEmitPass` *should* be but in reality isn't.
324 
325  /// {{@ For GlobalISel
326  ///
327 
328  /// addPreISel - This method should add any "last minute" LLVM->LLVM
329  /// passes (which are run just before instruction selector).
330  void addPreISel(AddIRPass &) const {
331  llvm_unreachable("addPreISel is not overridden");
332  }
333 
334  /// This method should install an IR translator pass, which converts from
335  /// LLVM code to machine instructions with possibly generic opcodes.
337  return make_error<StringError>("addIRTranslator is not overridden",
339  }
340 
341  /// This method may be implemented by targets that want to run passes
342  /// immediately before legalization.
344 
345  /// This method should install a legalize pass, which converts the instruction
346  /// sequence into one that can be selected by the target.
348  return make_error<StringError>("addLegalizeMachineIR is not overridden",
350  }
351 
352  /// This method may be implemented by targets that want to run passes
353  /// immediately before the register bank selection.
355 
356  /// This method should install a register bank selector pass, which
357  /// assigns register banks to virtual registers without a register
358  /// class or register banks.
360  return make_error<StringError>("addRegBankSelect is not overridden",
362  }
363 
364  /// This method may be implemented by targets that want to run passes
365  /// immediately before the (global) instruction selection.
367 
368  /// This method should install a (global) instruction selector pass, which
369  /// converts possibly generic instructions to fully target-specific
370  /// instructions, thereby constraining all generic virtual registers to
371  /// register classes.
373  return make_error<StringError>(
374  "addGlobalInstructionSelect is not overridden",
376  }
377  /// @}}
378 
379  /// High level function that adds all passes necessary to go from llvm IR
380  /// representation to the MI representation.
381  /// Adds IR based lowering and target specific optimization passes and finally
382  /// the core instruction selection passes.
383  void addISelPasses(AddIRPass &) const;
384 
385  /// Add the actual instruction selection passes. This does not include
386  /// preparation passes on IR.
387  Error addCoreISelPasses(AddMachinePass &) const;
388 
389  /// Add the complete, standard set of LLVM CodeGen passes.
390  /// Fully developed targets will not generally override this.
391  Error addMachinePasses(AddMachinePass &) const;
392 
393  /// Add passes to lower exception handling for the code generator.
394  void addPassesToHandleExceptions(AddIRPass &) const;
395 
396  /// Add common target configurable passes that perform LLVM IR to IR
397  /// transforms following machine independent optimization.
398  void addIRPasses(AddIRPass &) const;
399 
400  /// Add pass to prepare the LLVM IR for code generation. This should be done
401  /// before exception handling preparation passes.
402  void addCodeGenPrepare(AddIRPass &) const;
403 
404  /// Add common passes that perform LLVM IR to IR transforms in preparation for
405  /// instruction selection.
406  void addISelPrepare(AddIRPass &) const;
407 
408  /// Methods with trivial inline returns are convenient points in the common
409  /// codegen pass pipeline where targets may insert passes. Methods with
410  /// out-of-line standard implementations are major CodeGen stages called by
411  /// addMachinePasses. Some targets may override major stages when inserting
412  /// passes is insufficient, but maintaining overriden stages is more work.
413  ///
414 
415  /// addMachineSSAOptimization - Add standard passes that optimize machine
416  /// instructions in SSA form.
417  void addMachineSSAOptimization(AddMachinePass &) const;
418 
419  /// addFastRegAlloc - Add the minimum set of target-independent passes that
420  /// are required for fast register allocation.
421  Error addFastRegAlloc(AddMachinePass &) const;
422 
423  /// addOptimizedRegAlloc - Add passes related to register allocation.
424  /// LLVMTargetMachine provides standard regalloc passes for most targets.
425  void addOptimizedRegAlloc(AddMachinePass &) const;
426 
427  /// Add passes that optimize machine instructions after register allocation.
428  void addMachineLateOptimization(AddMachinePass &) const;
429 
430  /// addGCPasses - Add late codegen passes that analyze code for garbage
431  /// collection. This should return true if GC info should be printed after
432  /// these passes.
433  void addGCPasses(AddMachinePass &) const {}
434 
435  /// Add standard basic block placement passes.
436  void addBlockPlacement(AddMachinePass &) const;
437 
438  using CreateMCStreamer =
439  std::function<Expected<std::unique_ptr<MCStreamer>>(MCContext &)>;
441  llvm_unreachable("addAsmPrinter is not overridden");
442  }
443 
444  /// Utilities for targets to add passes to the pass manager.
445  ///
446 
447  /// createTargetRegisterAllocator - Create the register allocator pass for
448  /// this target at the current optimization level.
449  void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const;
450 
451  /// addMachinePasses helper to create the target-selected or overriden
452  /// regalloc pass.
453  void addRegAllocPass(AddMachinePass &, bool Optimized) const;
454 
455  /// Add core register alloator passes which do the actual register assignment
456  /// and rewriting. \returns true if any passes were added.
457  Error addRegAssignmentFast(AddMachinePass &) const;
458  Error addRegAssignmentOptimized(AddMachinePass &) const;
459 
460 private:
461  DerivedT &derived() { return static_cast<DerivedT &>(*this); }
462  const DerivedT &derived() const {
463  return static_cast<const DerivedT &>(*this);
464  }
465 };
466 
467 template <typename Derived>
470  raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
471  CodeGenFileType FileType) const {
472  AddIRPass addIRPass(MPM, Opt.DebugPM);
473  addISelPasses(addIRPass);
474 
475  AddMachinePass addPass(MFPM);
476  if (auto Err = addCoreISelPasses(addPass))
477  return std::move(Err);
478 
479  if (auto Err = derived().addMachinePasses(addPass))
480  return std::move(Err);
481 
482  derived().addAsmPrinter(
483  addPass, [this, &Out, DwoOut, FileType](MCContext &Ctx) {
484  return this->TM.createMCStreamer(Out, DwoOut, FileType, Ctx);
485  });
486 
487  addPass(FreeMachineFunctionPass());
488  return Error::success();
489 }
490 
492  AAManager AA;
493 
494  // The order in which these are registered determines their priority when
495  // being queried.
496 
497  switch (UseCFLAA) {
500  break;
501  case CFLAAType::Andersen:
503  break;
504  case CFLAAType::Both:
507  break;
508  default:
509  break;
510  }
511 
512  // Basic AliasAnalysis support.
513  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
514  // BasicAliasAnalysis wins if they disagree. This is intended to help
515  // support "obvious" type-punning idioms.
519 
520  return AA;
521 }
522 
523 template <typename Derived>
525  ModuleAnalysisManager &MAM) const {
526 #define MODULE_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \
527  MAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; });
528 #include "MachinePassRegistry.def"
529  derived().registerTargetAnalysis(MAM);
530 }
531 
532 template <typename Derived>
534  FunctionAnalysisManager &FAM) const {
535  FAM.registerPass([this] { return registerAAAnalyses(this->Opt.UseCFLAA); });
536 
537 #define FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \
538  FAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; });
539 #include "MachinePassRegistry.def"
540  derived().registerTargetAnalysis(FAM);
541 }
542 
543 template <typename Derived>
545  MachineFunctionAnalysisManager &MFAM) const {
546 #define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \
547  MFAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; });
548 #include "MachinePassRegistry.def"
549  derived().registerTargetAnalysis(MFAM);
550 }
551 
552 // FIXME: For new PM, use pass name directly in commandline seems good.
553 // Translate stringfied pass name to its old commandline name. Returns the
554 // matching legacy name and a boolean value indicating if the pass is a machine
555 // pass.
556 template <typename Derived>
557 std::pair<StringRef, bool>
559  std::pair<StringRef, bool> Ret;
560  if (Name.empty())
561  return Ret;
562 
563 #define FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
564  if (Name == NAME) \
565  Ret = {#PASS_NAME, false};
566 #define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
567  if (Name == NAME) \
568  Ret = {#PASS_NAME, false};
569 #define MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
570  if (Name == NAME) \
571  Ret = {#PASS_NAME, false};
572 #define DUMMY_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
573  if (Name == NAME) \
574  Ret = {#PASS_NAME, false};
575 #define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
576  if (Name == NAME) \
577  Ret = {#PASS_NAME, true};
578 #define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
579  if (Name == NAME) \
580  Ret = {#PASS_NAME, true};
581 #define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
582  if (Name == NAME) \
583  Ret = {#PASS_NAME, true};
584 #define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
585  if (Name == NAME) \
586  Ret = {#PASS_NAME, true};
587 #include "llvm/CodeGen/MachinePassRegistry.def"
588 
589  if (Ret.first.empty())
590  Ret = derived().getTargetPassNameFromLegacyName(Name);
591 
592  if (Ret.first.empty())
594  Twine("\" pass could not be found."));
595 
596  return Ret;
597 }
598 
599 template <typename Derived>
601  if (TM.useEmulatedTLS())
602  addPass(LowerEmuTLSPass());
603 
604  addPass(PreISelIntrinsicLoweringPass());
605 
606  derived().addIRPasses(addPass);
607  derived().addCodeGenPrepare(addPass);
608  addPassesToHandleExceptions(addPass);
609  derived().addISelPrepare(addPass);
610 }
611 
612 /// Add common target configurable passes that perform LLVM IR to IR transforms
613 /// following machine independent optimization.
614 template <typename Derived>
616  // Before running any passes, run the verifier to determine if the input
617  // coming from the front-end and/or optimizer is valid.
618  if (!Opt.DisableVerify)
619  addPass(VerifierPass());
620 
621  // Run loop strength reduction before anything else.
622  if (getOptLevel() != CodeGenOpt::None && !Opt.DisableLSR) {
624  LoopStrengthReducePass(), /*UseMemorySSA*/ true, Opt.DebugPM));
625  // FIXME: use -stop-after so we could remove PrintLSR
626  if (Opt.PrintLSR)
627  addPass(PrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
628  }
629 
630  if (getOptLevel() != CodeGenOpt::None) {
631  // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
632  // loads and compares. ExpandMemCmpPass then tries to expand those calls
633  // into optimally-sized loads and compares. The transforms are enabled by a
634  // target lowering hook.
635  if (!Opt.DisableMergeICmps)
636  addPass(MergeICmpsPass());
637  addPass(ExpandMemCmpPass());
638  }
639 
640  // Run GC lowering passes for builtin collectors
641  // TODO: add a pass insertion point here
642  addPass(GCLoweringPass());
643  addPass(ShadowStackGCLoweringPass());
644  addPass(LowerConstantIntrinsicsPass());
645 
646  // Make sure that no unreachable blocks are instruction selected.
647  addPass(UnreachableBlockElimPass());
648 
649  // Prepare expensive constants for SelectionDAG.
650  if (getOptLevel() != CodeGenOpt::None && !Opt.DisableConstantHoisting)
651  addPass(ConstantHoistingPass());
652 
653  // Replace calls to LLVM intrinsics (e.g., exp, log) operating on vector
654  // operands with calls to the corresponding functions in a vector library.
655  if (getOptLevel() != CodeGenOpt::None)
656  addPass(ReplaceWithVeclib());
657 
658  if (getOptLevel() != CodeGenOpt::None && !Opt.DisablePartialLibcallInlining)
659  addPass(PartiallyInlineLibCallsPass());
660 
661  // Instrument function entry and exit, e.g. with calls to mcount().
662  addPass(EntryExitInstrumenterPass(/*PostInlining=*/true));
663 
664  // Add scalarization of target's unsupported masked memory intrinsics pass.
665  // the unsupported intrinsic will be replaced with a chain of basic blocks,
666  // that stores/loads element one-by-one if the appropriate mask bit is set.
667  addPass(ScalarizeMaskedMemIntrinPass());
668 
669  // Expand reduction intrinsics into shuffle sequences if the target wants to.
670  addPass(ExpandReductionsPass());
671 }
672 
673 /// Turn exception handling constructs into something the code generators can
674 /// handle.
675 template <typename Derived>
677  AddIRPass &addPass) const {
678  const MCAsmInfo *MCAI = TM.getMCAsmInfo();
679  assert(MCAI && "No MCAsmInfo");
680  switch (MCAI->getExceptionHandlingType()) {
682  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
683  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
684  // catch info can get misplaced when a selector ends up more than one block
685  // removed from the parent invoke(s). This could happen when a landing
686  // pad is shared by multiple invokes and is also a target of a normal
687  // edge from elsewhere.
688  addPass(SjLjEHPreparePass());
693  addPass(DwarfEHPass(getOptLevel()));
694  break;
696  // We support using both GCC-style and MSVC-style exceptions on Windows, so
697  // add both preparation passes. Each pass will only actually run if it
698  // recognizes the personality function.
699  addPass(WinEHPass());
700  addPass(DwarfEHPass(getOptLevel()));
701  break;
703  // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
704  // on catchpads and cleanuppads because it does not outline them into
705  // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
706  // should remove PHIs there.
707  addPass(WinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
708  addPass(WasmEHPass());
709  break;
711  addPass(LowerInvokePass());
712 
713  // The lower invoke pass may create unreachable code. Remove it.
714  addPass(UnreachableBlockElimPass());
715  break;
716  }
717 }
718 
719 /// Add pass to prepare the LLVM IR for code generation. This should be done
720 /// before exception handling preparation passes.
721 template <typename Derived>
723  if (getOptLevel() != CodeGenOpt::None && !Opt.DisableCGP)
724  addPass(CodeGenPreparePass());
725  // TODO: Default ctor'd RewriteSymbolPass is no-op.
726  // addPass(RewriteSymbolPass());
727 }
728 
729 /// Add common passes that perform LLVM IR to IR transforms in preparation for
730 /// instruction selection.
731 template <typename Derived>
733  derived().addPreISel(addPass);
734 
735  // Add both the safe stack and the stack protection passes: each of them will
736  // only protect functions that have corresponding attributes.
737  addPass(SafeStackPass());
738  addPass(StackProtectorPass());
739 
740  if (Opt.PrintISelInput)
741  addPass(PrintFunctionPass(dbgs(),
742  "\n\n*** Final LLVM Code input to ISel ***\n"));
743 
744  // All passes which modify the LLVM IR are now complete; run the verifier
745  // to ensure that the IR is valid.
746  if (!Opt.DisableVerify)
747  addPass(VerifierPass());
748 }
749 
750 template <typename Derived>
752  AddMachinePass &addPass) const {
753  // Enable FastISel with -fast-isel, but allow that to be overridden.
754  TM.setO0WantsFastISel(Opt.EnableFastISelOption.getValueOr(true));
755 
756  // Determine an instruction selector.
757  enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
758  SelectorType Selector;
759 
760  if (Opt.EnableFastISelOption && *Opt.EnableFastISelOption == true)
761  Selector = SelectorType::FastISel;
762  else if ((Opt.EnableGlobalISelOption &&
763  *Opt.EnableGlobalISelOption == true) ||
764  (TM.Options.EnableGlobalISel &&
765  (!Opt.EnableGlobalISelOption ||
766  *Opt.EnableGlobalISelOption == false)))
767  Selector = SelectorType::GlobalISel;
768  else if (TM.getOptLevel() == CodeGenOpt::None && TM.getO0WantsFastISel())
769  Selector = SelectorType::FastISel;
770  else
771  Selector = SelectorType::SelectionDAG;
772 
773  // Set consistently TM.Options.EnableFastISel and EnableGlobalISel.
774  if (Selector == SelectorType::FastISel) {
775  TM.setFastISel(true);
776  TM.setGlobalISel(false);
777  } else if (Selector == SelectorType::GlobalISel) {
778  TM.setFastISel(false);
779  TM.setGlobalISel(true);
780  }
781 
782  // Add instruction selector passes.
783  if (Selector == SelectorType::GlobalISel) {
784  if (auto Err = derived().addIRTranslator(addPass))
785  return std::move(Err);
786 
787  derived().addPreLegalizeMachineIR(addPass);
788 
789  if (auto Err = derived().addLegalizeMachineIR(addPass))
790  return std::move(Err);
791 
792  // Before running the register bank selector, ask the target if it
793  // wants to run some passes.
794  derived().addPreRegBankSelect(addPass);
795 
796  if (auto Err = derived().addRegBankSelect(addPass))
797  return std::move(Err);
798 
799  derived().addPreGlobalInstructionSelect(addPass);
800 
801  if (auto Err = derived().addGlobalInstructionSelect(addPass))
802  return std::move(Err);
803 
804  // Pass to reset the MachineFunction if the ISel failed.
805  addPass(ResetMachineFunctionPass(reportDiagnosticWhenGlobalISelFallback(),
806  isGlobalISelAbortEnabled()));
807 
808  // Provide a fallback path when we do not want to abort on
809  // not-yet-supported input.
810  if (!isGlobalISelAbortEnabled())
811  if (auto Err = derived().addInstSelector(addPass))
812  return std::move(Err);
813 
814  } else if (auto Err = derived().addInstSelector(addPass))
815  return std::move(Err);
816 
817  // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
818  // FinalizeISel.
819  addPass(FinalizeISelPass());
820 
821  // // Print the instruction selected machine code...
822  // printAndVerify("After Instruction Selection");
823 
824  return Error::success();
825 }
826 
827 /// Add the complete set of target-independent postISel code generator passes.
828 ///
829 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
830 /// with nontrivial configuration or multiple passes are broken out below in
831 /// add%Stage routines.
832 ///
833 /// Any CodeGenPassBuilder<Derived>::addXX routine may be overriden by the
834 /// Target. The addPre/Post methods with empty header implementations allow
835 /// injecting target-specific fixups just before or after major stages.
836 /// Additionally, targets have the flexibility to change pass order within a
837 /// stage by overriding default implementation of add%Stage routines below. Each
838 /// technique has maintainability tradeoffs because alternate pass orders are
839 /// not well supported. addPre/Post works better if the target pass is easily
840 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
841 /// the target should override the stage instead.
842 template <typename Derived>
844  AddMachinePass &addPass) const {
845  // Add passes that optimize machine instructions in SSA form.
846  if (getOptLevel() != CodeGenOpt::None) {
847  derived().addMachineSSAOptimization(addPass);
848  } else {
849  // If the target requests it, assign local variables to stack slots relative
850  // to one another and simplify frame index references where possible.
851  addPass(LocalStackSlotPass());
852  }
853 
854  if (TM.Options.EnableIPRA)
855  addPass(RegUsageInfoPropagationPass());
856 
857  // Run pre-ra passes.
858  derived().addPreRegAlloc(addPass);
859 
860  // Run register allocation and passes that are tightly coupled with it,
861  // including phi elimination and scheduling.
862  if (*Opt.OptimizeRegAlloc) {
863  derived().addOptimizedRegAlloc(addPass);
864  } else {
865  if (auto Err = derived().addFastRegAlloc(addPass))
866  return Err;
867  }
868 
869  // Run post-ra passes.
870  derived().addPostRegAlloc(addPass);
871 
872  addPass(RemoveRedundantDebugValuesPass());
873 
874  // Insert prolog/epilog code. Eliminate abstract frame index references...
875  if (getOptLevel() != CodeGenOpt::None) {
876  addPass(PostRAMachineSinkingPass());
877  addPass(ShrinkWrapPass());
878  }
879 
880  addPass(PrologEpilogInserterPass());
881 
882  /// Add passes that optimize machine instructions after register allocation.
883  if (getOptLevel() != CodeGenOpt::None)
884  derived().addMachineLateOptimization(addPass);
885 
886  // Expand pseudo instructions before second scheduling pass.
887  addPass(ExpandPostRAPseudosPass());
888 
889  // Run pre-sched2 passes.
890  derived().addPreSched2(addPass);
891 
892  if (Opt.EnableImplicitNullChecks)
893  addPass(ImplicitNullChecksPass());
894 
895  // Second pass scheduler.
896  // Let Target optionally insert this pass by itself at some other
897  // point.
898  if (getOptLevel() != CodeGenOpt::None &&
899  !TM.targetSchedulesPostRAScheduling()) {
900  if (Opt.MISchedPostRA)
901  addPass(PostMachineSchedulerPass());
902  else
903  addPass(PostRASchedulerPass());
904  }
905 
906  // GC
907  derived().addGCPasses(addPass);
908 
909  // Basic block placement.
910  if (getOptLevel() != CodeGenOpt::None)
911  derived().addBlockPlacement(addPass);
912 
913  // Insert before XRay Instrumentation.
914  addPass(FEntryInserterPass());
915 
916  addPass(XRayInstrumentationPass());
917  addPass(PatchableFunctionPass());
918 
919  derived().addPreEmitPass(addPass);
920 
921  if (TM.Options.EnableIPRA)
922  // Collect register usage information and produce a register mask of
923  // clobbered registers, to be used to optimize call sites.
924  addPass(RegUsageInfoCollectorPass());
925 
926  addPass(FuncletLayoutPass());
927 
928  addPass(StackMapLivenessPass());
929  addPass(LiveDebugValuesPass());
930 
931  if (TM.Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
932  Opt.EnableMachineOutliner != RunOutliner::NeverOutline) {
933  bool RunOnAllFunctions =
934  (Opt.EnableMachineOutliner == RunOutliner::AlwaysOutline);
935  bool AddOutliner = RunOnAllFunctions || TM.Options.SupportsDefaultOutlining;
936  if (AddOutliner)
937  addPass(MachineOutlinerPass(RunOnAllFunctions));
938  }
939 
940  // Add passes that directly emit MI after all other MI passes.
941  derived().addPreEmitPass2(addPass);
942 
943  return Error::success();
944 }
945 
946 /// Add passes that optimize machine instructions in SSA form.
947 template <typename Derived>
949  AddMachinePass &addPass) const {
950  // Pre-ra tail duplication.
951  addPass(EarlyTailDuplicatePass());
952 
953  // Optimize PHIs before DCE: removing dead PHI cycles may make more
954  // instructions dead.
955  addPass(OptimizePHIsPass());
956 
957  // This pass merges large allocas. StackSlotColoring is a different pass
958  // which merges spill slots.
959  addPass(StackColoringPass());
960 
961  // If the target requests it, assign local variables to stack slots relative
962  // to one another and simplify frame index references where possible.
963  addPass(LocalStackSlotPass());
964 
965  // With optimization, dead code should already be eliminated. However
966  // there is one known exception: lowered code for arguments that are only
967  // used by tail calls, where the tail calls reuse the incoming stack
968  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
969  addPass(DeadMachineInstructionElimPass());
970 
971  // Allow targets to insert passes that improve instruction level parallelism,
972  // like if-conversion. Such passes will typically need dominator trees and
973  // loop info, just like LICM and CSE below.
974  derived().addILPOpts(addPass);
975 
976  addPass(EarlyMachineLICMPass());
977  addPass(MachineCSEPass());
978 
979  addPass(MachineSinkingPass());
980 
981  addPass(PeepholeOptimizerPass());
982  // Clean-up the dead code that may have been generated by peephole
983  // rewriting.
984  addPass(DeadMachineInstructionElimPass());
985 }
986 
987 //===---------------------------------------------------------------------===//
988 /// Register Allocation Pass Configuration
989 //===---------------------------------------------------------------------===//
990 
991 /// Instantiate the default register allocator pass for this target for either
992 /// the optimized or unoptimized allocation path. This will be added to the pass
993 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
994 /// in the optimized case.
995 ///
996 /// A target that uses the standard regalloc pass order for fast or optimized
997 /// allocation may still override this for per-target regalloc
998 /// selection. But -regalloc=... always takes precedence.
999 template <typename Derived>
1001  AddMachinePass &addPass, bool Optimized) const {
1002  if (Optimized)
1003  addPass(RAGreedyPass());
1004  else
1005  addPass(RAFastPass());
1006 }
1007 
1008 /// Find and instantiate the register allocation pass requested by this target
1009 /// at the current optimization level. Different register allocators are
1010 /// defined as separate passes because they may require different analysis.
1011 template <typename Derived>
1013  bool Optimized) const {
1014  if (Opt.RegAlloc == RegAllocType::Default)
1015  // With no -regalloc= override, ask the target for a regalloc pass.
1016  derived().addTargetRegisterAllocator(addPass, Optimized);
1017  else if (Opt.RegAlloc == RegAllocType::Basic)
1018  addPass(RABasicPass());
1019  else if (Opt.RegAlloc == RegAllocType::Fast)
1020  addPass(RAFastPass());
1021  else if (Opt.RegAlloc == RegAllocType::Greedy)
1022  addPass(RAGreedyPass());
1023  else if (Opt.RegAlloc == RegAllocType::PBQP)
1024  addPass(RAPBQPPass());
1025  else
1026  llvm_unreachable("unknonwn register allocator type");
1027 }
1028 
1029 template <typename Derived>
1031  AddMachinePass &addPass) const {
1032  if (Opt.RegAlloc != RegAllocType::Default &&
1033  Opt.RegAlloc != RegAllocType::Fast)
1034  return make_error<StringError>(
1035  "Must use fast (default) register allocator for unoptimized regalloc.",
1037 
1038  addRegAllocPass(addPass, false);
1039  return Error::success();
1040 }
1041 
1042 template <typename Derived>
1044  AddMachinePass &addPass) const {
1045  // Add the selected register allocation pass.
1046  addRegAllocPass(addPass, true);
1047 
1048  // Allow targets to change the register assignments before rewriting.
1049  derived().addPreRewrite(addPass);
1050 
1051  // Finally rewrite virtual registers.
1052  addPass(VirtRegRewriterPass());
1053  // Perform stack slot coloring and post-ra machine LICM.
1054  //
1055  // FIXME: Re-enable coloring with register when it's capable of adding
1056  // kill markers.
1057  addPass(StackSlotColoringPass());
1058 
1059  return Error::success();
1060 }
1061 
1062 /// Add the minimum set of target-independent passes that are required for
1063 /// register allocation. No coalescing or scheduling.
1064 template <typename Derived>
1066  AddMachinePass &addPass) const {
1067  addPass(PHIEliminationPass());
1068  addPass(TwoAddressInstructionPass());
1069  return derived().addRegAssignmentFast(addPass);
1070 }
1071 
1072 /// Add standard target-independent passes that are tightly coupled with
1073 /// optimized register allocation, including coalescing, machine instruction
1074 /// scheduling, and register allocation itself.
1075 template <typename Derived>
1077  AddMachinePass &addPass) const {
1078  addPass(DetectDeadLanesPass());
1079 
1080  addPass(ProcessImplicitDefsPass());
1081 
1082  // Edge splitting is smarter with machine loop info.
1083  addPass(PHIEliminationPass());
1084 
1085  // Eventually, we want to run LiveIntervals before PHI elimination.
1086  if (Opt.EarlyLiveIntervals)
1087  addPass(LiveIntervalsPass());
1088 
1089  addPass(TwoAddressInstructionPass());
1090  addPass(RegisterCoalescerPass());
1091 
1092  // The machine scheduler may accidentally create disconnected components
1093  // when moving subregister definitions around, avoid this by splitting them to
1094  // separate vregs before. Splitting can also improve reg. allocation quality.
1095  addPass(RenameIndependentSubregsPass());
1096 
1097  // PreRA instruction scheduling.
1098  addPass(MachineSchedulerPass());
1099 
1100  if (derived().addRegAssignmentOptimized(addPass)) {
1101  // Allow targets to expand pseudo instructions depending on the choice of
1102  // registers before MachineCopyPropagation.
1103  derived().addPostRewrite(addPass);
1104 
1105  // Copy propagate to forward register uses and try to eliminate COPYs that
1106  // were not coalesced.
1107  addPass(MachineCopyPropagationPass());
1108 
1109  // Run post-ra machine LICM to hoist reloads / remats.
1110  //
1111  // FIXME: can this move into MachineLateOptimization?
1112  addPass(MachineLICMPass());
1113  }
1114 }
1115 
1116 //===---------------------------------------------------------------------===//
1117 /// Post RegAlloc Pass Configuration
1118 //===---------------------------------------------------------------------===//
1119 
1120 /// Add passes that optimize machine instructions after register allocation.
1121 template <typename Derived>
1123  AddMachinePass &addPass) const {
1124  // Branch folding must be run after regalloc and prolog/epilog insertion.
1125  addPass(BranchFolderPass());
1126 
1127  // Tail duplication.
1128  // Note that duplicating tail just increases code size and degrades
1129  // performance for targets that require Structured Control Flow.
1130  // In addition it can also make CFG irreducible. Thus we disable it.
1131  if (!TM.requiresStructuredCFG())
1132  addPass(TailDuplicatePass());
1133 
1134  // Copy propagation.
1135  addPass(MachineCopyPropagationPass());
1136 }
1137 
1138 /// Add standard basic block placement passes.
1139 template <typename Derived>
1141  AddMachinePass &addPass) const {
1142  addPass(MachineBlockPlacementPass());
1143  // Run a separate pass to collect block placement statistics.
1144  if (Opt.EnableBlockPlacementStats)
1145  addPass(MachineBlockPlacementStatsPass());
1146 }
1147 
1148 } // namespace llvm
1149 
1150 #endif // LLVM_CODEGEN_CODEGENPASSBUILDER_H
TypeBasedAliasAnalysis.h
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:188
llvm::BasicAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: BasicAliasAnalysis.h:164
llvm::EntryExitInstrumenterPass
Definition: EntryExitInstrumenter.h:24
llvm::ScopedNoAliasAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: ScopedNoAliasAA.h:53
llvm::AAManager
A manager for alias analyses.
Definition: AliasAnalysis.h:1288
llvm::PrintFunctionPass
Pass for printing a Function as LLVM's text IR assembly.
Definition: IRPrintingPasses.h:70
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::RegAllocType::PBQP
@ PBQP
llvm::PreISelIntrinsicLoweringPass
Definition: PreISelIntrinsicLowering.h:22
llvm::CodeGenPassBuilder::getPassInstrumentationCallbacks
PassInstrumentationCallbacks * getPassInstrumentationCallbacks() const
Definition: CodeGenPassBuilder.h:143
FunctionExtras.h
llvm::CodeGenPassBuilder::AddIRPass::~AddIRPass
~AddIRPass()
Definition: CodeGenPassBuilder.h:166
llvm::CodeGenPassBuilder::isGlobalISelAbortEnabled
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Definition: CodeGenPassBuilder.h:258
llvm::ExpandReductionsPass
Definition: ExpandReductions.h:16
MCTargetOptions.h
llvm::CodeGenPassBuilder
This class provides access to building LLVM's passes.
Definition: CodeGenPassBuilder.h:108
llvm::CodeGenPassBuilder::addTargetRegisterAllocator
void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const
Utilities for targets to add passes to the pass manager.
Definition: CodeGenPassBuilder.h:1000
llvm::CodeGenPassBuilder::AddMachinePass::insertPass
void insertPass(AnalysisKey *ID, PassT Pass)
Definition: CodeGenPassBuilder.h:219
llvm::CodeGenPassBuilder::addGCPasses
void addGCPasses(AddMachinePass &) const
addGCPasses - Add late codegen passes that analyze code for garbage collection.
Definition: CodeGenPassBuilder.h:433
llvm::ReplaceWithVeclib
Definition: ReplaceWithVeclib.h:21
llvm::unique_function
unique_function is a type-erasing functor similar to std::function.
Definition: FunctionExtras.h:56
Scalar.h
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
llvm::CodeGenPassBuilder::addILPOpts
void addILPOpts(AddMachinePass &) const
Add passes that optimize instruction level parallelism for out-of-order targets.
Definition: CodeGenPassBuilder.h:282
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
StringRef.h
llvm::PassManager::addPass
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT &&Pass)
Definition: PassManager.h:553
llvm::CodeGenPassBuilder::CodeGenPassBuilder
CodeGenPassBuilder(LLVMTargetMachine &TM, CGPassBuilderOption Opts, PassInstrumentationCallbacks *PIC)
Definition: CodeGenPassBuilder.h:110
llvm::CodeGenPassBuilder::CreateMCStreamer
std::function< Expected< std::unique_ptr< MCStreamer > >(MCContext &)> CreateMCStreamer
Definition: CodeGenPassBuilder.h:439
llvm::CodeGenPassBuilder::addInstSelector
Error addInstSelector(AddMachinePass &) const
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
Definition: CodeGenPassBuilder.h:271
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::RegAllocType::Basic
@ Basic
ErrorHandling.h
llvm::CodeGenPassBuilder::addPostRewrite
void addPostRewrite(AddMachinePass &) const
Add passes to be run immediately after virtual registers are rewritten to physical registers.
Definition: CodeGenPassBuilder.h:304
llvm::Error::success
static ErrorSuccess success()
Create a success value.
Definition: Error.h:331
llvm::CodeGenPassBuilder::registerTargetAnalysis
void registerTargetAnalysis(ModuleAnalysisManager &) const
Target override these hooks to parse target-specific analyses.
Definition: CodeGenPassBuilder.h:245
CGPassBuilderOption.h
Error.h
llvm::VerifierPass
Create a verifier pass.
Definition: Verifier.h:137
FAM
FunctionAnalysisManager FAM
Definition: PassBuilderBindings.cpp:59
llvm::CodeGenPassBuilder::addISelPrepare
void addISelPrepare(AddIRPass &) const
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
Definition: CodeGenPassBuilder.h:732
llvm::CodeGenPassBuilder::addIRTranslator
Error addIRTranslator(AddMachinePass &) const
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
Definition: CodeGenPassBuilder.h:336
llvm::RegAllocType::Fast
@ Fast
llvm::CFLAAType::Andersen
@ Andersen
llvm::CodeGenPassBuilder::addMachinePasses
Error addMachinePasses(AddMachinePass &) const
Add the complete, standard set of LLVM CodeGen passes.
Definition: CodeGenPassBuilder.h:843
llvm::CodeGenPassBuilder::addOptimizedRegAlloc
void addOptimizedRegAlloc(AddMachinePass &) const
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: CodeGenPassBuilder.h:1076
llvm::CodeGenPassBuilder::AddIRPass::operator()
std::enable_if_t< is_detected< is_module_pass_t, PassT >::value &&!is_detected< is_function_pass_t, PassT >::value > operator()(PassT &&Pass)
Definition: CodeGenPassBuilder.h:183
llvm::UseCFLAA
static cl::opt<::CFLAAType > UseCFLAA("use-cfl-aa", cl::init(::CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis"), cl::values(clEnumValN(::CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(::CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(::CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(::CFLAAType::Both, "both", "Enable both variants of CFL-AA")))
llvm::ExceptionHandling::ARM
@ ARM
ARM EHABI.
llvm::Optional< bool >
llvm::RunOutliner::NeverOutline
@ NeverOutline
PartiallyInlineLibCalls.h
llvm::CFLAAType::Both
@ Both
llvm::CodeGenPassBuilder::getOptLevel
CodeGenOpt::Level getOptLevel() const
Definition: CodeGenPassBuilder.h:253
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::LoopStrengthReducePass
Performs Loop Strength Reduce Pass.
Definition: LoopStrengthReduce.h:33
BasicAliasAnalysis.h
llvm::ScalarizeMaskedMemIntrinPass
Definition: ScalarizeMaskedMemIntrin.h:23
llvm::is_detected
typename detail::detector< void, Op, Args... >::value_t is_detected
Detects if a given trait holds for some set of arguments 'Args'.
Definition: STLExtras.h:93
llvm::ExceptionHandling::AIX
@ AIX
AIX Exception Handling.
llvm::TypeBasedAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: TypeBasedAliasAnalysis.h:59
AliasAnalysis.h
llvm::CodeGenPassBuilder::addCodeGenPrepare
void addCodeGenPrepare(AddIRPass &) const
Add pass to prepare the LLVM IR for code generation.
Definition: CodeGenPassBuilder.h:722
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::CodeGenPassBuilder::addPreLegalizeMachineIR
void addPreLegalizeMachineIR(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before legalization.
Definition: CodeGenPassBuilder.h:343
llvm::CodeGenPassBuilder::addPreEmitPass2
void addPreEmitPass2(AddMachinePass &) const
Targets may add passes immediately before machine code is emitted in this callback.
Definition: CodeGenPassBuilder.h:323
llvm::registerAAAnalyses
static AAManager registerAAAnalyses(CFLAAType UseCFLAA)
Definition: CodeGenPassBuilder.h:491
TargetMachine.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetOptions::EnableIPRA
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
Definition: TargetOptions.h:291
MAM
ModuleAnalysisManager MAM
Definition: PassBuilderBindings.cpp:61
llvm::CodeGenPassBuilder::registerTargetAnalysis
void registerTargetAnalysis(FunctionAnalysisManager &) const
Definition: CodeGenPassBuilder.h:246
LowerInvoke.h
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:481
llvm::CodeGenPassBuilder::registerFunctionAnalyses
void registerFunctionAnalyses(FunctionAnalysisManager &) const
Definition: CodeGenPassBuilder.h:533
llvm::MachineFunctionAnalysisManager::FAM
FunctionAnalysisManager * FAM
Definition: MachinePassManager.h:97
llvm::CodeGenPassBuilder::registerAnalyses
void registerAnalyses(MachineFunctionAnalysisManager &MFAM) const
Definition: CodeGenPassBuilder.h:137
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
IRPrintingPasses.h
llvm::ExceptionHandling::Wasm
@ Wasm
WebAssembly Exception Handling.
llvm::CodeGenPassBuilder::is_function_pass_t
decltype(std::declval< PassT & >().run(std::declval< Function & >(), std::declval< FunctionAnalysisManager & >())) is_function_pass_t
Definition: CodeGenPassBuilder.h:156
llvm::CodeGenPassBuilder::addIRPasses
void addIRPasses(AddIRPass &) const
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: CodeGenPassBuilder.h:615
llvm::CodeGenPassBuilder::addPassesToHandleExceptions
void addPassesToHandleExceptions(AddIRPass &) const
Add passes to lower exception handling for the code generator.
Definition: CodeGenPassBuilder.h:676
llvm::CodeGenPassBuilder::is_module_pass_t
decltype(std::declval< PassT & >().run(std::declval< Module & >(), std::declval< ModuleAnalysisManager & >())) is_module_pass_t
Definition: CodeGenPassBuilder.h:152
llvm::CGPassBuilderOption
Definition: CGPassBuilderOption.h:30
ConstantHoisting.h
llvm::CFLSteensAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: CFLSteensAliasAnalysis.h:111
CFLAndersAliasAnalysis.h
llvm::MachineFunctionAnalysisManager
An AnalysisManager<MachineFunction> that also exposes IR analysis results.
Definition: MachinePassManager.h:39
Utils.h
ScopedNoAliasAA.h
llvm::CodeGenPassBuilder::AddIRPass::AddIRPass
AddIRPass(ModulePassManager &MPM, bool DebugPM, bool Check=true)
Definition: CodeGenPassBuilder.h:161
llvm::CodeGenPassBuilder::addRegAssignmentOptimized
Error addRegAssignmentOptimized(AddMachinePass &) const
Definition: CodeGenPassBuilder.h:1043
llvm::MachO::FileType
FileType
Defines the file type this file represents.
Definition: InterfaceFile.h:57
llvm::CodeGenPassBuilder::AddIRPass
Definition: CodeGenPassBuilder.h:159
llvm::CodeGenPassBuilder::addFastRegAlloc
Error addFastRegAlloc(AddMachinePass &) const
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: CodeGenPassBuilder.h:1065
llvm::CodeGenPassBuilder::AddMachinePass::AddMachinePass
AddMachinePass(MachineFunctionPassManager &PM)
Definition: CodeGenPassBuilder.h:205
Check
static bool Check(DecodeStatus &Out, DecodeStatus In)
Definition: AArch64Disassembler.cpp:242
llvm::CodeGenPassBuilder::registerTargetAnalysis
void registerTargetAnalysis(MachineFunctionAnalysisManager &) const
Definition: CodeGenPassBuilder.h:247
llvm::createModuleToFunctionPassAdaptor
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:1227
llvm::CodeGenPassBuilder::has_key_t
decltype(PassT::Key) has_key_t
Definition: CodeGenPassBuilder.h:148
llvm::CodeGenPassBuilder::addGlobalInstructionSelect
Error addGlobalInstructionSelect(AddMachinePass &) const
This method should install a (global) instruction selector pass, which converts possibly generic inst...
Definition: CodeGenPassBuilder.h:372
llvm::raw_pwrite_stream
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:417
llvm::LowerInvokePass
Definition: LowerInvoke.h:22
llvm::CodeGenPassBuilder::AddMachinePass
Definition: CodeGenPassBuilder.h:203
llvm::CodeGenPassBuilder::reportDiagnosticWhenGlobalISelFallback
bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
Definition: CodeGenPassBuilder.h:265
llvm::CodeGenPassBuilder::getTargetPassNameFromLegacyName
std::pair< StringRef, bool > getTargetPassNameFromLegacyName(StringRef) const
Definition: CodeGenPassBuilder.h:248
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MachineFunctionAnalysisManager::MAM
ModuleAnalysisManager * MAM
Definition: MachinePassManager.h:98
llvm::AnalysisKey
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:72
llvm::CodeGenPassBuilder::addRegAssignmentFast
Error addRegAssignmentFast(AddMachinePass &) const
Add core register alloator passes which do the actual register assignment and rewriting.
Definition: CodeGenPassBuilder.h:1030
llvm::UnreachableBlockElimPass
Definition: UnreachableBlockElim.h:29
llvm::CodeGenPassBuilder::addISelPasses
void addISelPasses(AddIRPass &) const
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
Definition: CodeGenPassBuilder.h:600
llvm::createFunctionToLoopPassAdaptor
std::enable_if_t< is_detected< HasRunOnLoopT, LoopPassT >::value, FunctionToLoopPassAdaptor > createFunctionToLoopPassAdaptor(LoopPassT &&Pass, bool UseMemorySSA=false, bool UseBlockFrequencyInfo=false, bool UseBranchProbabilityInfo=false)
A function to deduce a loop pass type and wrap it in the templated adaptor.
Definition: LoopPassManager.h:474
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:121
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::CGPassBuilderOption::EnableGlobalISelAbort
Optional< GlobalISelAbortMode > EnableGlobalISelAbort
Definition: CGPassBuilderOption.h:53
llvm::RegAllocType::Greedy
@ Greedy
MachineModuleInfo.h
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
LoopPassManager.h
llvm::CodeGenPassBuilder::registerModuleAnalyses
void registerModuleAnalyses(ModuleAnalysisManager &) const
Definition: CodeGenPassBuilder.h:524
llvm::CodeGenPassBuilder::buildPipeline
Error buildPipeline(ModulePassManager &MPM, MachineFunctionPassManager &MFPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType) const
Definition: CodeGenPassBuilder.h:468
llvm::CFLAAType::Steensgaard
@ Steensgaard
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::CodeGenPassBuilder::addBlockPlacement
void addBlockPlacement(AddMachinePass &) const
Add standard basic block placement passes.
Definition: CodeGenPassBuilder.h:1140
MCAsmInfo.h
llvm::CodeGenPassBuilder::Opt
CGPassBuilderOption Opt
Definition: CodeGenPassBuilder.h:241
llvm::CodeGenFileType
CodeGenFileType
These enums are meant to be passed into addPassesToEmitFile to indicate what type of file to emit,...
Definition: CodeGen.h:63
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::CodeGenPassBuilder::addPreEmitPass
void addPreEmitPass(AddMachinePass &) const
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Definition: CodeGenPassBuilder.h:316
llvm::CodeGenPassBuilder::addPreGlobalInstructionSelect
void addPreGlobalInstructionSelect(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before the (global) ins...
Definition: CodeGenPassBuilder.h:366
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::RunOutliner::AlwaysOutline
@ AlwaysOutline
llvm::GlobalISelAbortMode::DisableWithDiag
@ DisableWithDiag
llvm::CodeGenPassBuilder::addAsmPrinter
void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const
Definition: CodeGenPassBuilder.h:440
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
llvm::CodeGenPassBuilder::addLegalizeMachineIR
Error addLegalizeMachineIR(AddMachinePass &) const
This method should install a legalize pass, which converts the instruction sequence into one that can...
Definition: CodeGenPassBuilder.h:347
llvm::CodeGenPassBuilder::AddMachinePass::operator()
void operator()(PassT &&Pass)
Definition: CodeGenPassBuilder.h:207
llvm::PassManager< Module >
MergeICmps.h
llvm::CodeGenPassBuilder::addPreRewrite
void addPreRewrite(AddMachinePass &) const
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
Definition: CodeGenPassBuilder.h:300
llvm::CodeGenPassBuilder::addPostRegAlloc
void addPostRegAlloc(AddMachinePass &) const
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Definition: CodeGenPassBuilder.h:308
MachinePassManager.h
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
Verifier.h
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
LoopStrengthReduce.h
llvm::CodeGenPassBuilder::PIC
PassInstrumentationCallbacks * PIC
Definition: CodeGenPassBuilder.h:242
llvm::inconvertibleErrorCode
std::error_code inconvertibleErrorCode()
The value returned by this function can be returned from convertToErrorCode for Error values where no...
Definition: Error.cpp:77
llvm::CodeGenPassBuilder::registerMachineFunctionAnalyses
void registerMachineFunctionAnalyses(MachineFunctionAnalysisManager &) const
Definition: CodeGenPassBuilder.h:544
llvm::CGPassBuilderOption::OptimizeRegAlloc
Optional< bool > OptimizeRegAlloc
Definition: CGPassBuilderOption.h:31
llvm::CodeGenPassBuilder::addRegBankSelect
Error addRegBankSelect(AddMachinePass &) const
This method should install a register bank selector pass, which assigns register banks to virtual reg...
Definition: CodeGenPassBuilder.h:359
llvm::TargetOptions::GlobalISelAbort
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
Definition: TargetOptions.h:237
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::ExceptionHandling::WinEH
@ WinEH
Windows Exception Handling.
PassManager.h
llvm::PartiallyInlineLibCallsPass
Definition: PartiallyInlineLibCalls.h:22
LowerConstantIntrinsics.h
llvm::CodeGenPassBuilder::AddMachinePass::releasePM
MachineFunctionPassManager releasePM()
Definition: CodeGenPassBuilder.h:232
llvm::MachineFunctionPassManager::addPass
void addPass(PassT &&Pass)
Definition: MachinePassManager.h:153
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:406
ScalarizeMaskedMemIntrin.h
UnreachableBlockElim.h
llvm::AnalysisManager::registerPass
bool registerPass(PassBuilderT &&PassBuilder)
Register an analysis pass with the manager.
Definition: PassManager.h:845
llvm::MachineFunctionPassManager
MachineFunctionPassManager adds/removes below features to/from the base PassManager template instanti...
Definition: MachinePassManager.h:130
llvm::CodeGenPassBuilder::addCoreISelPasses
Error addCoreISelPasses(AddMachinePass &) const
Add the actual instruction selection passes.
Definition: CodeGenPassBuilder.h:751
llvm::AAManager::registerFunctionAnalysis
void registerFunctionAnalysis()
Register a specific AA result.
Definition: AliasAnalysis.h:1293
llvm::ExceptionHandling::None
@ None
No exception support.
CodeGen.h
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:762
llvm::GlobalISelAbortMode::Enable
@ Enable
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
SmallVector.h
ExpandReductions.h
llvm::CodeGenPassBuilder::addPreRegBankSelect
void addPreRegBankSelect(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before the register ban...
Definition: CodeGenPassBuilder.h:354
llvm::LowerConstantIntrinsicsPass
Definition: LowerConstantIntrinsics.h:23
llvm::PassInstrumentationCallbacks
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
Definition: PassInstrumentation.h:66
ReplaceWithVeclib.h
llvm::CFLAAType
CFLAAType
Definition: CGPassBuilderOption.h:26
MCStreamer.h
TargetTransformInfo.h
llvm::CodeGenPassBuilder::addMachineSSAOptimization
void addMachineSSAOptimization(AddMachinePass &) const
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Definition: CodeGenPassBuilder.h:948
llvm::CodeGenPassBuilder::AddIRPass::operator()
std::enable_if_t< is_detected< is_function_pass_t, PassT >::value > operator()(PassT &&Pass)
Definition: CodeGenPassBuilder.h:173
llvm::CodeGenPassBuilder::addRegAllocPass
void addRegAllocPass(AddMachinePass &, bool Optimized) const
addMachinePasses helper to create the target-selected or overriden regalloc pass.
Definition: CodeGenPassBuilder.h:1012
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:44
llvm::CFLAndersAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: CFLAndersAliasAnalysis.h:94
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::CodeGenPassBuilder::getTM
TMC & getTM() const
Definition: CodeGenPassBuilder.h:252
llvm::CodeGenPassBuilder::addPreISel
void addPreISel(AddIRPass &) const
{{@ For GlobalISel
Definition: CodeGenPassBuilder.h:330
EntryExitInstrumenter.h
llvm::RegAllocType::Default
@ Default
llvm::CodeGenPassBuilder::addMachineLateOptimization
void addMachineLateOptimization(AddMachinePass &) const
Add passes that optimize machine instructions after register allocation.
Definition: CodeGenPassBuilder.h:1122
llvm::CGPassBuilderOption::EnableIPRA
Optional< bool > EnableIPRA
Definition: CGPassBuilderOption.h:32
llvm::CodeGenPassBuilder::AddMachinePass::disablePass
void disablePass(AnalysisKey *ID)
Definition: CodeGenPassBuilder.h:227
llvm::ConstantHoistingPass
Definition: ConstantHoisting.h:124
llvm::CodeGenPassBuilder::addPreRegAlloc
void addPreRegAlloc(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before register allocat...
Definition: CodeGenPassBuilder.h:286
MPM
ModulePassManager MPM
Definition: PassBuilderBindings.cpp:70
llvm::ExceptionHandling::DwarfCFI
@ DwarfCFI
DWARF-like instruction based exceptions.
Debug.h
llvm::MergeICmpsPass
Definition: MergeICmps.h:18
llvm::CodeGenPassBuilder::addPreSched2
void addPreSched2(AddMachinePass &) const
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Definition: CodeGenPassBuilder.h:312
PreISelIntrinsicLowering.h
CFLSteensAliasAnalysis.h
llvm::CodeGenPassBuilder::getPassNameFromLegacyName
std::pair< StringRef, bool > getPassNameFromLegacyName(StringRef) const
Definition: CodeGenPassBuilder.h:558
llvm::CodeGenPassBuilder::TM
LLVMTargetMachine & TM
Definition: CodeGenPassBuilder.h:240
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38