LLVM  13.0.0git
CodeGenPassBuilder.h
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1 //===- Construction of codegen pass pipelines ------------------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// Interfaces for registering analysis passes, producing common pass manager
11 /// configurations, and parsing of pass pipelines.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_CODEGENPASSBUILDER_H
16 #define LLVM_CODEGEN_CODEGENPASSBUILDER_H
17 
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringRef.h"
35 #include "llvm/IR/PassManager.h"
36 #include "llvm/IR/Verifier.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/Error.h"
46 #include "llvm/Transforms/Scalar.h"
54 #include "llvm/Transforms/Utils.h"
57 #include <cassert>
58 #include <string>
59 #include <type_traits>
60 #include <utility>
61 
62 namespace llvm {
63 
64 // FIXME: Dummy target independent passes definitions that have not yet been
65 // ported to new pass manager. Once they do, remove these.
66 #define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
67  struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
68  template <typename... Ts> PASS_NAME(Ts &&...) {} \
69  PreservedAnalyses run(Function &, FunctionAnalysisManager &) { \
70  return PreservedAnalyses::all(); \
71  } \
72  };
73 #define DUMMY_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
74  struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
75  template <typename... Ts> PASS_NAME(Ts &&...) {} \
76  PreservedAnalyses run(Module &, ModuleAnalysisManager &) { \
77  return PreservedAnalyses::all(); \
78  } \
79  };
80 #define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
81  struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
82  template <typename... Ts> PASS_NAME(Ts &&...) {} \
83  Error run(Module &, MachineFunctionAnalysisManager &) { \
84  return Error::success(); \
85  } \
86  PreservedAnalyses run(MachineFunction &, \
87  MachineFunctionAnalysisManager &) { \
88  llvm_unreachable("this api is to make new PM api happy"); \
89  } \
90  static AnalysisKey Key; \
91  };
92 #define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
93  struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
94  template <typename... Ts> PASS_NAME(Ts &&...) {} \
95  PreservedAnalyses run(MachineFunction &, \
96  MachineFunctionAnalysisManager &) { \
97  return PreservedAnalyses::all(); \
98  } \
99  static AnalysisKey Key; \
100  };
101 #include "MachinePassRegistry.def"
102 
103 /// This class provides access to building LLVM's passes.
104 ///
105 /// Its members provide the baseline state available to passes during their
106 /// construction. The \c MachinePassRegistry.def file specifies how to construct
107 /// all of the built-in passes, and those may reference these members during
108 /// construction.
109 template <typename DerivedT> class CodeGenPassBuilder {
110 public:
113  : TM(TM), Opt(Opts), PIC(PIC) {
114  // Target could set CGPassBuilderOption::MISchedPostRA to true to achieve
115  // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID)
116 
117  // Target should override TM.Options.EnableIPRA in their target-specific
118  // LLVMTM ctor. See TargetMachine::setGlobalISel for example.
119  if (Opt.EnableIPRA)
121 
124 
125  if (!Opt.OptimizeRegAlloc)
127  }
128 
130  raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
131  CodeGenFileType FileType) const;
132 
136  std::pair<StringRef, bool> getPassNameFromLegacyName(StringRef) const;
137 
142  }
143 
145  return PIC;
146  }
147 
148 protected:
149  template <typename PassT> using has_key_t = decltype(PassT::Key);
150 
151  template <typename PassT>
152  using is_module_pass_t = decltype(std::declval<PassT &>().run(
153  std::declval<Module &>(), std::declval<ModuleAnalysisManager &>()));
154 
155  template <typename PassT>
156  using is_function_pass_t = decltype(std::declval<PassT &>().run(
157  std::declval<Function &>(), std::declval<FunctionAnalysisManager &>()));
158 
159  // Function object to maintain state while adding codegen IR passes.
160  class AddIRPass {
161  public:
162  AddIRPass(ModulePassManager &MPM, bool DebugPM, bool Check = true)
163  : MPM(MPM), FPM(DebugPM) {
164  if (Check)
165  AddingFunctionPasses = false;
166  }
169  }
170 
171  // Add Function Pass
172  template <typename PassT>
173  std::enable_if_t<is_detected<is_function_pass_t, PassT>::value>
174  operator()(PassT &&Pass) {
175  if (AddingFunctionPasses && !*AddingFunctionPasses)
176  AddingFunctionPasses = true;
177  FPM.addPass(std::forward<PassT>(Pass));
178  }
179 
180  // Add Module Pass
181  template <typename PassT>
182  std::enable_if_t<is_detected<is_module_pass_t, PassT>::value &&
184  operator()(PassT &&Pass) {
185  assert((!AddingFunctionPasses || !*AddingFunctionPasses) &&
186  "could not add module pass after adding function pass");
187  MPM.addPass(std::forward<PassT>(Pass));
188  }
189 
190  private:
191  ModulePassManager &MPM;
193  // The codegen IR pipeline are mostly function passes with the exceptions of
194  // a few loop and module passes. `AddingFunctionPasses` make sures that
195  // we could only add module passes at the beginning of the pipeline. Once
196  // we begin adding function passes, we could no longer add module passes.
197  // This special-casing introduces less adaptor passes. If we have the need
198  // of adding module passes after function passes, we could change the
199  // implementation to accommodate that.
200  Optional<bool> AddingFunctionPasses;
201  };
202 
203  // Function object to maintain state while adding codegen machine passes.
205  public:
207 
208  template <typename PassT> void operator()(PassT &&Pass) {
209  static_assert(
211  "Machine function pass must define a static member variable `Key`.");
212  for (auto &C : BeforeCallbacks)
213  if (!C(&PassT::Key))
214  return;
215  PM.addPass(std::forward<PassT>(Pass));
216  for (auto &C : AfterCallbacks)
217  C(&PassT::Key);
218  }
219 
220  template <typename PassT> void insertPass(AnalysisKey *ID, PassT Pass) {
221  AfterCallbacks.emplace_back(
222  [this, ID, Pass = std::move(Pass)](AnalysisKey *PassID) {
223  if (PassID == ID)
224  this->PM.addPass(std::move(Pass));
225  });
226  }
227 
229  BeforeCallbacks.emplace_back(
230  [ID](AnalysisKey *PassID) { return PassID != ID; });
231  }
232 
234 
235  private:
237  SmallVector<llvm::unique_function<bool(AnalysisKey *)>, 4> BeforeCallbacks;
238  SmallVector<llvm::unique_function<void(AnalysisKey *)>, 4> AfterCallbacks;
239  };
240 
244 
245  /// Target override these hooks to parse target-specific analyses.
249  std::pair<StringRef, bool> getTargetPassNameFromLegacyName(StringRef) const {
250  return {"", false};
251  }
252 
253  template <typename TMC> TMC &getTM() const { return static_cast<TMC &>(TM); }
255 
256  /// Check whether or not GlobalISel should abort on error.
257  /// When this is disabled, GlobalISel will fall back on SDISel instead of
258  /// erroring out.
261  }
262 
263  /// Check whether or not a diagnostic should be emitted when GlobalISel
264  /// uses the fallback path. In other words, it will emit a diagnostic
265  /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
268  }
269 
270  /// addInstSelector - This method should install an instruction selector pass,
271  /// which converts from LLVM code to machine instructions.
273  return make_error<StringError>("addInstSelector is not overridden",
275  }
276 
277  /// Add passes that optimize instruction level parallelism for out-of-order
278  /// targets. These passes are run while the machine code is still in SSA
279  /// form, so they can use MachineTraceMetrics to control their heuristics.
280  ///
281  /// All passes added here should preserve the MachineDominatorTree,
282  /// MachineLoopInfo, and MachineTraceMetrics analyses.
283  void addILPOpts(AddMachinePass &) const {}
284 
285  /// This method may be implemented by targets that want to run passes
286  /// immediately before register allocation.
288 
289  /// addPreRewrite - Add passes to the optimized register allocation pipeline
290  /// after register allocation is complete, but before virtual registers are
291  /// rewritten to physical registers.
292  ///
293  /// These passes must preserve VirtRegMap and LiveIntervals, and when running
294  /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
295  /// When these passes run, VirtRegMap contains legal physreg assignments for
296  /// all virtual registers.
297  ///
298  /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
299  /// be honored. This is also not generally used for the the fast variant,
300  /// where the allocation and rewriting are done in one pass.
301  void addPreRewrite(AddMachinePass &) const {}
302 
303  /// Add passes to be run immediately after virtual registers are rewritten
304  /// to physical registers.
306 
307  /// This method may be implemented by targets that want to run passes after
308  /// register allocation pass pipeline but before prolog-epilog insertion.
310 
311  /// This method may be implemented by targets that want to run passes after
312  /// prolog-epilog insertion and before the second instruction scheduling pass.
313  void addPreSched2(AddMachinePass &) const {}
314 
315  /// This pass may be implemented by targets that want to run passes
316  /// immediately before machine code is emitted.
318 
319  /// Targets may add passes immediately before machine code is emitted in this
320  /// callback. This is called even later than `addPreEmitPass`.
321  // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
322  // position and remove the `2` suffix here as this callback is what
323  // `addPreEmitPass` *should* be but in reality isn't.
325 
326  /// {{@ For GlobalISel
327  ///
328 
329  /// addPreISel - This method should add any "last minute" LLVM->LLVM
330  /// passes (which are run just before instruction selector).
331  void addPreISel(AddIRPass &) const {
332  llvm_unreachable("addPreISel is not overridden");
333  }
334 
335  /// This method should install an IR translator pass, which converts from
336  /// LLVM code to machine instructions with possibly generic opcodes.
338  return make_error<StringError>("addIRTranslator is not overridden",
340  }
341 
342  /// This method may be implemented by targets that want to run passes
343  /// immediately before legalization.
345 
346  /// This method should install a legalize pass, which converts the instruction
347  /// sequence into one that can be selected by the target.
349  return make_error<StringError>("addLegalizeMachineIR is not overridden",
351  }
352 
353  /// This method may be implemented by targets that want to run passes
354  /// immediately before the register bank selection.
356 
357  /// This method should install a register bank selector pass, which
358  /// assigns register banks to virtual registers without a register
359  /// class or register banks.
361  return make_error<StringError>("addRegBankSelect is not overridden",
363  }
364 
365  /// This method may be implemented by targets that want to run passes
366  /// immediately before the (global) instruction selection.
368 
369  /// This method should install a (global) instruction selector pass, which
370  /// converts possibly generic instructions to fully target-specific
371  /// instructions, thereby constraining all generic virtual registers to
372  /// register classes.
374  return make_error<StringError>(
375  "addGlobalInstructionSelect is not overridden",
377  }
378  /// @}}
379 
380  /// High level function that adds all passes necessary to go from llvm IR
381  /// representation to the MI representation.
382  /// Adds IR based lowering and target specific optimization passes and finally
383  /// the core instruction selection passes.
384  void addISelPasses(AddIRPass &) const;
385 
386  /// Add the actual instruction selection passes. This does not include
387  /// preparation passes on IR.
388  Error addCoreISelPasses(AddMachinePass &) const;
389 
390  /// Add the complete, standard set of LLVM CodeGen passes.
391  /// Fully developed targets will not generally override this.
392  Error addMachinePasses(AddMachinePass &) const;
393 
394  /// Add passes to lower exception handling for the code generator.
395  void addPassesToHandleExceptions(AddIRPass &) const;
396 
397  /// Add common target configurable passes that perform LLVM IR to IR
398  /// transforms following machine independent optimization.
399  void addIRPasses(AddIRPass &) const;
400 
401  /// Add pass to prepare the LLVM IR for code generation. This should be done
402  /// before exception handling preparation passes.
403  void addCodeGenPrepare(AddIRPass &) const;
404 
405  /// Add common passes that perform LLVM IR to IR transforms in preparation for
406  /// instruction selection.
407  void addISelPrepare(AddIRPass &) const;
408 
409  /// Methods with trivial inline returns are convenient points in the common
410  /// codegen pass pipeline where targets may insert passes. Methods with
411  /// out-of-line standard implementations are major CodeGen stages called by
412  /// addMachinePasses. Some targets may override major stages when inserting
413  /// passes is insufficient, but maintaining overriden stages is more work.
414  ///
415 
416  /// addMachineSSAOptimization - Add standard passes that optimize machine
417  /// instructions in SSA form.
418  void addMachineSSAOptimization(AddMachinePass &) const;
419 
420  /// addFastRegAlloc - Add the minimum set of target-independent passes that
421  /// are required for fast register allocation.
422  Error addFastRegAlloc(AddMachinePass &) const;
423 
424  /// addOptimizedRegAlloc - Add passes related to register allocation.
425  /// LLVMTargetMachine provides standard regalloc passes for most targets.
426  void addOptimizedRegAlloc(AddMachinePass &) const;
427 
428  /// Add passes that optimize machine instructions after register allocation.
429  void addMachineLateOptimization(AddMachinePass &) const;
430 
431  /// addGCPasses - Add late codegen passes that analyze code for garbage
432  /// collection. This should return true if GC info should be printed after
433  /// these passes.
434  void addGCPasses(AddMachinePass &) const {}
435 
436  /// Add standard basic block placement passes.
437  void addBlockPlacement(AddMachinePass &) const;
438 
439  using CreateMCStreamer =
440  std::function<Expected<std::unique_ptr<MCStreamer>>(MCContext &)>;
442  llvm_unreachable("addAsmPrinter is not overridden");
443  }
444 
445  /// Utilities for targets to add passes to the pass manager.
446  ///
447 
448  /// createTargetRegisterAllocator - Create the register allocator pass for
449  /// this target at the current optimization level.
450  void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const;
451 
452  /// addMachinePasses helper to create the target-selected or overriden
453  /// regalloc pass.
454  void addRegAllocPass(AddMachinePass &, bool Optimized) const;
455 
456  /// Add core register alloator passes which do the actual register assignment
457  /// and rewriting. \returns true if any passes were added.
458  Error addRegAssignmentFast(AddMachinePass &) const;
459  Error addRegAssignmentOptimized(AddMachinePass &) const;
460 
461 private:
462  DerivedT &derived() { return static_cast<DerivedT &>(*this); }
463  const DerivedT &derived() const {
464  return static_cast<const DerivedT &>(*this);
465  }
466 };
467 
468 template <typename Derived>
471  raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
472  CodeGenFileType FileType) const {
473  AddIRPass addIRPass(MPM, Opt.DebugPM);
474  addISelPasses(addIRPass);
475 
476  AddMachinePass addPass(MFPM);
477  if (auto Err = addCoreISelPasses(addPass))
478  return std::move(Err);
479 
480  if (auto Err = derived().addMachinePasses(addPass))
481  return std::move(Err);
482 
483  derived().addAsmPrinter(
484  addPass, [this, &Out, DwoOut, FileType](MCContext &Ctx) {
485  return this->TM.createMCStreamer(Out, DwoOut, FileType, Ctx);
486  });
487 
488  addPass(FreeMachineFunctionPass());
489  return Error::success();
490 }
491 
493  AAManager AA;
494 
495  // The order in which these are registered determines their priority when
496  // being queried.
497 
498  switch (UseCFLAA) {
501  break;
502  case CFLAAType::Andersen:
504  break;
505  case CFLAAType::Both:
508  break;
509  default:
510  break;
511  }
512 
513  // Basic AliasAnalysis support.
514  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
515  // BasicAliasAnalysis wins if they disagree. This is intended to help
516  // support "obvious" type-punning idioms.
520 
521  return AA;
522 }
523 
524 template <typename Derived>
526  ModuleAnalysisManager &MAM) const {
527 #define MODULE_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \
528  MAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; });
529 #include "MachinePassRegistry.def"
530  derived().registerTargetAnalysis(MAM);
531 }
532 
533 template <typename Derived>
535  FunctionAnalysisManager &FAM) const {
536  FAM.registerPass([this] { return registerAAAnalyses(this->Opt.UseCFLAA); });
537 
538 #define FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \
539  FAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; });
540 #include "MachinePassRegistry.def"
541  derived().registerTargetAnalysis(FAM);
542 }
543 
544 template <typename Derived>
546  MachineFunctionAnalysisManager &MFAM) const {
547 #define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \
548  MFAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; });
549 #include "MachinePassRegistry.def"
550  derived().registerTargetAnalysis(MFAM);
551 }
552 
553 // FIXME: For new PM, use pass name directly in commandline seems good.
554 // Translate stringfied pass name to its old commandline name. Returns the
555 // matching legacy name and a boolean value indicating if the pass is a machine
556 // pass.
557 template <typename Derived>
558 std::pair<StringRef, bool>
560  std::pair<StringRef, bool> Ret;
561  if (Name.empty())
562  return Ret;
563 
564 #define FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
565  if (Name == NAME) \
566  Ret = {#PASS_NAME, false};
567 #define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
568  if (Name == NAME) \
569  Ret = {#PASS_NAME, false};
570 #define MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
571  if (Name == NAME) \
572  Ret = {#PASS_NAME, false};
573 #define DUMMY_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
574  if (Name == NAME) \
575  Ret = {#PASS_NAME, false};
576 #define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
577  if (Name == NAME) \
578  Ret = {#PASS_NAME, true};
579 #define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
580  if (Name == NAME) \
581  Ret = {#PASS_NAME, true};
582 #define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
583  if (Name == NAME) \
584  Ret = {#PASS_NAME, true};
585 #define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \
586  if (Name == NAME) \
587  Ret = {#PASS_NAME, true};
588 #include "llvm/CodeGen/MachinePassRegistry.def"
589 
590  if (Ret.first.empty())
591  Ret = derived().getTargetPassNameFromLegacyName(Name);
592 
593  if (Ret.first.empty())
595  Twine("\" pass could not be found."));
596 
597  return Ret;
598 }
599 
600 template <typename Derived>
602  if (TM.useEmulatedTLS())
603  addPass(LowerEmuTLSPass());
604 
605  addPass(PreISelIntrinsicLoweringPass());
606 
607  derived().addIRPasses(addPass);
608  derived().addCodeGenPrepare(addPass);
609  addPassesToHandleExceptions(addPass);
610  derived().addISelPrepare(addPass);
611 }
612 
613 /// Add common target configurable passes that perform LLVM IR to IR transforms
614 /// following machine independent optimization.
615 template <typename Derived>
617  // Before running any passes, run the verifier to determine if the input
618  // coming from the front-end and/or optimizer is valid.
619  if (!Opt.DisableVerify)
620  addPass(VerifierPass());
621 
622  // Run loop strength reduction before anything else.
623  if (getOptLevel() != CodeGenOpt::None && !Opt.DisableLSR) {
625  LoopStrengthReducePass(), /*UseMemorySSA*/ true, Opt.DebugPM));
626  // FIXME: use -stop-after so we could remove PrintLSR
627  if (Opt.PrintLSR)
628  addPass(PrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
629  }
630 
631  if (getOptLevel() != CodeGenOpt::None) {
632  // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
633  // loads and compares. ExpandMemCmpPass then tries to expand those calls
634  // into optimally-sized loads and compares. The transforms are enabled by a
635  // target lowering hook.
636  if (!Opt.DisableMergeICmps)
637  addPass(MergeICmpsPass());
638  addPass(ExpandMemCmpPass());
639  }
640 
641  // Run GC lowering passes for builtin collectors
642  // TODO: add a pass insertion point here
643  addPass(GCLoweringPass());
644  addPass(ShadowStackGCLoweringPass());
645  addPass(LowerConstantIntrinsicsPass());
646 
647  // Make sure that no unreachable blocks are instruction selected.
648  addPass(UnreachableBlockElimPass());
649 
650  // Prepare expensive constants for SelectionDAG.
651  if (getOptLevel() != CodeGenOpt::None && !Opt.DisableConstantHoisting)
652  addPass(ConstantHoistingPass());
653 
654  // Replace calls to LLVM intrinsics (e.g., exp, log) operating on vector
655  // operands with calls to the corresponding functions in a vector library.
656  if (getOptLevel() != CodeGenOpt::None)
657  addPass(ReplaceWithVeclib());
658 
659  if (getOptLevel() != CodeGenOpt::None && !Opt.DisablePartialLibcallInlining)
660  addPass(PartiallyInlineLibCallsPass());
661 
662  // Instrument function entry and exit, e.g. with calls to mcount().
663  addPass(EntryExitInstrumenterPass(/*PostInlining=*/true));
664 
665  // Add scalarization of target's unsupported masked memory intrinsics pass.
666  // the unsupported intrinsic will be replaced with a chain of basic blocks,
667  // that stores/loads element one-by-one if the appropriate mask bit is set.
668  addPass(ScalarizeMaskedMemIntrinPass());
669 
670  // Expand reduction intrinsics into shuffle sequences if the target wants to.
671  addPass(ExpandReductionsPass());
672 }
673 
674 /// Turn exception handling constructs into something the code generators can
675 /// handle.
676 template <typename Derived>
678  AddIRPass &addPass) const {
679  const MCAsmInfo *MCAI = TM.getMCAsmInfo();
680  assert(MCAI && "No MCAsmInfo");
681  switch (MCAI->getExceptionHandlingType()) {
683  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
684  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
685  // catch info can get misplaced when a selector ends up more than one block
686  // removed from the parent invoke(s). This could happen when a landing
687  // pad is shared by multiple invokes and is also a target of a normal
688  // edge from elsewhere.
689  addPass(SjLjEHPreparePass());
694  addPass(DwarfEHPass(getOptLevel()));
695  break;
697  // We support using both GCC-style and MSVC-style exceptions on Windows, so
698  // add both preparation passes. Each pass will only actually run if it
699  // recognizes the personality function.
700  addPass(WinEHPass());
701  addPass(DwarfEHPass(getOptLevel()));
702  break;
704  // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
705  // on catchpads and cleanuppads because it does not outline them into
706  // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
707  // should remove PHIs there.
708  addPass(WinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
709  addPass(WasmEHPass());
710  break;
712  addPass(LowerInvokePass());
713 
714  // The lower invoke pass may create unreachable code. Remove it.
715  addPass(UnreachableBlockElimPass());
716  break;
717  }
718 }
719 
720 /// Add pass to prepare the LLVM IR for code generation. This should be done
721 /// before exception handling preparation passes.
722 template <typename Derived>
724  if (getOptLevel() != CodeGenOpt::None && !Opt.DisableCGP)
725  addPass(CodeGenPreparePass());
726  // TODO: Default ctor'd RewriteSymbolPass is no-op.
727  // addPass(RewriteSymbolPass());
728 }
729 
730 /// Add common passes that perform LLVM IR to IR transforms in preparation for
731 /// instruction selection.
732 template <typename Derived>
734  derived().addPreISel(addPass);
735 
736  // Add both the safe stack and the stack protection passes: each of them will
737  // only protect functions that have corresponding attributes.
738  addPass(SafeStackPass());
739  addPass(StackProtectorPass());
740 
741  if (Opt.PrintISelInput)
742  addPass(PrintFunctionPass(dbgs(),
743  "\n\n*** Final LLVM Code input to ISel ***\n"));
744 
745  // All passes which modify the LLVM IR are now complete; run the verifier
746  // to ensure that the IR is valid.
747  if (!Opt.DisableVerify)
748  addPass(VerifierPass());
749 }
750 
751 template <typename Derived>
753  AddMachinePass &addPass) const {
754  // Enable FastISel with -fast-isel, but allow that to be overridden.
755  TM.setO0WantsFastISel(Opt.EnableFastISelOption.getValueOr(true));
756 
757  // Determine an instruction selector.
758  enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
759  SelectorType Selector;
760 
761  if (Opt.EnableFastISelOption && *Opt.EnableFastISelOption == true)
762  Selector = SelectorType::FastISel;
763  else if ((Opt.EnableGlobalISelOption &&
764  *Opt.EnableGlobalISelOption == true) ||
765  (TM.Options.EnableGlobalISel &&
766  (!Opt.EnableGlobalISelOption ||
767  *Opt.EnableGlobalISelOption == false)))
768  Selector = SelectorType::GlobalISel;
769  else if (TM.getOptLevel() == CodeGenOpt::None && TM.getO0WantsFastISel())
770  Selector = SelectorType::FastISel;
771  else
772  Selector = SelectorType::SelectionDAG;
773 
774  // Set consistently TM.Options.EnableFastISel and EnableGlobalISel.
775  if (Selector == SelectorType::FastISel) {
776  TM.setFastISel(true);
777  TM.setGlobalISel(false);
778  } else if (Selector == SelectorType::GlobalISel) {
779  TM.setFastISel(false);
780  TM.setGlobalISel(true);
781  }
782 
783  // Add instruction selector passes.
784  if (Selector == SelectorType::GlobalISel) {
785  if (auto Err = derived().addIRTranslator(addPass))
786  return std::move(Err);
787 
788  derived().addPreLegalizeMachineIR(addPass);
789 
790  if (auto Err = derived().addLegalizeMachineIR(addPass))
791  return std::move(Err);
792 
793  // Before running the register bank selector, ask the target if it
794  // wants to run some passes.
795  derived().addPreRegBankSelect(addPass);
796 
797  if (auto Err = derived().addRegBankSelect(addPass))
798  return std::move(Err);
799 
800  derived().addPreGlobalInstructionSelect(addPass);
801 
802  if (auto Err = derived().addGlobalInstructionSelect(addPass))
803  return std::move(Err);
804 
805  // Pass to reset the MachineFunction if the ISel failed.
806  addPass(ResetMachineFunctionPass(reportDiagnosticWhenGlobalISelFallback(),
807  isGlobalISelAbortEnabled()));
808 
809  // Provide a fallback path when we do not want to abort on
810  // not-yet-supported input.
811  if (!isGlobalISelAbortEnabled())
812  if (auto Err = derived().addInstSelector(addPass))
813  return std::move(Err);
814 
815  } else if (auto Err = derived().addInstSelector(addPass))
816  return std::move(Err);
817 
818  // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
819  // FinalizeISel.
820  addPass(FinalizeISelPass());
821 
822  // // Print the instruction selected machine code...
823  // printAndVerify("After Instruction Selection");
824 
825  return Error::success();
826 }
827 
828 /// Add the complete set of target-independent postISel code generator passes.
829 ///
830 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
831 /// with nontrivial configuration or multiple passes are broken out below in
832 /// add%Stage routines.
833 ///
834 /// Any CodeGenPassBuilder<Derived>::addXX routine may be overriden by the
835 /// Target. The addPre/Post methods with empty header implementations allow
836 /// injecting target-specific fixups just before or after major stages.
837 /// Additionally, targets have the flexibility to change pass order within a
838 /// stage by overriding default implementation of add%Stage routines below. Each
839 /// technique has maintainability tradeoffs because alternate pass orders are
840 /// not well supported. addPre/Post works better if the target pass is easily
841 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
842 /// the target should override the stage instead.
843 template <typename Derived>
845  AddMachinePass &addPass) const {
846  // Add passes that optimize machine instructions in SSA form.
847  if (getOptLevel() != CodeGenOpt::None) {
848  derived().addMachineSSAOptimization(addPass);
849  } else {
850  // If the target requests it, assign local variables to stack slots relative
851  // to one another and simplify frame index references where possible.
852  addPass(LocalStackSlotPass());
853  }
854 
855  if (TM.Options.EnableIPRA)
856  addPass(RegUsageInfoPropagationPass());
857 
858  // Run pre-ra passes.
859  derived().addPreRegAlloc(addPass);
860 
861  // Run register allocation and passes that are tightly coupled with it,
862  // including phi elimination and scheduling.
863  if (*Opt.OptimizeRegAlloc) {
864  derived().addOptimizedRegAlloc(addPass);
865  } else {
866  if (auto Err = derived().addFastRegAlloc(addPass))
867  return Err;
868  }
869 
870  // Run post-ra passes.
871  derived().addPostRegAlloc(addPass);
872 
873  // Insert prolog/epilog code. Eliminate abstract frame index references...
874  if (getOptLevel() != CodeGenOpt::None) {
875  addPass(PostRAMachineSinkingPass());
876  addPass(ShrinkWrapPass());
877  }
878 
879  addPass(PrologEpilogInserterPass());
880 
881  /// Add passes that optimize machine instructions after register allocation.
882  if (getOptLevel() != CodeGenOpt::None)
883  derived().addMachineLateOptimization(addPass);
884 
885  // Expand pseudo instructions before second scheduling pass.
886  addPass(ExpandPostRAPseudosPass());
887 
888  // Run pre-sched2 passes.
889  derived().addPreSched2(addPass);
890 
891  if (Opt.EnableImplicitNullChecks)
892  addPass(ImplicitNullChecksPass());
893 
894  // Second pass scheduler.
895  // Let Target optionally insert this pass by itself at some other
896  // point.
897  if (getOptLevel() != CodeGenOpt::None &&
898  !TM.targetSchedulesPostRAScheduling()) {
899  if (Opt.MISchedPostRA)
900  addPass(PostMachineSchedulerPass());
901  else
902  addPass(PostRASchedulerPass());
903  }
904 
905  // GC
906  derived().addGCPasses(addPass);
907 
908  // Basic block placement.
909  if (getOptLevel() != CodeGenOpt::None)
910  derived().addBlockPlacement(addPass);
911 
912  // Insert before XRay Instrumentation.
913  addPass(FEntryInserterPass());
914 
915  addPass(XRayInstrumentationPass());
916  addPass(PatchableFunctionPass());
917 
918  derived().addPreEmitPass(addPass);
919 
920  if (TM.Options.EnableIPRA)
921  // Collect register usage information and produce a register mask of
922  // clobbered registers, to be used to optimize call sites.
923  addPass(RegUsageInfoCollectorPass());
924 
925  addPass(FuncletLayoutPass());
926 
927  addPass(StackMapLivenessPass());
928  addPass(LiveDebugValuesPass());
929 
930  if (TM.Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
931  Opt.EnableMachineOutliner != RunOutliner::NeverOutline) {
932  bool RunOnAllFunctions =
933  (Opt.EnableMachineOutliner == RunOutliner::AlwaysOutline);
934  bool AddOutliner = RunOnAllFunctions || TM.Options.SupportsDefaultOutlining;
935  if (AddOutliner)
936  addPass(MachineOutlinerPass(RunOnAllFunctions));
937  }
938 
939  // Add passes that directly emit MI after all other MI passes.
940  derived().addPreEmitPass2(addPass);
941 
942  return Error::success();
943 }
944 
945 /// Add passes that optimize machine instructions in SSA form.
946 template <typename Derived>
948  AddMachinePass &addPass) const {
949  // Pre-ra tail duplication.
950  addPass(EarlyTailDuplicatePass());
951 
952  // Optimize PHIs before DCE: removing dead PHI cycles may make more
953  // instructions dead.
954  addPass(OptimizePHIsPass());
955 
956  // This pass merges large allocas. StackSlotColoring is a different pass
957  // which merges spill slots.
958  addPass(StackColoringPass());
959 
960  // If the target requests it, assign local variables to stack slots relative
961  // to one another and simplify frame index references where possible.
962  addPass(LocalStackSlotPass());
963 
964  // With optimization, dead code should already be eliminated. However
965  // there is one known exception: lowered code for arguments that are only
966  // used by tail calls, where the tail calls reuse the incoming stack
967  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
968  addPass(DeadMachineInstructionElimPass());
969 
970  // Allow targets to insert passes that improve instruction level parallelism,
971  // like if-conversion. Such passes will typically need dominator trees and
972  // loop info, just like LICM and CSE below.
973  derived().addILPOpts(addPass);
974 
975  addPass(EarlyMachineLICMPass());
976  addPass(MachineCSEPass());
977 
978  addPass(MachineSinkingPass());
979 
980  addPass(PeepholeOptimizerPass());
981  // Clean-up the dead code that may have been generated by peephole
982  // rewriting.
983  addPass(DeadMachineInstructionElimPass());
984 }
985 
986 //===---------------------------------------------------------------------===//
987 /// Register Allocation Pass Configuration
988 //===---------------------------------------------------------------------===//
989 
990 /// Instantiate the default register allocator pass for this target for either
991 /// the optimized or unoptimized allocation path. This will be added to the pass
992 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
993 /// in the optimized case.
994 ///
995 /// A target that uses the standard regalloc pass order for fast or optimized
996 /// allocation may still override this for per-target regalloc
997 /// selection. But -regalloc=... always takes precedence.
998 template <typename Derived>
1000  AddMachinePass &addPass, bool Optimized) const {
1001  if (Optimized)
1002  addPass(RAGreedyPass());
1003  else
1004  addPass(RAFastPass());
1005 }
1006 
1007 /// Find and instantiate the register allocation pass requested by this target
1008 /// at the current optimization level. Different register allocators are
1009 /// defined as separate passes because they may require different analysis.
1010 template <typename Derived>
1012  bool Optimized) const {
1013  if (Opt.RegAlloc == RegAllocType::Default)
1014  // With no -regalloc= override, ask the target for a regalloc pass.
1015  derived().addTargetRegisterAllocator(addPass, Optimized);
1016  else if (Opt.RegAlloc == RegAllocType::Basic)
1017  addPass(RABasicPass());
1018  else if (Opt.RegAlloc == RegAllocType::Fast)
1019  addPass(RAFastPass());
1020  else if (Opt.RegAlloc == RegAllocType::Greedy)
1021  addPass(RAGreedyPass());
1022  else if (Opt.RegAlloc == RegAllocType::PBQP)
1023  addPass(RAPBQPPass());
1024  else
1025  llvm_unreachable("unknonwn register allocator type");
1026 }
1027 
1028 template <typename Derived>
1030  AddMachinePass &addPass) const {
1031  if (Opt.RegAlloc != RegAllocType::Default &&
1032  Opt.RegAlloc != RegAllocType::Fast)
1033  return make_error<StringError>(
1034  "Must use fast (default) register allocator for unoptimized regalloc.",
1036 
1037  addRegAllocPass(addPass, false);
1038  return Error::success();
1039 }
1040 
1041 template <typename Derived>
1043  AddMachinePass &addPass) const {
1044  // Add the selected register allocation pass.
1045  addRegAllocPass(addPass, true);
1046 
1047  // Allow targets to change the register assignments before rewriting.
1048  derived().addPreRewrite(addPass);
1049 
1050  // Finally rewrite virtual registers.
1051  addPass(VirtRegRewriterPass());
1052  // Perform stack slot coloring and post-ra machine LICM.
1053  //
1054  // FIXME: Re-enable coloring with register when it's capable of adding
1055  // kill markers.
1056  addPass(StackSlotColoringPass());
1057 
1058  return Error::success();
1059 }
1060 
1061 /// Add the minimum set of target-independent passes that are required for
1062 /// register allocation. No coalescing or scheduling.
1063 template <typename Derived>
1065  AddMachinePass &addPass) const {
1066  addPass(PHIEliminationPass());
1067  addPass(TwoAddressInstructionPass());
1068  return derived().addRegAssignmentFast(addPass);
1069 }
1070 
1071 /// Add standard target-independent passes that are tightly coupled with
1072 /// optimized register allocation, including coalescing, machine instruction
1073 /// scheduling, and register allocation itself.
1074 template <typename Derived>
1076  AddMachinePass &addPass) const {
1077  addPass(DetectDeadLanesPass());
1078 
1079  addPass(ProcessImplicitDefsPass());
1080 
1081  // Edge splitting is smarter with machine loop info.
1082  addPass(PHIEliminationPass());
1083 
1084  // Eventually, we want to run LiveIntervals before PHI elimination.
1085  if (Opt.EarlyLiveIntervals)
1086  addPass(LiveIntervalsPass());
1087 
1088  addPass(TwoAddressInstructionPass());
1089  addPass(RegisterCoalescerPass());
1090 
1091  // The machine scheduler may accidentally create disconnected components
1092  // when moving subregister definitions around, avoid this by splitting them to
1093  // separate vregs before. Splitting can also improve reg. allocation quality.
1094  addPass(RenameIndependentSubregsPass());
1095 
1096  // PreRA instruction scheduling.
1097  addPass(MachineSchedulerPass());
1098 
1099  if (derived().addRegAssignmentOptimized(addPass)) {
1100  // Allow targets to expand pseudo instructions depending on the choice of
1101  // registers before MachineCopyPropagation.
1102  derived().addPostRewrite(addPass);
1103 
1104  // Copy propagate to forward register uses and try to eliminate COPYs that
1105  // were not coalesced.
1106  addPass(MachineCopyPropagationPass());
1107 
1108  // Run post-ra machine LICM to hoist reloads / remats.
1109  //
1110  // FIXME: can this move into MachineLateOptimization?
1111  addPass(MachineLICMPass());
1112  }
1113 }
1114 
1115 //===---------------------------------------------------------------------===//
1116 /// Post RegAlloc Pass Configuration
1117 //===---------------------------------------------------------------------===//
1118 
1119 /// Add passes that optimize machine instructions after register allocation.
1120 template <typename Derived>
1122  AddMachinePass &addPass) const {
1123  // Branch folding must be run after regalloc and prolog/epilog insertion.
1124  addPass(BranchFolderPass());
1125 
1126  // Tail duplication.
1127  // Note that duplicating tail just increases code size and degrades
1128  // performance for targets that require Structured Control Flow.
1129  // In addition it can also make CFG irreducible. Thus we disable it.
1130  if (!TM.requiresStructuredCFG())
1131  addPass(TailDuplicatePass());
1132 
1133  // Copy propagation.
1134  addPass(MachineCopyPropagationPass());
1135 }
1136 
1137 /// Add standard basic block placement passes.
1138 template <typename Derived>
1140  AddMachinePass &addPass) const {
1141  addPass(MachineBlockPlacementPass());
1142  // Run a separate pass to collect block placement statistics.
1143  if (Opt.EnableBlockPlacementStats)
1144  addPass(MachineBlockPlacementStatsPass());
1145 }
1146 
1147 } // namespace llvm
1148 
1149 #endif // LLVM_CODEGEN_CODEGENPASSBUILDER_H
TypeBasedAliasAnalysis.h
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:198
llvm::BasicAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: BasicAliasAnalysis.h:233
llvm::EntryExitInstrumenterPass
Definition: EntryExitInstrumenter.h:24
llvm::ScopedNoAliasAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: ScopedNoAliasAA.h:53
llvm::AAManager
A manager for alias analyses.
Definition: AliasAnalysis.h:1221
llvm::PrintFunctionPass
Pass for printing a Function as LLVM's text IR assembly.
Definition: IRPrintingPasses.h:70
llvm
Definition: AllocatorList.h:23
llvm::RegAllocType::PBQP
@ PBQP
llvm::PreISelIntrinsicLoweringPass
Definition: PreISelIntrinsicLowering.h:22
llvm::CodeGenPassBuilder::getPassInstrumentationCallbacks
PassInstrumentationCallbacks * getPassInstrumentationCallbacks() const
Definition: CodeGenPassBuilder.h:144
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
FunctionExtras.h
llvm::CodeGenPassBuilder::AddIRPass::~AddIRPass
~AddIRPass()
Definition: CodeGenPassBuilder.h:167
llvm::CodeGenPassBuilder::isGlobalISelAbortEnabled
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Definition: CodeGenPassBuilder.h:259
llvm::ExpandReductionsPass
Definition: ExpandReductions.h:16
MCTargetOptions.h
llvm::CodeGenPassBuilder
This class provides access to building LLVM's passes.
Definition: CodeGenPassBuilder.h:109
llvm::CodeGenPassBuilder::addTargetRegisterAllocator
void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const
Utilities for targets to add passes to the pass manager.
Definition: CodeGenPassBuilder.h:999
llvm::CodeGenPassBuilder::AddMachinePass::insertPass
void insertPass(AnalysisKey *ID, PassT Pass)
Definition: CodeGenPassBuilder.h:220
llvm::CodeGenPassBuilder::addGCPasses
void addGCPasses(AddMachinePass &) const
addGCPasses - Add late codegen passes that analyze code for garbage collection.
Definition: CodeGenPassBuilder.h:434
llvm::ReplaceWithVeclib
Definition: ReplaceWithVeclib.h:21
llvm::unique_function
unique_function is a type-erasing functor similar to std::function.
Definition: FunctionExtras.h:54
Scalar.h
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
llvm::CodeGenPassBuilder::addILPOpts
void addILPOpts(AddMachinePass &) const
Add passes that optimize instruction level parallelism for out-of-order targets.
Definition: CodeGenPassBuilder.h:283
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:71
StringRef.h
llvm::CodeGenPassBuilder::CodeGenPassBuilder
CodeGenPassBuilder(LLVMTargetMachine &TM, CGPassBuilderOption Opts, PassInstrumentationCallbacks *PIC)
Definition: CodeGenPassBuilder.h:111
llvm::CodeGenPassBuilder::CreateMCStreamer
std::function< Expected< std::unique_ptr< MCStreamer > >(MCContext &)> CreateMCStreamer
Definition: CodeGenPassBuilder.h:440
llvm::CodeGenPassBuilder::addInstSelector
Error addInstSelector(AddMachinePass &) const
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
Definition: CodeGenPassBuilder.h:272
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::RegAllocType::Basic
@ Basic
ErrorHandling.h
llvm::CodeGenPassBuilder::addPostRewrite
void addPostRewrite(AddMachinePass &) const
Add passes to be run immediately after virtual registers are rewritten to physical registers.
Definition: CodeGenPassBuilder.h:305
llvm::Error::success
static ErrorSuccess success()
Create a success value.
Definition: Error.h:332
llvm::CodeGenPassBuilder::registerTargetAnalysis
void registerTargetAnalysis(ModuleAnalysisManager &) const
Target override these hooks to parse target-specific analyses.
Definition: CodeGenPassBuilder.h:246
CGPassBuilderOption.h
Error.h
llvm::VerifierPass
Create a verifier pass.
Definition: Verifier.h:137
llvm::CodeGenPassBuilder::addISelPrepare
void addISelPrepare(AddIRPass &) const
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
Definition: CodeGenPassBuilder.h:733
llvm::CodeGenPassBuilder::addIRTranslator
Error addIRTranslator(AddMachinePass &) const
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
Definition: CodeGenPassBuilder.h:337
llvm::RegAllocType::Fast
@ Fast
llvm::CFLAAType::Andersen
@ Andersen
llvm::CodeGenPassBuilder::addMachinePasses
Error addMachinePasses(AddMachinePass &) const
Add the complete, standard set of LLVM CodeGen passes.
Definition: CodeGenPassBuilder.h:844
llvm::CodeGenPassBuilder::addOptimizedRegAlloc
void addOptimizedRegAlloc(AddMachinePass &) const
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: CodeGenPassBuilder.h:1075
llvm::CodeGenPassBuilder::AddIRPass::operator()
std::enable_if_t< is_detected< is_module_pass_t, PassT >::value &&!is_detected< is_function_pass_t, PassT >::value > operator()(PassT &&Pass)
Definition: CodeGenPassBuilder.h:184
llvm::ExceptionHandling::ARM
@ ARM
ARM EHABI.
llvm::Optional< bool >
llvm::RunOutliner::NeverOutline
@ NeverOutline
PartiallyInlineLibCalls.h
llvm::CFLAAType::Both
@ Both
llvm::CodeGenPassBuilder::getOptLevel
CodeGenOpt::Level getOptLevel() const
Definition: CodeGenPassBuilder.h:254
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::LoopStrengthReducePass
Performs Loop Strength Reduce Pass.
Definition: LoopStrengthReduce.h:33
BasicAliasAnalysis.h
llvm::ScalarizeMaskedMemIntrinPass
Definition: ScalarizeMaskedMemIntrin.h:23
llvm::is_detected
typename detail::detector< void, Op, Args... >::value_t is_detected
Detects if a given trait holds for some set of arguments 'Args'.
Definition: STLExtras.h:101
llvm::ExceptionHandling::AIX
@ AIX
AIX Exception Handling.
llvm::TypeBasedAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: TypeBasedAliasAnalysis.h:59
AliasAnalysis.h
llvm::CodeGenPassBuilder::addCodeGenPrepare
void addCodeGenPrepare(AddIRPass &) const
Add pass to prepare the LLVM IR for code generation.
Definition: CodeGenPassBuilder.h:723
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::CodeGenPassBuilder::addPreLegalizeMachineIR
void addPreLegalizeMachineIR(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before legalization.
Definition: CodeGenPassBuilder.h:344
llvm::CodeGenPassBuilder::addPreEmitPass2
void addPreEmitPass2(AddMachinePass &) const
Targets may add passes immediately before machine code is emitted in this callback.
Definition: CodeGenPassBuilder.h:324
llvm::registerAAAnalyses
static AAManager registerAAAnalyses(CFLAAType UseCFLAA)
Definition: CodeGenPassBuilder.h:492
TargetMachine.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetOptions::EnableIPRA
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
Definition: TargetOptions.h:281
llvm::CodeGenPassBuilder::registerTargetAnalysis
void registerTargetAnalysis(FunctionAnalysisManager &) const
Definition: CodeGenPassBuilder.h:247
LowerInvoke.h
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:481
llvm::CodeGenPassBuilder::registerFunctionAnalyses
void registerFunctionAnalyses(FunctionAnalysisManager &) const
Definition: CodeGenPassBuilder.h:534
llvm::MachineFunctionAnalysisManager::FAM
FunctionAnalysisManager * FAM
Definition: MachinePassManager.h:98
llvm::CodeGenPassBuilder::registerAnalyses
void registerAnalyses(MachineFunctionAnalysisManager &MFAM) const
Definition: CodeGenPassBuilder.h:138
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
IRPrintingPasses.h
llvm::ExceptionHandling::Wasm
@ Wasm
WebAssembly Exception Handling.
llvm::CodeGenPassBuilder::is_function_pass_t
decltype(std::declval< PassT & >().run(std::declval< Function & >(), std::declval< FunctionAnalysisManager & >())) is_function_pass_t
Definition: CodeGenPassBuilder.h:157
llvm::CodeGenPassBuilder::addIRPasses
void addIRPasses(AddIRPass &) const
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: CodeGenPassBuilder.h:616
llvm::CodeGenPassBuilder::addPassesToHandleExceptions
void addPassesToHandleExceptions(AddIRPass &) const
Add passes to lower exception handling for the code generator.
Definition: CodeGenPassBuilder.h:677
llvm::CodeGenPassBuilder::is_module_pass_t
decltype(std::declval< PassT & >().run(std::declval< Module & >(), std::declval< ModuleAnalysisManager & >())) is_module_pass_t
Definition: CodeGenPassBuilder.h:153
llvm::CGPassBuilderOption
Definition: CGPassBuilderOption.h:31
ConstantHoisting.h
llvm::CFLSteensAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: CFLSteensAliasAnalysis.h:111
CFLAndersAliasAnalysis.h
llvm::MachineFunctionAnalysisManager
An AnalysisManager<MachineFunction> that also exposes IR analysis results.
Definition: MachinePassManager.h:39
Utils.h
ScopedNoAliasAA.h
llvm::CodeGenPassBuilder::AddIRPass::AddIRPass
AddIRPass(ModulePassManager &MPM, bool DebugPM, bool Check=true)
Definition: CodeGenPassBuilder.h:162
llvm::CodeGenPassBuilder::addRegAssignmentOptimized
Error addRegAssignmentOptimized(AddMachinePass &) const
Definition: CodeGenPassBuilder.h:1042
llvm::MachO::FileType
FileType
Defines the file type this file represents.
Definition: InterfaceFile.h:57
llvm::CodeGenPassBuilder::AddIRPass
Definition: CodeGenPassBuilder.h:160
llvm::CodeGenPassBuilder::addFastRegAlloc
Error addFastRegAlloc(AddMachinePass &) const
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: CodeGenPassBuilder.h:1064
llvm::CodeGenPassBuilder::AddMachinePass::AddMachinePass
AddMachinePass(MachineFunctionPassManager &PM)
Definition: CodeGenPassBuilder.h:206
Check
static bool Check(DecodeStatus &Out, DecodeStatus In)
Definition: AArch64Disassembler.cpp:230
llvm::CodeGenPassBuilder::registerTargetAnalysis
void registerTargetAnalysis(MachineFunctionAnalysisManager &) const
Definition: CodeGenPassBuilder.h:248
llvm::createModuleToFunctionPassAdaptor
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT Pass)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:1252
llvm::CodeGenPassBuilder::has_key_t
decltype(PassT::Key) has_key_t
Definition: CodeGenPassBuilder.h:149
llvm::CodeGenPassBuilder::addGlobalInstructionSelect
Error addGlobalInstructionSelect(AddMachinePass &) const
This method should install a (global) instruction selector pass, which converts possibly generic inst...
Definition: CodeGenPassBuilder.h:373
llvm::raw_pwrite_stream
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:406
llvm::LowerInvokePass
Definition: LowerInvoke.h:22
llvm::CodeGenPassBuilder::AddMachinePass
Definition: CodeGenPassBuilder.h:204
llvm::CodeGenPassBuilder::reportDiagnosticWhenGlobalISelFallback
bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
Definition: CodeGenPassBuilder.h:266
llvm::CodeGenPassBuilder::getTargetPassNameFromLegacyName
std::pair< StringRef, bool > getTargetPassNameFromLegacyName(StringRef) const
Definition: CodeGenPassBuilder.h:249
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MachineFunctionAnalysisManager::MAM
ModuleAnalysisManager * MAM
Definition: MachinePassManager.h:99
llvm::AnalysisKey
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:72
UseCFLAA
static cl::opt< CFLAAType > UseCFLAA("use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(CFLAAType::Both, "both", "Enable both variants of CFL-AA")))
llvm::CodeGenPassBuilder::addRegAssignmentFast
Error addRegAssignmentFast(AddMachinePass &) const
Add core register alloator passes which do the actual register assignment and rewriting.
Definition: CodeGenPassBuilder.h:1029
llvm::UnreachableBlockElimPass
Definition: UnreachableBlockElim.h:29
llvm::CodeGenPassBuilder::addISelPasses
void addISelPasses(AddIRPass &) const
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
Definition: CodeGenPassBuilder.h:601
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:115
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::CGPassBuilderOption::EnableGlobalISelAbort
Optional< GlobalISelAbortMode > EnableGlobalISelAbort
Definition: CGPassBuilderOption.h:54
llvm::RegAllocType::Greedy
@ Greedy
MachineModuleInfo.h
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
LoopPassManager.h
llvm::CodeGenPassBuilder::registerModuleAnalyses
void registerModuleAnalyses(ModuleAnalysisManager &) const
Definition: CodeGenPassBuilder.h:525
llvm::CodeGenPassBuilder::buildPipeline
Error buildPipeline(ModulePassManager &MPM, MachineFunctionPassManager &MFPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType) const
Definition: CodeGenPassBuilder.h:469
llvm::CFLAAType::Steensgaard
@ Steensgaard
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::CodeGenPassBuilder::addBlockPlacement
void addBlockPlacement(AddMachinePass &) const
Add standard basic block placement passes.
Definition: CodeGenPassBuilder.h:1139
MCAsmInfo.h
llvm::CodeGenPassBuilder::Opt
CGPassBuilderOption Opt
Definition: CodeGenPassBuilder.h:242
llvm::CodeGenFileType
CodeGenFileType
These enums are meant to be passed into addPassesToEmitFile to indicate what type of file to emit,...
Definition: CodeGen.h:63
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::CodeGenPassBuilder::addPreEmitPass
void addPreEmitPass(AddMachinePass &) const
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Definition: CodeGenPassBuilder.h:317
llvm::CodeGenPassBuilder::addPreGlobalInstructionSelect
void addPreGlobalInstructionSelect(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before the (global) ins...
Definition: CodeGenPassBuilder.h:367
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::RunOutliner::AlwaysOutline
@ AlwaysOutline
llvm::GlobalISelAbortMode::DisableWithDiag
@ DisableWithDiag
llvm::CodeGenPassBuilder::addAsmPrinter
void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const
Definition: CodeGenPassBuilder.h:441
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:281
llvm::CodeGenPassBuilder::addLegalizeMachineIR
Error addLegalizeMachineIR(AddMachinePass &) const
This method should install a legalize pass, which converts the instruction sequence into one that can...
Definition: CodeGenPassBuilder.h:348
llvm::CodeGenPassBuilder::AddMachinePass::operator()
void operator()(PassT &&Pass)
Definition: CodeGenPassBuilder.h:208
llvm::PassManager< Module >
MergeICmps.h
llvm::CodeGenPassBuilder::addPreRewrite
void addPreRewrite(AddMachinePass &) const
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
Definition: CodeGenPassBuilder.h:301
llvm::CodeGenPassBuilder::addPostRegAlloc
void addPostRegAlloc(AddMachinePass &) const
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Definition: CodeGenPassBuilder.h:309
MachinePassManager.h
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
Verifier.h
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
LoopStrengthReduce.h
llvm::CodeGenPassBuilder::PIC
PassInstrumentationCallbacks * PIC
Definition: CodeGenPassBuilder.h:243
llvm::inconvertibleErrorCode
std::error_code inconvertibleErrorCode()
The value returned by this function can be returned from convertToErrorCode for Error values where no...
Definition: Error.cpp:77
llvm::CodeGenPassBuilder::registerMachineFunctionAnalyses
void registerMachineFunctionAnalyses(MachineFunctionAnalysisManager &) const
Definition: CodeGenPassBuilder.h:545
llvm::CGPassBuilderOption::OptimizeRegAlloc
Optional< bool > OptimizeRegAlloc
Definition: CGPassBuilderOption.h:32
llvm::CodeGenPassBuilder::addRegBankSelect
Error addRegBankSelect(AddMachinePass &) const
This method should install a register bank selector pass, which assigns register banks to virtual reg...
Definition: CodeGenPassBuilder.h:360
llvm::TargetOptions::GlobalISelAbort
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
Definition: TargetOptions.h:232
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::ExceptionHandling::WinEH
@ WinEH
Windows Exception Handling.
PassManager.h
llvm::PartiallyInlineLibCallsPass
Definition: PartiallyInlineLibCalls.h:22
LowerConstantIntrinsics.h
llvm::CodeGenPassBuilder::AddMachinePass::releasePM
MachineFunctionPassManager releasePM()
Definition: CodeGenPassBuilder.h:233
llvm::MachineFunctionPassManager::addPass
void addPass(PassT &&Pass)
Definition: MachinePassManager.h:154
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:386
ScalarizeMaskedMemIntrin.h
UnreachableBlockElim.h
llvm::AnalysisManager::registerPass
bool registerPass(PassBuilderT &&PassBuilder)
Register an analysis pass with the manager.
Definition: PassManager.h:847
llvm::MachineFunctionPassManager
MachineFunctionPassManager adds/removes below features to/from the base PassManager template instanti...
Definition: MachinePassManager.h:131
llvm::CodeGenPassBuilder::addCoreISelPasses
Error addCoreISelPasses(AddMachinePass &) const
Add the actual instruction selection passes.
Definition: CodeGenPassBuilder.h:752
llvm::AAManager::registerFunctionAnalysis
void registerFunctionAnalysis()
Register a specific AA result.
Definition: AliasAnalysis.h:1226
llvm::ExceptionHandling::None
@ None
No exception support.
CodeGen.h
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:672
llvm::GlobalISelAbortMode::Enable
@ Enable
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
SmallVector.h
ExpandReductions.h
llvm::CodeGenPassBuilder::addPreRegBankSelect
void addPreRegBankSelect(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before the register ban...
Definition: CodeGenPassBuilder.h:355
llvm::LowerConstantIntrinsicsPass
Definition: LowerConstantIntrinsics.h:23
llvm::PassInstrumentationCallbacks
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
Definition: PassInstrumentation.h:65
ReplaceWithVeclib.h
llvm::CFLAAType
CFLAAType
Definition: CGPassBuilderOption.h:27
MCStreamer.h
llvm::createFunctionToLoopPassAdaptor
std::enable_if_t< is_detected< HasRunOnLoopT, LoopPassT >::value, FunctionToLoopPassAdaptor > createFunctionToLoopPassAdaptor(LoopPassT Pass, bool UseMemorySSA=false, bool UseBlockFrequencyInfo=false, bool DebugLogging=false)
A function to deduce a loop pass type and wrap it in the templated adaptor.
Definition: LoopPassManager.h:449
TargetTransformInfo.h
llvm::CodeGenPassBuilder::addMachineSSAOptimization
void addMachineSSAOptimization(AddMachinePass &) const
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Definition: CodeGenPassBuilder.h:947
llvm::CodeGenPassBuilder::AddIRPass::operator()
std::enable_if_t< is_detected< is_function_pass_t, PassT >::value > operator()(PassT &&Pass)
Definition: CodeGenPassBuilder.h:174
llvm::CodeGenPassBuilder::addRegAllocPass
void addRegAllocPass(AddMachinePass &, bool Optimized) const
addMachinePasses helper to create the target-selected or overriden regalloc pass.
Definition: CodeGenPassBuilder.h:1011
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:43
llvm::CFLAndersAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: CFLAndersAliasAnalysis.h:94
llvm::CodeGenPassBuilder::getTM
TMC & getTM() const
Definition: CodeGenPassBuilder.h:253
llvm::CodeGenPassBuilder::addPreISel
void addPreISel(AddIRPass &) const
{{@ For GlobalISel
Definition: CodeGenPassBuilder.h:331
EntryExitInstrumenter.h
llvm::RegAllocType::Default
@ Default
llvm::CodeGenPassBuilder::addMachineLateOptimization
void addMachineLateOptimization(AddMachinePass &) const
Add passes that optimize machine instructions after register allocation.
Definition: CodeGenPassBuilder.h:1121
llvm::CGPassBuilderOption::EnableIPRA
Optional< bool > EnableIPRA
Definition: CGPassBuilderOption.h:33
llvm::CodeGenPassBuilder::AddMachinePass::disablePass
void disablePass(AnalysisKey *ID)
Definition: CodeGenPassBuilder.h:228
llvm::ConstantHoistingPass
Definition: ConstantHoisting.h:124
llvm::CodeGenPassBuilder::addPreRegAlloc
void addPreRegAlloc(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before register allocat...
Definition: CodeGenPassBuilder.h:287
llvm::ExceptionHandling::DwarfCFI
@ DwarfCFI
DWARF-like instruction based exceptions.
Debug.h
llvm::MergeICmpsPass
Definition: MergeICmps.h:18
llvm::PassManager::addPass
std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT Pass)
Definition: PassManager.h:553
llvm::CodeGenPassBuilder::addPreSched2
void addPreSched2(AddMachinePass &) const
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Definition: CodeGenPassBuilder.h:313
PreISelIntrinsicLowering.h
CFLSteensAliasAnalysis.h
llvm::CodeGenPassBuilder::getPassNameFromLegacyName
std::pair< StringRef, bool > getPassNameFromLegacyName(StringRef) const
Definition: CodeGenPassBuilder.h:559
llvm::CodeGenPassBuilder::TM
LLVMTargetMachine & TM
Definition: CodeGenPassBuilder.h:241
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38