LLVM 19.0.0git
CodeGenPassBuilder.h
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1//===- Construction of codegen pass pipelines ------------------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// Interfaces for producing common pass manager configurations.
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_PASSES_CODEGENPASSBUILDER_H
15#define LLVM_PASSES_CODEGENPASSBUILDER_H
16
18#include "llvm/ADT/StringRef.h"
57#include "llvm/IR/PassManager.h"
58#include "llvm/IR/Verifier.h"
60#include "llvm/MC/MCAsmInfo.h"
63#include "llvm/Support/Debug.h"
64#include "llvm/Support/Error.h"
78#include <cassert>
79#include <type_traits>
80#include <utility>
81
82namespace llvm {
83
84// FIXME: Dummy target independent passes definitions that have not yet been
85// ported to new pass manager. Once they do, remove these.
86#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME) \
87 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
88 template <typename... Ts> PASS_NAME(Ts &&...) {} \
89 PreservedAnalyses run(Function &, FunctionAnalysisManager &) { \
90 return PreservedAnalyses::all(); \
91 } \
92 };
93#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME) \
94 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
95 template <typename... Ts> PASS_NAME(Ts &&...) {} \
96 PreservedAnalyses run(Module &, ModuleAnalysisManager &) { \
97 return PreservedAnalyses::all(); \
98 } \
99 };
100#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME) \
101 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
102 template <typename... Ts> PASS_NAME(Ts &&...) {} \
103 PreservedAnalyses run(MachineFunction &, \
104 MachineFunctionAnalysisManager &) { \
105 return PreservedAnalyses::all(); \
106 } \
107 };
108#include "llvm/Passes/MachinePassRegistry.def"
109
110/// This class provides access to building LLVM's passes.
111///
112/// Its members provide the baseline state available to passes during their
113/// construction. The \c MachinePassRegistry.def file specifies how to construct
114/// all of the built-in passes, and those may reference these members during
115/// construction.
116template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
117public:
118 explicit CodeGenPassBuilder(TargetMachineT &TM,
119 const CGPassBuilderOption &Opts,
121 : TM(TM), Opt(Opts), PIC(PIC) {
122 // Target could set CGPassBuilderOption::MISchedPostRA to true to achieve
123 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID)
124
125 // Target should override TM.Options.EnableIPRA in their target-specific
126 // LLVMTM ctor. See TargetMachine::setGlobalISel for example.
127 if (Opt.EnableIPRA)
128 TM.Options.EnableIPRA = *Opt.EnableIPRA;
129
131 TM.Options.GlobalISelAbort = *Opt.EnableGlobalISelAbort;
132
135 }
136
138 raw_pwrite_stream *DwoOut,
139 CodeGenFileType FileType) const;
140
142 return PIC;
143 }
144
145protected:
146 template <typename PassT>
147 using has_required_t = decltype(std::declval<PassT &>().isRequired());
148
149 template <typename PassT>
150 using is_module_pass_t = decltype(std::declval<PassT &>().run(
151 std::declval<Module &>(), std::declval<ModuleAnalysisManager &>()));
152
153 template <typename PassT>
154 using is_function_pass_t = decltype(std::declval<PassT &>().run(
155 std::declval<Function &>(), std::declval<FunctionAnalysisManager &>()));
156
157 template <typename PassT>
158 using is_machine_function_pass_t = decltype(std::declval<PassT &>().run(
159 std::declval<MachineFunction &>(),
160 std::declval<MachineFunctionAnalysisManager &>()));
161
162 // Function object to maintain state while adding codegen IR passes.
163 // TODO: add a Function -> MachineFunction adaptor and merge
164 // AddIRPass/AddMachinePass so we can have a function pipeline that runs both
165 // function passes and machine function passes.
166 class AddIRPass {
167 public:
168 AddIRPass(ModulePassManager &MPM, const DerivedT &PB) : MPM(MPM), PB(PB) {}
170 if (!FPM.isEmpty())
171 MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
172 }
173
174 template <typename PassT>
175 void operator()(PassT &&Pass, StringRef Name = PassT::name()) {
178 "Only module pass and function pass are supported.");
179 bool Required = false;
181 Required = PassT::isRequired();
182 if (!PB.runBeforeAdding(Name) && !Required)
183 return;
184
185 // Add Function Pass
187 FPM.addPass(std::forward<PassT>(Pass));
188 } else {
189 // Add Module Pass
190 if (!FPM.isEmpty()) {
191 MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
192 FPM = FunctionPassManager();
193 }
194
195 MPM.addPass(std::forward<PassT>(Pass));
196 }
197 }
198
199 private:
202 const DerivedT &PB;
203 };
204
205 // Function object to maintain state while adding codegen machine passes.
207 public:
208 AddMachinePass(ModulePassManager &MPM, const DerivedT &PB)
209 : MPM(MPM), PB(PB) {}
211 if (!MFPM.isEmpty()) {
213 FPM.addPass(
216 MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
217 }
218 }
219
220 template <typename PassT>
221 void operator()(PassT &&Pass, bool Force = false,
222 StringRef Name = PassT::name()) {
225 "Only module pass and function pass are supported.");
226
227 if (!Force && !PB.runBeforeAdding(Name))
228 return;
229
230 // Add Function Pass
232 MFPM.addPass(std::forward<PassT>(Pass));
233 } else {
234 // Add Module Pass
235 if (!MFPM.isEmpty()) {
239 }
240
241 MPM.addPass(std::forward<PassT>(Pass));
242 }
243
244 for (auto &C : PB.AfterCallbacks)
245 C(Name, MFPM);
246 }
247
248 private:
251 const DerivedT &PB;
252 };
253
254 TargetMachineT &TM;
257
258 template <typename TMC> TMC &getTM() const { return static_cast<TMC &>(TM); }
259 CodeGenOptLevel getOptLevel() const { return TM.getOptLevel(); }
260
261 /// Check whether or not GlobalISel should abort on error.
262 /// When this is disabled, GlobalISel will fall back on SDISel instead of
263 /// erroring out.
265 return TM.Options.GlobalISelAbort == GlobalISelAbortMode::Enable;
266 }
267
268 /// Check whether or not a diagnostic should be emitted when GlobalISel
269 /// uses the fallback path. In other words, it will emit a diagnostic
270 /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
272 return TM.Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag;
273 }
274
275 /// addInstSelector - This method should install an instruction selector pass,
276 /// which converts from LLVM code to machine instructions.
278 return make_error<StringError>("addInstSelector is not overridden",
280 }
281
282 /// Target can override this to add GlobalMergePass before all IR passes.
284
285 /// Add passes that optimize instruction level parallelism for out-of-order
286 /// targets. These passes are run while the machine code is still in SSA
287 /// form, so they can use MachineTraceMetrics to control their heuristics.
288 ///
289 /// All passes added here should preserve the MachineDominatorTree,
290 /// MachineLoopInfo, and MachineTraceMetrics analyses.
291 void addILPOpts(AddMachinePass &) const {}
292
293 /// This method may be implemented by targets that want to run passes
294 /// immediately before register allocation.
296
297 /// addPreRewrite - Add passes to the optimized register allocation pipeline
298 /// after register allocation is complete, but before virtual registers are
299 /// rewritten to physical registers.
300 ///
301 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
302 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
303 /// When these passes run, VirtRegMap contains legal physreg assignments for
304 /// all virtual registers.
305 ///
306 /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
307 /// be honored. This is also not generally used for the fast variant,
308 /// where the allocation and rewriting are done in one pass.
310
311 /// Add passes to be run immediately after virtual registers are rewritten
312 /// to physical registers.
314
315 /// This method may be implemented by targets that want to run passes after
316 /// register allocation pass pipeline but before prolog-epilog insertion.
318
319 /// This method may be implemented by targets that want to run passes after
320 /// prolog-epilog insertion and before the second instruction scheduling pass.
322
323 /// This pass may be implemented by targets that want to run passes
324 /// immediately before machine code is emitted.
326
327 /// Targets may add passes immediately before machine code is emitted in this
328 /// callback. This is called even later than `addPreEmitPass`.
329 // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
330 // position and remove the `2` suffix here as this callback is what
331 // `addPreEmitPass` *should* be but in reality isn't.
333
334 /// {{@ For GlobalISel
335 ///
336
337 /// addPreISel - This method should add any "last minute" LLVM->LLVM
338 /// passes (which are run just before instruction selector).
339 void addPreISel(AddIRPass &) const {
340 llvm_unreachable("addPreISel is not overridden");
341 }
342
343 /// This method should install an IR translator pass, which converts from
344 /// LLVM code to machine instructions with possibly generic opcodes.
346 return make_error<StringError>("addIRTranslator is not overridden",
348 }
349
350 /// This method may be implemented by targets that want to run passes
351 /// immediately before legalization.
353
354 /// This method should install a legalize pass, which converts the instruction
355 /// sequence into one that can be selected by the target.
357 return make_error<StringError>("addLegalizeMachineIR is not overridden",
359 }
360
361 /// This method may be implemented by targets that want to run passes
362 /// immediately before the register bank selection.
364
365 /// This method should install a register bank selector pass, which
366 /// assigns register banks to virtual registers without a register
367 /// class or register banks.
369 return make_error<StringError>("addRegBankSelect is not overridden",
371 }
372
373 /// This method may be implemented by targets that want to run passes
374 /// immediately before the (global) instruction selection.
376
377 /// This method should install a (global) instruction selector pass, which
378 /// converts possibly generic instructions to fully target-specific
379 /// instructions, thereby constraining all generic virtual registers to
380 /// register classes.
382 return make_error<StringError>(
383 "addGlobalInstructionSelect is not overridden",
385 }
386 /// @}}
387
388 /// High level function that adds all passes necessary to go from llvm IR
389 /// representation to the MI representation.
390 /// Adds IR based lowering and target specific optimization passes and finally
391 /// the core instruction selection passes.
392 void addISelPasses(AddIRPass &) const;
393
394 /// Add the actual instruction selection passes. This does not include
395 /// preparation passes on IR.
396 Error addCoreISelPasses(AddMachinePass &) const;
397
398 /// Add the complete, standard set of LLVM CodeGen passes.
399 /// Fully developed targets will not generally override this.
400 Error addMachinePasses(AddMachinePass &) const;
401
402 /// Add passes to lower exception handling for the code generator.
403 void addPassesToHandleExceptions(AddIRPass &) const;
404
405 /// Add common target configurable passes that perform LLVM IR to IR
406 /// transforms following machine independent optimization.
407 void addIRPasses(AddIRPass &) const;
408
409 /// Add pass to prepare the LLVM IR for code generation. This should be done
410 /// before exception handling preparation passes.
411 void addCodeGenPrepare(AddIRPass &) const;
412
413 /// Add common passes that perform LLVM IR to IR transforms in preparation for
414 /// instruction selection.
415 void addISelPrepare(AddIRPass &) const;
416
417 /// Methods with trivial inline returns are convenient points in the common
418 /// codegen pass pipeline where targets may insert passes. Methods with
419 /// out-of-line standard implementations are major CodeGen stages called by
420 /// addMachinePasses. Some targets may override major stages when inserting
421 /// passes is insufficient, but maintaining overriden stages is more work.
422 ///
423
424 /// addMachineSSAOptimization - Add standard passes that optimize machine
425 /// instructions in SSA form.
426 void addMachineSSAOptimization(AddMachinePass &) const;
427
428 /// addFastRegAlloc - Add the minimum set of target-independent passes that
429 /// are required for fast register allocation.
430 Error addFastRegAlloc(AddMachinePass &) const;
431
432 /// addOptimizedRegAlloc - Add passes related to register allocation.
433 /// LLVMTargetMachine provides standard regalloc passes for most targets.
434 void addOptimizedRegAlloc(AddMachinePass &) const;
435
436 /// Add passes that optimize machine instructions after register allocation.
437 void addMachineLateOptimization(AddMachinePass &) const;
438
439 /// addGCPasses - Add late codegen passes that analyze code for garbage
440 /// collection. This should return true if GC info should be printed after
441 /// these passes.
443
444 /// Add standard basic block placement passes.
445 void addBlockPlacement(AddMachinePass &) const;
446
448 std::function<Expected<std::unique_ptr<MCStreamer>>(MCContext &)>;
450 llvm_unreachable("addAsmPrinter is not overridden");
451 }
452
453 /// Utilities for targets to add passes to the pass manager.
454 ///
455
456 /// createTargetRegisterAllocator - Create the register allocator pass for
457 /// this target at the current optimization level.
458 void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const;
459
460 /// addMachinePasses helper to create the target-selected or overriden
461 /// regalloc pass.
462 void addRegAllocPass(AddMachinePass &, bool Optimized) const;
463
464 /// Add core register alloator passes which do the actual register assignment
465 /// and rewriting. \returns true if any passes were added.
466 Error addRegAssignmentFast(AddMachinePass &) const;
467 Error addRegAssignmentOptimized(AddMachinePass &) const;
468
469 /// Allow the target to disable a specific pass by default.
470 /// Backend can declare unwanted passes in constructor.
471 template <typename... PassTs> void disablePass() {
472 BeforeCallbacks.emplace_back(
473 [](StringRef Name) { return ((Name != PassTs::name()) && ...); });
474 }
475
476 /// Insert InsertedPass pass after TargetPass pass.
477 /// Only machine function passes are supported.
478 template <typename TargetPassT, typename InsertedPassT>
479 void insertPass(InsertedPassT &&Pass) {
480 AfterCallbacks.emplace_back(
481 [&](StringRef Name, MachineFunctionPassManager &MFPM) mutable {
482 if (Name == TargetPassT::name())
483 MFPM.addPass(std::forward<InsertedPassT>(Pass));
484 });
485 }
486
487private:
488 DerivedT &derived() { return static_cast<DerivedT &>(*this); }
489 const DerivedT &derived() const {
490 return static_cast<const DerivedT &>(*this);
491 }
492
493 bool runBeforeAdding(StringRef Name) const {
494 bool ShouldAdd = true;
495 for (auto &C : BeforeCallbacks)
496 ShouldAdd &= C(Name);
497 return ShouldAdd;
498 }
499
500 void setStartStopPasses(const TargetPassConfig::StartStopInfo &Info) const;
501
502 Error verifyStartStop(const TargetPassConfig::StartStopInfo &Info) const;
503
504 mutable SmallVector<llvm::unique_function<bool(StringRef)>, 4>
505 BeforeCallbacks;
506 mutable SmallVector<
508 AfterCallbacks;
509
510 /// Helper variable for `-start-before/-start-after/-stop-before/-stop-after`
511 mutable bool Started = true;
512 mutable bool Stopped = true;
513};
514
515template <typename Derived, typename TargetMachineT>
518 CodeGenFileType FileType) const {
519 auto StartStopInfo = TargetPassConfig::getStartStopInfo(*PIC);
520 if (!StartStopInfo)
521 return StartStopInfo.takeError();
522 setStartStopPasses(*StartStopInfo);
523
525 bool PrintMIR = !PrintAsm && FileType != CodeGenFileType::Null;
526
527 {
528 AddIRPass addIRPass(MPM, derived());
532 addISelPasses(addIRPass);
533 }
534
535 AddMachinePass addPass(MPM, derived());
536
537 if (PrintMIR)
538 addPass(PrintMIRPreparePass(Out), /*Force=*/true);
539
540 if (auto Err = addCoreISelPasses(addPass))
541 return std::move(Err);
542
543 if (auto Err = derived().addMachinePasses(addPass))
544 return std::move(Err);
545
546 if (PrintAsm) {
547 derived().addAsmPrinter(
548 addPass, [this, &Out, DwoOut, FileType](MCContext &Ctx) {
549 return this->TM.createMCStreamer(Out, DwoOut, FileType, Ctx);
550 });
551 }
552
553 if (PrintMIR)
554 addPass(PrintMIRPass(Out), /*Force=*/true);
555
556 return verifyStartStop(*StartStopInfo);
557}
558
559template <typename Derived, typename TargetMachineT>
562 if (!Info.StartPass.empty()) {
563 Started = false;
564 BeforeCallbacks.emplace_back([this, &Info, AfterFlag = Info.StartAfter,
565 Count = 0u](StringRef ClassName) mutable {
566 if (Count == Info.StartInstanceNum) {
567 if (AfterFlag) {
568 AfterFlag = false;
569 Started = true;
570 }
571 return Started;
572 }
573
574 auto PassName = PIC->getPassNameForClassName(ClassName);
575 if (Info.StartPass == PassName && ++Count == Info.StartInstanceNum)
576 Started = !Info.StartAfter;
577
578 return Started;
579 });
580 }
581
582 if (!Info.StopPass.empty()) {
583 Stopped = false;
584 BeforeCallbacks.emplace_back([this, &Info, AfterFlag = Info.StopAfter,
585 Count = 0u](StringRef ClassName) mutable {
586 if (Count == Info.StopInstanceNum) {
587 if (AfterFlag) {
588 AfterFlag = false;
589 Stopped = true;
590 }
591 return !Stopped;
592 }
593
594 auto PassName = PIC->getPassNameForClassName(ClassName);
595 if (Info.StopPass == PassName && ++Count == Info.StopInstanceNum)
596 Stopped = !Info.StopAfter;
597 return !Stopped;
598 });
599 }
600}
601
602template <typename Derived, typename TargetMachineT>
603Error CodeGenPassBuilder<Derived, TargetMachineT>::verifyStartStop(
604 const TargetPassConfig::StartStopInfo &Info) const {
605 if (Started && Stopped)
606 return Error::success();
607
608 if (!Started)
609 return make_error<StringError>(
610 "Can't find start pass \"" +
611 PIC->getPassNameForClassName(Info.StartPass) + "\".",
612 std::make_error_code(std::errc::invalid_argument));
613 if (!Stopped)
614 return make_error<StringError>(
615 "Can't find stop pass \"" +
616 PIC->getPassNameForClassName(Info.StopPass) + "\".",
617 std::make_error_code(std::errc::invalid_argument));
618 return Error::success();
619}
620
621template <typename Derived, typename TargetMachineT>
623 AddIRPass &addPass) const {
624 derived().addGlobalMergePass(addPass);
625 if (TM.useEmulatedTLS())
626 addPass(LowerEmuTLSPass());
627
629
630 derived().addIRPasses(addPass);
631 derived().addCodeGenPrepare(addPass);
632 addPassesToHandleExceptions(addPass);
633 derived().addISelPrepare(addPass);
634}
635
636/// Add common target configurable passes that perform LLVM IR to IR transforms
637/// following machine independent optimization.
638template <typename Derived, typename TargetMachineT>
640 AddIRPass &addPass) const {
641 // Before running any passes, run the verifier to determine if the input
642 // coming from the front-end and/or optimizer is valid.
643 if (!Opt.DisableVerify)
644 addPass(VerifierPass());
645
646 // Run loop strength reduction before anything else.
647 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) {
649 /*UseMemorySSA=*/true));
650 // FIXME: use -stop-after so we could remove PrintLSR
651 if (Opt.PrintLSR)
652 addPass(PrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
653 }
654
655 if (getOptLevel() != CodeGenOptLevel::None) {
656 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
657 // loads and compares. ExpandMemCmpPass then tries to expand those calls
658 // into optimally-sized loads and compares. The transforms are enabled by a
659 // target lowering hook.
660 if (!Opt.DisableMergeICmps)
661 addPass(MergeICmpsPass());
662 addPass(ExpandMemCmpPass(&TM));
663 }
664
665 // Run GC lowering passes for builtin collectors
666 // TODO: add a pass insertion point here
667 addPass(GCLoweringPass());
668 addPass(ShadowStackGCLoweringPass());
670
671 // Make sure that no unreachable blocks are instruction selected.
672 addPass(UnreachableBlockElimPass());
673
674 // Prepare expensive constants for SelectionDAG.
675 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableConstantHoisting)
676 addPass(ConstantHoistingPass());
677
678 // Replace calls to LLVM intrinsics (e.g., exp, log) operating on vector
679 // operands with calls to the corresponding functions in a vector library.
680 if (getOptLevel() != CodeGenOptLevel::None)
681 addPass(ReplaceWithVeclib());
682
683 if (getOptLevel() != CodeGenOptLevel::None &&
686
687 // Instrument function entry and exit, e.g. with calls to mcount().
688 addPass(EntryExitInstrumenterPass(/*PostInlining=*/true));
689
690 // Add scalarization of target's unsupported masked memory intrinsics pass.
691 // the unsupported intrinsic will be replaced with a chain of basic blocks,
692 // that stores/loads element one-by-one if the appropriate mask bit is set.
694
695 // Expand reduction intrinsics into shuffle sequences if the target wants to.
696 addPass(ExpandReductionsPass());
697
698 // Convert conditional moves to conditional jumps when profitable.
699 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableSelectOptimize)
700 addPass(SelectOptimizePass(&TM));
701}
702
703/// Turn exception handling constructs into something the code generators can
704/// handle.
705template <typename Derived, typename TargetMachineT>
707 AddIRPass &addPass) const {
708 const MCAsmInfo *MCAI = TM.getMCAsmInfo();
709 assert(MCAI && "No MCAsmInfo");
710 switch (MCAI->getExceptionHandlingType()) {
711 case ExceptionHandling::SjLj:
712 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
713 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
714 // catch info can get misplaced when a selector ends up more than one block
715 // removed from the parent invoke(s). This could happen when a landing
716 // pad is shared by multiple invokes and is also a target of a normal
717 // edge from elsewhere.
718 addPass(SjLjEHPreparePass(&TM));
719 [[fallthrough]];
720 case ExceptionHandling::DwarfCFI:
721 case ExceptionHandling::ARM:
722 case ExceptionHandling::AIX:
723 case ExceptionHandling::ZOS:
724 addPass(DwarfEHPreparePass(&TM));
725 break;
726 case ExceptionHandling::WinEH:
727 // We support using both GCC-style and MSVC-style exceptions on Windows, so
728 // add both preparation passes. Each pass will only actually run if it
729 // recognizes the personality function.
730 addPass(WinEHPreparePass());
731 addPass(DwarfEHPreparePass(&TM));
732 break;
733 case ExceptionHandling::Wasm:
734 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
735 // on catchpads and cleanuppads because it does not outline them into
736 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
737 // should remove PHIs there.
738 addPass(WinEHPreparePass(/*DemoteCatchSwitchPHIOnly=*/false));
739 addPass(WasmEHPreparePass());
740 break;
741 case ExceptionHandling::None:
742 addPass(LowerInvokePass());
743
744 // The lower invoke pass may create unreachable code. Remove it.
745 addPass(UnreachableBlockElimPass());
746 break;
747 }
748}
749
750/// Add pass to prepare the LLVM IR for code generation. This should be done
751/// before exception handling preparation passes.
752template <typename Derived, typename TargetMachineT>
754 AddIRPass &addPass) const {
755 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableCGP)
756 addPass(CodeGenPreparePass(&TM));
757 // TODO: Default ctor'd RewriteSymbolPass is no-op.
758 // addPass(RewriteSymbolPass());
759}
760
761/// Add common passes that perform LLVM IR to IR transforms in preparation for
762/// instruction selection.
763template <typename Derived, typename TargetMachineT>
765 AddIRPass &addPass) const {
766 derived().addPreISel(addPass);
767
768 addPass(CallBrPreparePass());
769 // Add both the safe stack and the stack protection passes: each of them will
770 // only protect functions that have corresponding attributes.
771 addPass(SafeStackPass(&TM));
772 addPass(StackProtectorPass(&TM));
773
774 if (Opt.PrintISelInput)
775 addPass(PrintFunctionPass(dbgs(),
776 "\n\n*** Final LLVM Code input to ISel ***\n"));
777
778 // All passes which modify the LLVM IR are now complete; run the verifier
779 // to ensure that the IR is valid.
780 if (!Opt.DisableVerify)
781 addPass(VerifierPass());
782}
783
784template <typename Derived, typename TargetMachineT>
786 AddMachinePass &addPass) const {
787 // Enable FastISel with -fast-isel, but allow that to be overridden.
788 TM.setO0WantsFastISel(Opt.EnableFastISelOption.value_or(true));
789
790 // Determine an instruction selector.
791 enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
792 SelectorType Selector;
793
794 if (Opt.EnableFastISelOption && *Opt.EnableFastISelOption == true)
795 Selector = SelectorType::FastISel;
796 else if ((Opt.EnableGlobalISelOption &&
797 *Opt.EnableGlobalISelOption == true) ||
798 (TM.Options.EnableGlobalISel &&
800 *Opt.EnableGlobalISelOption == false)))
801 Selector = SelectorType::GlobalISel;
802 else if (TM.getOptLevel() == CodeGenOptLevel::None && TM.getO0WantsFastISel())
803 Selector = SelectorType::FastISel;
804 else
805 Selector = SelectorType::SelectionDAG;
806
807 // Set consistently TM.Options.EnableFastISel and EnableGlobalISel.
808 if (Selector == SelectorType::FastISel) {
809 TM.setFastISel(true);
810 TM.setGlobalISel(false);
811 } else if (Selector == SelectorType::GlobalISel) {
812 TM.setFastISel(false);
813 TM.setGlobalISel(true);
814 }
815
816 // Add instruction selector passes.
817 if (Selector == SelectorType::GlobalISel) {
818 if (auto Err = derived().addIRTranslator(addPass))
819 return std::move(Err);
820
821 derived().addPreLegalizeMachineIR(addPass);
822
823 if (auto Err = derived().addLegalizeMachineIR(addPass))
824 return std::move(Err);
825
826 // Before running the register bank selector, ask the target if it
827 // wants to run some passes.
828 derived().addPreRegBankSelect(addPass);
829
830 if (auto Err = derived().addRegBankSelect(addPass))
831 return std::move(Err);
832
833 derived().addPreGlobalInstructionSelect(addPass);
834
835 if (auto Err = derived().addGlobalInstructionSelect(addPass))
836 return std::move(Err);
837
838 // Pass to reset the MachineFunction if the ISel failed.
839 addPass(ResetMachineFunctionPass(reportDiagnosticWhenGlobalISelFallback(),
840 isGlobalISelAbortEnabled()));
841
842 // Provide a fallback path when we do not want to abort on
843 // not-yet-supported input.
844 if (!isGlobalISelAbortEnabled())
845 if (auto Err = derived().addInstSelector(addPass))
846 return std::move(Err);
847
848 } else if (auto Err = derived().addInstSelector(addPass))
849 return std::move(Err);
850
851 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
852 // FinalizeISel.
853 addPass(FinalizeISelPass());
854
855 // // Print the instruction selected machine code...
856 // printAndVerify("After Instruction Selection");
857
858 return Error::success();
859}
860
861/// Add the complete set of target-independent postISel code generator passes.
862///
863/// This can be read as the standard order of major LLVM CodeGen stages. Stages
864/// with nontrivial configuration or multiple passes are broken out below in
865/// add%Stage routines.
866///
867/// Any CodeGenPassBuilder<Derived, TargetMachine>::addXX routine may be
868/// overriden by the Target. The addPre/Post methods with empty header
869/// implementations allow injecting target-specific fixups just before or after
870/// major stages. Additionally, targets have the flexibility to change pass
871/// order within a stage by overriding default implementation of add%Stage
872/// routines below. Each technique has maintainability tradeoffs because
873/// alternate pass orders are not well supported. addPre/Post works better if
874/// the target pass is easily tied to a common pass. But if it has subtle
875/// dependencies on multiple passes, the target should override the stage
876/// instead.
877template <typename Derived, typename TargetMachineT>
879 AddMachinePass &addPass) const {
880 // Add passes that optimize machine instructions in SSA form.
881 if (getOptLevel() != CodeGenOptLevel::None) {
882 derived().addMachineSSAOptimization(addPass);
883 } else {
884 // If the target requests it, assign local variables to stack slots relative
885 // to one another and simplify frame index references where possible.
887 }
888
889 if (TM.Options.EnableIPRA)
890 addPass(RegUsageInfoPropagationPass());
891
892 // Run pre-ra passes.
893 derived().addPreRegAlloc(addPass);
894
895 // Run register allocation and passes that are tightly coupled with it,
896 // including phi elimination and scheduling.
897 if (*Opt.OptimizeRegAlloc) {
898 derived().addOptimizedRegAlloc(addPass);
899 } else {
900 if (auto Err = derived().addFastRegAlloc(addPass))
901 return Err;
902 }
903
904 // Run post-ra passes.
905 derived().addPostRegAlloc(addPass);
906
907 addPass(RemoveRedundantDebugValuesPass());
908
909 // Insert prolog/epilog code. Eliminate abstract frame index references...
910 if (getOptLevel() != CodeGenOptLevel::None) {
911 addPass(PostRAMachineSinkingPass());
912 addPass(ShrinkWrapPass());
913 }
914
915 addPass(PrologEpilogInserterPass());
916
917 /// Add passes that optimize machine instructions after register allocation.
918 if (getOptLevel() != CodeGenOptLevel::None)
919 derived().addMachineLateOptimization(addPass);
920
921 // Expand pseudo instructions before second scheduling pass.
922 addPass(ExpandPostRAPseudosPass());
923
924 // Run pre-sched2 passes.
925 derived().addPreSched2(addPass);
926
928 addPass(ImplicitNullChecksPass());
929
930 // Second pass scheduler.
931 // Let Target optionally insert this pass by itself at some other
932 // point.
933 if (getOptLevel() != CodeGenOptLevel::None &&
934 !TM.targetSchedulesPostRAScheduling()) {
935 if (Opt.MISchedPostRA)
936 addPass(PostMachineSchedulerPass());
937 else
938 addPass(PostRASchedulerPass());
939 }
940
941 // GC
942 derived().addGCPasses(addPass);
943
944 // Basic block placement.
945 if (getOptLevel() != CodeGenOptLevel::None)
946 derived().addBlockPlacement(addPass);
947
948 // Insert before XRay Instrumentation.
949 addPass(FEntryInserterPass());
950
951 addPass(XRayInstrumentationPass());
952 addPass(PatchableFunctionPass());
953
954 derived().addPreEmitPass(addPass);
955
956 if (TM.Options.EnableIPRA)
957 // Collect register usage information and produce a register mask of
958 // clobbered registers, to be used to optimize call sites.
959 addPass(RegUsageInfoCollectorPass());
960
961 addPass(FuncletLayoutPass());
962
963 addPass(StackMapLivenessPass());
964 addPass(LiveDebugValuesPass());
965 addPass(MachineSanitizerBinaryMetadata());
966
967 if (TM.Options.EnableMachineOutliner &&
968 getOptLevel() != CodeGenOptLevel::None &&
969 Opt.EnableMachineOutliner != RunOutliner::NeverOutline) {
970 bool RunOnAllFunctions =
971 (Opt.EnableMachineOutliner == RunOutliner::AlwaysOutline);
972 bool AddOutliner = RunOnAllFunctions || TM.Options.SupportsDefaultOutlining;
973 if (AddOutliner)
974 addPass(MachineOutlinerPass(RunOnAllFunctions));
975 }
976
977 // Add passes that directly emit MI after all other MI passes.
978 derived().addPreEmitPass2(addPass);
979
980 return Error::success();
981}
982
983/// Add passes that optimize machine instructions in SSA form.
984template <typename Derived, typename TargetMachineT>
986 AddMachinePass &addPass) const {
987 // Pre-ra tail duplication.
988 addPass(EarlyTailDuplicatePass());
989
990 // Optimize PHIs before DCE: removing dead PHI cycles may make more
991 // instructions dead.
992 addPass(OptimizePHIsPass());
993
994 // This pass merges large allocas. StackSlotColoring is a different pass
995 // which merges spill slots.
996 addPass(StackColoringPass());
997
998 // If the target requests it, assign local variables to stack slots relative
999 // to one another and simplify frame index references where possible.
1001
1002 // With optimization, dead code should already be eliminated. However
1003 // there is one known exception: lowered code for arguments that are only
1004 // used by tail calls, where the tail calls reuse the incoming stack
1005 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1007
1008 // Allow targets to insert passes that improve instruction level parallelism,
1009 // like if-conversion. Such passes will typically need dominator trees and
1010 // loop info, just like LICM and CSE below.
1011 derived().addILPOpts(addPass);
1012
1013 addPass(EarlyMachineLICMPass());
1014 addPass(MachineCSEPass());
1015
1016 addPass(MachineSinkingPass());
1017
1018 addPass(PeepholeOptimizerPass());
1019 // Clean-up the dead code that may have been generated by peephole
1020 // rewriting.
1022}
1023
1024//===---------------------------------------------------------------------===//
1025/// Register Allocation Pass Configuration
1026//===---------------------------------------------------------------------===//
1027
1028/// Instantiate the default register allocator pass for this target for either
1029/// the optimized or unoptimized allocation path. This will be added to the pass
1030/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1031/// in the optimized case.
1032///
1033/// A target that uses the standard regalloc pass order for fast or optimized
1034/// allocation may still override this for per-target regalloc
1035/// selection. But -regalloc=... always takes precedence.
1036template <typename Derived, typename TargetMachineT>
1038 AddMachinePass &addPass, bool Optimized) const {
1039 if (Optimized)
1040 addPass(RAGreedyPass());
1041 else
1042 addPass(RegAllocFastPass());
1043}
1044
1045/// Find and instantiate the register allocation pass requested by this target
1046/// at the current optimization level. Different register allocators are
1047/// defined as separate passes because they may require different analysis.
1048template <typename Derived, typename TargetMachineT>
1050 AddMachinePass &addPass, bool Optimized) const {
1051 // TODO: Parse Opt.RegAlloc to add register allocator.
1052}
1053
1054template <typename Derived, typename TargetMachineT>
1056 AddMachinePass &addPass) const {
1057 // TODO: Ensure allocator is default or fast.
1058 addRegAllocPass(addPass, false);
1059 return Error::success();
1060}
1061
1062template <typename Derived, typename TargetMachineT>
1064 AddMachinePass &addPass) const {
1065 // Add the selected register allocation pass.
1066 addRegAllocPass(addPass, true);
1067
1068 // Allow targets to change the register assignments before rewriting.
1069 derived().addPreRewrite(addPass);
1070
1071 // Finally rewrite virtual registers.
1072 addPass(VirtRegRewriterPass());
1073 // Perform stack slot coloring and post-ra machine LICM.
1074 //
1075 // FIXME: Re-enable coloring with register when it's capable of adding
1076 // kill markers.
1077 addPass(StackSlotColoringPass());
1078
1079 return Error::success();
1080}
1081
1082/// Add the minimum set of target-independent passes that are required for
1083/// register allocation. No coalescing or scheduling.
1084template <typename Derived, typename TargetMachineT>
1086 AddMachinePass &addPass) const {
1087 addPass(PHIEliminationPass());
1088 addPass(TwoAddressInstructionPass());
1089 return derived().addRegAssignmentFast(addPass);
1090}
1091
1092/// Add standard target-independent passes that are tightly coupled with
1093/// optimized register allocation, including coalescing, machine instruction
1094/// scheduling, and register allocation itself.
1095template <typename Derived, typename TargetMachineT>
1097 AddMachinePass &addPass) const {
1098 addPass(DetectDeadLanesPass());
1099
1100 addPass(InitUndefPass());
1101
1102 addPass(ProcessImplicitDefsPass());
1103
1104 // Edge splitting is smarter with machine loop info.
1105 addPass(PHIEliminationPass());
1106
1107 // Eventually, we want to run LiveIntervals before PHI elimination.
1108 if (Opt.EarlyLiveIntervals)
1109 addPass(LiveIntervalsPass());
1110
1111 addPass(TwoAddressInstructionPass());
1112 addPass(RegisterCoalescerPass());
1113
1114 // The machine scheduler may accidentally create disconnected components
1115 // when moving subregister definitions around, avoid this by splitting them to
1116 // separate vregs before. Splitting can also improve reg. allocation quality.
1117 addPass(RenameIndependentSubregsPass());
1118
1119 // PreRA instruction scheduling.
1120 addPass(MachineSchedulerPass());
1121
1122 if (derived().addRegAssignmentOptimized(addPass)) {
1123 // Allow targets to expand pseudo instructions depending on the choice of
1124 // registers before MachineCopyPropagation.
1125 derived().addPostRewrite(addPass);
1126
1127 // Copy propagate to forward register uses and try to eliminate COPYs that
1128 // were not coalesced.
1129 addPass(MachineCopyPropagationPass());
1130
1131 // Run post-ra machine LICM to hoist reloads / remats.
1132 //
1133 // FIXME: can this move into MachineLateOptimization?
1134 addPass(MachineLICMPass());
1135 }
1136}
1137
1138//===---------------------------------------------------------------------===//
1139/// Post RegAlloc Pass Configuration
1140//===---------------------------------------------------------------------===//
1141
1142/// Add passes that optimize machine instructions after register allocation.
1143template <typename Derived, typename TargetMachineT>
1145 AddMachinePass &addPass) const {
1146 // Branch folding must be run after regalloc and prolog/epilog insertion.
1147 addPass(BranchFolderPass());
1148
1149 // Tail duplication.
1150 // Note that duplicating tail just increases code size and degrades
1151 // performance for targets that require Structured Control Flow.
1152 // In addition it can also make CFG irreducible. Thus we disable it.
1153 if (!TM.requiresStructuredCFG())
1154 addPass(TailDuplicatePass());
1155
1156 // Cleanup of redundant (identical) address/immediate loads.
1157 addPass(MachineLateInstrsCleanupPass());
1158
1159 // Copy propagation.
1160 addPass(MachineCopyPropagationPass());
1161}
1162
1163/// Add standard basic block placement passes.
1164template <typename Derived, typename TargetMachineT>
1166 AddMachinePass &addPass) const {
1167 addPass(MachineBlockPlacementPass());
1168 // Run a separate pass to collect block placement statistics.
1170 addPass(MachineBlockPlacementStatsPass());
1171}
1172
1173} // namespace llvm
1174
1175#endif // LLVM_PASSES_CODEGENPASSBUILDER_H
This is the interface for LLVM's primary stateless and local alias analysis.
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Defines an IR pass for CodeGen Prepare.
std::string Name
This file defines passes to print out IR in various granularities.
This file contains the declaration of the InterleavedAccessPass class, its corresponding pass name is...
This header provides classes for managing a pipeline of passes over loops in LLVM IR.
The header file for the LowerConstantIntrinsics pass as used by the new pass manager.
if(VerifyEach)
ModulePassManager MPM
const char LLVMTargetMachineRef TM
PassInstrumentationCallbacks PIC
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
This header defines various interfaces for pass management in LLVM.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This is the interface for a metadata-based scoped no-alias analysis.
This file contains the declaration of the SelectOptimizePass class, its corresponding pass name is se...
This file defines the SmallVector class.
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
This is the interface for a metadata-based TBAA.
static const char PassName[]
AddIRPass(ModulePassManager &MPM, const DerivedT &PB)
void operator()(PassT &&Pass, StringRef Name=PassT::name())
AddMachinePass(ModulePassManager &MPM, const DerivedT &PB)
void operator()(PassT &&Pass, bool Force=false, StringRef Name=PassT::name())
This class provides access to building LLVM's passes.
void addPreRewrite(AddMachinePass &) const
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
void addPostRegAlloc(AddMachinePass &) const
This method may be implemented by targets that want to run passes after register allocation pass pipe...
void insertPass(InsertedPassT &&Pass)
Insert InsertedPass pass after TargetPass pass.
void addPreGlobalInstructionSelect(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before the (global) ins...
Error addRegAssignmentFast(AddMachinePass &) const
Add core register alloator passes which do the actual register assignment and rewriting.
Error addFastRegAlloc(AddMachinePass &) const
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Error addIRTranslator(AddMachinePass &) const
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
void addILPOpts(AddMachinePass &) const
Add passes that optimize instruction level parallelism for out-of-order targets.
void addRegAllocPass(AddMachinePass &, bool Optimized) const
addMachinePasses helper to create the target-selected or overriden regalloc pass.
void addPreSched2(AddMachinePass &) const
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
std::function< Expected< std::unique_ptr< MCStreamer > >(MCContext &)> CreateMCStreamer
Error addRegBankSelect(AddMachinePass &) const
This method should install a register bank selector pass, which assigns register banks to virtual reg...
decltype(std::declval< PassT & >().isRequired()) has_required_t
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
void addPreRegAlloc(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before register allocat...
void addGCPasses(AddMachinePass &) const
addGCPasses - Add late codegen passes that analyze code for garbage collection.
Error buildPipeline(ModulePassManager &MPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType) const
void addGlobalMergePass(AddIRPass &) const
Target can override this to add GlobalMergePass before all IR passes.
Error addLegalizeMachineIR(AddMachinePass &) const
This method should install a legalize pass, which converts the instruction sequence into one that can...
Error addCoreISelPasses(AddMachinePass &) const
Add the actual instruction selection passes.
void addOptimizedRegAlloc(AddMachinePass &) const
addOptimizedRegAlloc - Add passes related to register allocation.
void addISelPasses(AddIRPass &) const
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
PassInstrumentationCallbacks * PIC
void addMachineSSAOptimization(AddMachinePass &) const
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
decltype(std::declval< PassT & >().run(std::declval< Module & >(), std::declval< ModuleAnalysisManager & >())) is_module_pass_t
CodeGenPassBuilder(TargetMachineT &TM, const CGPassBuilderOption &Opts, PassInstrumentationCallbacks *PIC)
Error addRegAssignmentOptimized(AddMachinePass &) const
void addCodeGenPrepare(AddIRPass &) const
Add pass to prepare the LLVM IR for code generation.
Error addMachinePasses(AddMachinePass &) const
Add the complete, standard set of LLVM CodeGen passes.
void addISelPrepare(AddIRPass &) const
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
void disablePass()
Allow the target to disable a specific pass by default.
void addBlockPlacement(AddMachinePass &) const
Add standard basic block placement passes.
Error addInstSelector(AddMachinePass &) const
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const
Utilities for targets to add passes to the pass manager.
void addPreEmitPass2(AddMachinePass &) const
Targets may add passes immediately before machine code is emitted in this callback.
void addPostRewrite(AddMachinePass &) const
Add passes to be run immediately after virtual registers are rewritten to physical registers.
void addPreRegBankSelect(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before the register ban...
void addPreEmitPass(AddMachinePass &) const
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Error addGlobalInstructionSelect(AddMachinePass &) const
This method should install a (global) instruction selector pass, which converts possibly generic inst...
void addMachineLateOptimization(AddMachinePass &) const
Add passes that optimize machine instructions after register allocation.
void addIRPasses(AddIRPass &) const
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
decltype(std::declval< PassT & >().run(std::declval< Function & >(), std::declval< FunctionAnalysisManager & >())) is_function_pass_t
decltype(std::declval< PassT & >().run(std::declval< MachineFunction & >(), std::declval< MachineFunctionAnalysisManager & >())) is_machine_function_pass_t
void addPreLegalizeMachineIR(AddMachinePass &) const
This method may be implemented by targets that want to run passes immediately before legalization.
CodeGenOptLevel getOptLevel() const
void addPassesToHandleExceptions(AddIRPass &) const
Add passes to lower exception handling for the code generator.
PassInstrumentationCallbacks * getPassInstrumentationCallbacks() const
bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
void addPreISel(AddIRPass &) const
{{@ For GlobalISel
void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
LowerIntrinsics - This pass rewrites calls to the llvm.gcread or llvm.gcwrite intrinsics,...
Definition: GCMetadata.h:195
Performs Loop Strength Reduce Pass.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:780
Context object for machine code objects.
Definition: MCContext.h:81
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
StringRef getPassNameForClassName(StringRef ClassName)
Get the pass name for a given pass class name.
LLVM_ATTRIBUTE_MINSIZE void addPass(PassT &&Pass)
Definition: PassManager.h:249
bool isEmpty() const
Returns if the pass manager contains any passes.
Definition: PassManager.h:269
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
Pass (for the new pass manager) for printing a Function as LLVM's text IR assembly.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:227
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
static Expected< StartStopInfo > getStartStopInfo(PassInstrumentationCallbacks &PIC)
Returns pass name in -stop-before or -stop-after NOTE: New pass manager migration only.
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
Create a verifier pass.
Definition: Verifier.h:132
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:445
unique_function is a type-erasing functor similar to std::function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
PassManager< Function > FunctionPassManager
Convenience typedef for a pass manager over functions.
Definition: PassManager.h:288
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:916
std::error_code inconvertibleErrorCode()
The value returned by this function can be returned from convertToErrorCode for Error values where no...
Definition: Error.cpp:90
PassManager< MachineFunction > MachineFunctionPassManager
Convenience typedef for a pass manager over functions.
typename detail::detector< void, Op, Args... >::value_t is_detected
Detects if a given trait holds for some set of arguments 'Args'.
Definition: STLExtras.h:79
CodeGenFileType
These enums are meant to be passed into addPassesToEmitFile to indicate what type of file to emit,...
Definition: CodeGen.h:83
FunctionToMachineFunctionPassAdaptor createFunctionToMachineFunctionPassAdaptor(MachineFunctionPassT &&Pass)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
Definition: SmallVector.h:1135
std::enable_if_t< is_detected< HasRunOnLoopT, LoopPassT >::value, FunctionToLoopPassAdaptor > createFunctionToLoopPassAdaptor(LoopPassT &&Pass, bool UseMemorySSA=false, bool UseBlockFrequencyInfo=false, bool UseBranchProbabilityInfo=false)
A function to deduce a loop pass type and wrap it in the templated adaptor.
std::optional< bool > EnableGlobalISelOption
std::optional< bool > EnableIPRA
std::optional< bool > OptimizeRegAlloc
std::optional< bool > EnableFastISelOption
std::optional< GlobalISelAbortMode > EnableGlobalISelAbort
A no-op pass template which simply forces a specific analysis result to be invalidated.
Definition: PassManager.h:969
A utility pass template to force an analysis result to be available.
Definition: PassManager.h:942