SchedulerRegistry.h File Reference

#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/Support/CodeGen.h"

Go to the source code of this file.

Classes
class	llvm::RegisterScheduler

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Functions
ScheduleDAGSDNodes *	llvm::createBURRListDAGScheduler (SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
	createBURRListDAGScheduler - This creates a bottom up register usage reduction list scheduler.
ScheduleDAGSDNodes *	llvm::createSourceListDAGScheduler (SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
	createSourceListDAGScheduler - This creates a bottom up list scheduler that schedules nodes in source code order when possible.
ScheduleDAGSDNodes *	llvm::createHybridListDAGScheduler (SelectionDAGISel *IS, CodeGenOptLevel)
	createHybridListDAGScheduler - This creates a bottom up register pressure aware list scheduler that make use of latency information to avoid stalls for long latency instructions in low register pressure mode.
ScheduleDAGSDNodes *	llvm::createILPListDAGScheduler (SelectionDAGISel *IS, CodeGenOptLevel)
	createILPListDAGScheduler - This creates a bottom up register pressure aware list scheduler that tries to increase instruction level parallelism in low register pressure mode.
ScheduleDAGSDNodes *	llvm::createFastDAGScheduler (SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
	createFastDAGScheduler - This creates a "fast" scheduler.
ScheduleDAGSDNodes *	llvm::createVLIWDAGScheduler (SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
	createVLIWDAGScheduler - Scheduler for VLIW targets.
ScheduleDAGSDNodes *	llvm::createDefaultScheduler (SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
	createDefaultScheduler - This creates an instruction scheduler appropriate for the target.
ScheduleDAGSDNodes *	llvm::createDAGLinearizer (SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
	createDAGLinearizer - This creates a "no-scheduling" scheduler which linearize the DAG using topological order.