LLVM 20.0.0git
Classes | Namespaces | Functions
SchedulerRegistry.h File Reference
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/Support/CodeGen.h"

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Classes

class  llvm::RegisterScheduler
 

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 

Functions

ScheduleDAGSDNodesllvm::createBURRListDAGScheduler (SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
 createBURRListDAGScheduler - This creates a bottom up register usage reduction list scheduler.
 
ScheduleDAGSDNodesllvm::createSourceListDAGScheduler (SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
 createSourceListDAGScheduler - This creates a bottom up list scheduler that schedules nodes in source code order when possible.
 
ScheduleDAGSDNodesllvm::createHybridListDAGScheduler (SelectionDAGISel *IS, CodeGenOptLevel)
 createHybridListDAGScheduler - This creates a bottom up register pressure aware list scheduler that make use of latency information to avoid stalls for long latency instructions in low register pressure mode.
 
ScheduleDAGSDNodesllvm::createILPListDAGScheduler (SelectionDAGISel *IS, CodeGenOptLevel)
 createILPListDAGScheduler - This creates a bottom up register pressure aware list scheduler that tries to increase instruction level parallelism in low register pressure mode.
 
ScheduleDAGSDNodesllvm::createFastDAGScheduler (SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
 createFastDAGScheduler - This creates a "fast" scheduler.
 
ScheduleDAGSDNodesllvm::createVLIWDAGScheduler (SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
 createVLIWDAGScheduler - Scheduler for VLIW targets.
 
ScheduleDAGSDNodesllvm::createDefaultScheduler (SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
 createDefaultScheduler - This creates an instruction scheduler appropriate for the target.
 
ScheduleDAGSDNodesllvm::createDAGLinearizer (SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
 createDAGLinearizer - This creates a "no-scheduling" scheduler which linearize the DAG using topological order.