33#define DEBUG_TYPE "pre-RA-sched"
57 std::vector<SUnit*> PendingQueue;
69 ~ScheduleDAGVLIW()
override {
71 delete AvailableQueue;
78 void releaseSuccessors(
SUnit *SU);
79 void scheduleNodeTopDown(
SUnit *SU,
unsigned CurCycle);
80 void listScheduleTopDown();
85void ScheduleDAGVLIW::Schedule() {
87 <<
" '" << BB->getName() <<
"' **********\n");
94 listScheduleTopDown();
105void ScheduleDAGVLIW::releaseSucc(
SUnit *SU,
const SDep &
D) {
106 SUnit *SuccSU =
D.getSUnit();
110 dbgs() <<
"*** Scheduling failed! ***\n";
112 dbgs() <<
" has been released too many times!\n";
116 assert(!
D.isWeak() &&
"unexpected artificial DAG edge");
125 PendingQueue.push_back(SuccSU);
129void ScheduleDAGVLIW::releaseSuccessors(
SUnit *SU) {
133 "The list-td scheduler doesn't yet support physreg dependencies!");
135 releaseSucc(SU, Succ);
142void ScheduleDAGVLIW::scheduleNodeTopDown(
SUnit *SU,
unsigned CurCycle) {
147 assert(CurCycle >= SU->
getDepth() &&
"Node scheduled above its depth!");
150 releaseSuccessors(SU);
157void ScheduleDAGVLIW::listScheduleTopDown() {
158 unsigned CurCycle = 0;
161 releaseSuccessors(&EntrySU);
164 for (
SUnit &SU : SUnits) {
166 if (SU.
Preds.empty()) {
167 AvailableQueue->
push(&SU);
174 std::vector<SUnit*> NotReady;
176 while (!AvailableQueue->
empty() || !PendingQueue.empty()) {
179 for (
unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
180 if (PendingQueue[i]->getDepth() == CurCycle) {
181 AvailableQueue->
push(PendingQueue[i]);
182 PendingQueue[i]->isAvailable =
true;
183 PendingQueue[i] = PendingQueue.back();
184 PendingQueue.pop_back();
188 assert(PendingQueue[i]->getDepth() > CurCycle &&
"Negative latency?");
194 if (AvailableQueue->
empty()) {
201 SUnit *FoundSUnit =
nullptr;
203 bool HasNoopHazards =
false;
204 while (!AvailableQueue->
empty()) {
205 SUnit *CurSUnit = AvailableQueue->
pop();
210 FoundSUnit = CurSUnit;
217 NotReady.push_back(CurSUnit);
221 if (!NotReady.empty()) {
228 scheduleNodeTopDown(FoundSUnit, CurCycle);
235 }
else if (!HasNoopHazards) {
255 VerifyScheduledSequence(
false);
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static RegisterScheduler VLIWScheduler("vliw-td", "VLIW scheduler", createVLIWDAGScheduler)
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isAssignedRegDep() const
Tests if this is a Data dependence that is associated with a register.
Scheduling unit. This is a node in the scheduling DAG.
unsigned short Latency
Node latency.
unsigned getDepth() const
Returns the depth of this node, which is the length of the maximum path up to any node which has no p...
bool isScheduled
True once scheduled.
bool isAvailable
True once available.
SmallVector< SDep, 4 > Succs
All sunit successors.
SmallVector< SDep, 4 > Preds
All sunit predecessors.
void setDepthToAtLeast(unsigned NewDepth)
If NewDepth is greater than this node's depth value, sets it to be the new depth value.
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
virtual void Schedule()=0
Schedule - Order nodes according to selected style, filling in the Sequence member.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
virtual void EmitInstruction(SUnit *)
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
virtual void EmitNoop()
EmitNoop - This callback is invoked when a noop was added to the instruction stream.
virtual void AdvanceCycle()
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
virtual HazardType getHazardType(SUnit *, int Stalls=0)
getHazardType - Return the hazard type of emitting this node.
This interface is used to plug different priorities computation algorithms into the list scheduler.
virtual void releaseState()=0
virtual void scheduledNode(SUnit *)
As each node is scheduled, this method is invoked.
virtual void initNodes(std::vector< SUnit > &SUnits)=0
virtual bool empty() const =0
void push_all(const std::vector< SUnit * > &Nodes)
virtual void push(SUnit *U)=0
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetInstrInfo * getInstrInfo() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Sequence
A sequence of states that a pointer may go through in which an objc_retain and objc_release are actua...
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
CodeGenOptLevel
Code generation optimization level.
ScheduleDAGSDNodes * createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createVLIWDAGScheduler - Scheduler for VLIW targets.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.