31 using namespace Hexagon;
33 #define DEBUG_TYPE "hexagon-mcduplex-info" 36 static const std::pair<unsigned, unsigned>
opcodeData[] = {
37 std::make_pair((
unsigned)SA1_addi, 0),
38 std::make_pair((
unsigned)SA1_addrx, 6144),
39 std::make_pair((
unsigned)SA1_addsp, 3072),
40 std::make_pair((
unsigned)SA1_and1, 4608),
41 std::make_pair((
unsigned)SA1_clrf, 6768),
42 std::make_pair((
unsigned)SA1_clrfnew, 6736),
43 std::make_pair((
unsigned)SA1_clrt, 6752),
44 std::make_pair((
unsigned)SA1_clrtnew, 6720),
45 std::make_pair((
unsigned)SA1_cmpeqi, 6400),
46 std::make_pair((
unsigned)SA1_combine0i, 7168),
47 std::make_pair((
unsigned)SA1_combine1i, 7176),
48 std::make_pair((
unsigned)SA1_combine2i, 7184),
49 std::make_pair((
unsigned)SA1_combine3i, 7192),
50 std::make_pair((
unsigned)SA1_combinerz, 7432),
51 std::make_pair((
unsigned)SA1_combinezr, 7424),
52 std::make_pair((
unsigned)SA1_dec, 4864),
53 std::make_pair((
unsigned)SA1_inc, 4352),
54 std::make_pair((
unsigned)SA1_seti, 2048),
55 std::make_pair((
unsigned)SA1_setin1, 6656),
56 std::make_pair((
unsigned)SA1_sxtb, 5376),
57 std::make_pair((
unsigned)SA1_sxth, 5120),
58 std::make_pair((
unsigned)SA1_tfr, 4096),
59 std::make_pair((
unsigned)SA1_zxtb, 5888),
60 std::make_pair((
unsigned)SA1_zxth, 5632),
61 std::make_pair((
unsigned)SL1_loadri_io, 0),
62 std::make_pair((
unsigned)SL1_loadrub_io, 4096),
63 std::make_pair((
unsigned)SL2_deallocframe, 7936),
64 std::make_pair((
unsigned)SL2_jumpr31, 8128),
65 std::make_pair((
unsigned)SL2_jumpr31_f, 8133),
66 std::make_pair((
unsigned)SL2_jumpr31_fnew, 8135),
67 std::make_pair((
unsigned)SL2_jumpr31_t, 8132),
68 std::make_pair((
unsigned)SL2_jumpr31_tnew, 8134),
69 std::make_pair((
unsigned)SL2_loadrb_io, 4096),
70 std::make_pair((
unsigned)SL2_loadrd_sp, 7680),
71 std::make_pair((
unsigned)SL2_loadrh_io, 0),
72 std::make_pair((
unsigned)SL2_loadri_sp, 7168),
73 std::make_pair((
unsigned)SL2_loadruh_io, 2048),
74 std::make_pair((
unsigned)SL2_return, 8000),
75 std::make_pair((
unsigned)SL2_return_f, 8005),
76 std::make_pair((
unsigned)SL2_return_fnew, 8007),
77 std::make_pair((
unsigned)SL2_return_t, 8004),
78 std::make_pair((
unsigned)SL2_return_tnew, 8006),
79 std::make_pair((
unsigned)SS1_storeb_io, 4096),
80 std::make_pair((
unsigned)SS1_storew_io, 0),
81 std::make_pair((
unsigned)SS2_allocframe, 7168),
82 std::make_pair((
unsigned)SS2_storebi0, 4608),
83 std::make_pair((
unsigned)SS2_storebi1, 4864),
84 std::make_pair((
unsigned)SS2_stored_sp, 2560),
85 std::make_pair((
unsigned)SS2_storeh_io, 0),
86 std::make_pair((
unsigned)SS2_storew_sp, 2048),
87 std::make_pair((
unsigned)SS2_storewi0, 4096),
88 std::make_pair((
unsigned)SS2_storewi1, 4352)};
191 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
201 case Hexagon::L2_loadri_io:
208 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
213 inRange<4, 2>(MCI, 2)) {
218 case Hexagon::L2_loadrub_io:
224 inRange<4>(MCI, 2)) {
238 case Hexagon::L2_loadrh_io:
239 case Hexagon::L2_loadruh_io:
245 inRange<3, 1>(MCI, 2)) {
249 case Hexagon::L2_loadrb_io:
255 inRange<3>(MCI, 2)) {
259 case Hexagon::L2_loadrd_io:
265 inRange<5, 3>(MCI, 2)) {
270 case Hexagon::L4_return:
271 case Hexagon::L2_deallocframe:
274 case Hexagon::EH_RETURN_JMPR:
275 case Hexagon::J2_jumpr:
276 case Hexagon::PS_jmpret:
280 if (Hexagon::R31 == DstReg)
284 case Hexagon::J2_jumprt:
285 case Hexagon::J2_jumprf:
286 case Hexagon::J2_jumprtnew:
287 case Hexagon::J2_jumprfnew:
288 case Hexagon::J2_jumprtnewpt:
289 case Hexagon::J2_jumprfnewpt:
290 case Hexagon::PS_jmprett:
291 case Hexagon::PS_jmpretf:
292 case Hexagon::PS_jmprettnew:
293 case Hexagon::PS_jmpretfnew:
294 case Hexagon::PS_jmprettnewpt:
295 case Hexagon::PS_jmpretfnewpt:
300 (Hexagon::R31 == DstReg)) {
304 case Hexagon::L4_return_t:
305 case Hexagon::L4_return_f:
306 case Hexagon::L4_return_tnew_pnt:
307 case Hexagon::L4_return_fnew_pnt:
308 case Hexagon::L4_return_tnew_pt:
309 case Hexagon::L4_return_fnew_pt:
312 if (Hexagon::P0 == SrcReg) {
321 case Hexagon::S2_storeri_io:
328 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) {
334 inRange<4, 2>(MCI, 1)) {
338 case Hexagon::S2_storerb_io:
344 inRange<4>(MCI, 1)) {
357 case Hexagon::S2_storerh_io:
363 inRange<3, 1>(MCI, 1)) {
367 case Hexagon::S2_storerd_io:
373 inSRange<6, 3>(MCI, 1)) {
377 case Hexagon::S4_storeiri_io:
381 inRange<4, 2>(MCI, 1) && inRange<1>(MCI, 2)) {
385 case Hexagon::S4_storeirb_io:
389 inRange<4>(MCI, 1) && inRange<1>(MCI, 2)) {
393 case Hexagon::S2_allocframe:
394 if (inRange<5, 3>(MCI, 2))
415 case Hexagon::A2_addi:
421 inRange<6, 2>(MCI, 2)) {
425 if (DstReg == SrcReg) {
436 case Hexagon::A2_add:
446 case Hexagon::A2_andir:
455 case Hexagon::A2_tfr:
464 case Hexagon::A2_tfrsi:
471 case Hexagon::C2_cmoveit:
472 case Hexagon::C2_cmovenewit:
473 case Hexagon::C2_cmoveif:
474 case Hexagon::C2_cmovenewif:
481 Hexagon::P0 == PredReg &&
minConstant(MCI, 2) == 0) {
485 case Hexagon::C2_cmpeqi:
489 if (Hexagon::P0 == DstReg &&
491 inRange<2>(MCI, 2)) {
495 case Hexagon::A2_combineii:
496 case Hexagon::A4_combineii:
500 inRange<2>(MCI, 1) && inRange<2>(MCI, 2)) {
504 case Hexagon::A4_combineri:
514 case Hexagon::A4_combineir:
524 case Hexagon::A2_sxtb:
525 case Hexagon::A2_sxth:
526 case Hexagon::A2_zxtb:
527 case Hexagon::A2_zxth:
542 unsigned DstReg, SrcReg;
544 case Hexagon::A2_addi:
552 if (!isShiftedInt<7, 0>(Value))
556 case Hexagon::A2_tfrsi:
567 if (!isShiftedUInt<6, 0>(Value))
579 MCInst const &MIa,
bool ExtendedA,
580 MCInst const &MIb,
bool ExtendedB,
589 if ((Opcode != Hexagon::A2_addi) && (Opcode != Hexagon::A2_tfrsi))
604 unsigned zeroedSubInstS0 =
606 unsigned zeroedSubInstS1 =
609 if (zeroedSubInstS0 < zeroedSubInstS1)
616 if (MIb.
getOpcode() == Hexagon::S2_allocframe)
711 case Hexagon::A2_addi:
739 case Hexagon::A2_add:
745 case Hexagon::S2_allocframe:
746 Result.
setOpcode(Hexagon::SS2_allocframe);
749 case Hexagon::A2_andir:
761 case Hexagon::C2_cmpeqi:
766 case Hexagon::A4_combineii:
767 case Hexagon::A2_combineii:
769 assert(Absolute);(void)Absolute;
771 Result.
setOpcode(Hexagon::SA1_combine1i);
777 Result.
setOpcode(Hexagon::SA1_combine3i);
783 Result.
setOpcode(Hexagon::SA1_combine0i);
789 Result.
setOpcode(Hexagon::SA1_combine2i);
795 case Hexagon::A4_combineir:
796 Result.
setOpcode(Hexagon::SA1_combinezr);
800 case Hexagon::A4_combineri:
801 Result.
setOpcode(Hexagon::SA1_combinerz);
805 case Hexagon::L4_return_tnew_pnt:
806 case Hexagon::L4_return_tnew_pt:
807 Result.
setOpcode(Hexagon::SL2_return_tnew);
809 case Hexagon::L4_return_fnew_pnt:
810 case Hexagon::L4_return_fnew_pt:
811 Result.
setOpcode(Hexagon::SL2_return_fnew);
813 case Hexagon::L4_return_f:
816 case Hexagon::L4_return_t:
819 case Hexagon::L4_return:
822 case Hexagon::L2_deallocframe:
823 Result.
setOpcode(Hexagon::SL2_deallocframe);
825 case Hexagon::EH_RETURN_JMPR:
826 case Hexagon::J2_jumpr:
827 case Hexagon::PS_jmpret:
830 case Hexagon::J2_jumprf:
831 case Hexagon::PS_jmpretf:
832 Result.
setOpcode(Hexagon::SL2_jumpr31_f);
834 case Hexagon::J2_jumprfnew:
835 case Hexagon::J2_jumprfnewpt:
836 case Hexagon::PS_jmpretfnewpt:
837 case Hexagon::PS_jmpretfnew:
838 Result.
setOpcode(Hexagon::SL2_jumpr31_fnew);
840 case Hexagon::J2_jumprt:
841 case Hexagon::PS_jmprett:
842 Result.
setOpcode(Hexagon::SL2_jumpr31_t);
844 case Hexagon::J2_jumprtnew:
845 case Hexagon::J2_jumprtnewpt:
846 case Hexagon::PS_jmprettnewpt:
847 case Hexagon::PS_jmprettnew:
848 Result.
setOpcode(Hexagon::SL2_jumpr31_tnew);
850 case Hexagon::L2_loadrb_io:
851 Result.
setOpcode(Hexagon::SL2_loadrb_io);
856 case Hexagon::L2_loadrd_io:
857 Result.
setOpcode(Hexagon::SL2_loadrd_sp);
861 case Hexagon::L2_loadrh_io:
862 Result.
setOpcode(Hexagon::SL2_loadrh_io);
867 case Hexagon::L2_loadrub_io:
868 Result.
setOpcode(Hexagon::SL1_loadrub_io);
873 case Hexagon::L2_loadruh_io:
874 Result.
setOpcode(Hexagon::SL2_loadruh_io);
879 case Hexagon::L2_loadri_io:
881 Result.
setOpcode(Hexagon::SL2_loadri_sp);
886 Result.
setOpcode(Hexagon::SL1_loadri_io);
892 case Hexagon::S4_storeirb_io:
894 assert(Absolute);(void)Absolute;
900 }
else if (Value == 1) {
907 case Hexagon::S2_storerb_io:
908 Result.
setOpcode(Hexagon::SS1_storeb_io);
913 case Hexagon::S2_storerd_io:
914 Result.
setOpcode(Hexagon::SS2_stored_sp);
918 case Hexagon::S2_storerh_io:
919 Result.
setOpcode(Hexagon::SS2_storeh_io);
924 case Hexagon::S4_storeiri_io:
926 assert(Absolute);(void)Absolute;
932 }
else if (Value == 1) {
938 Result.
setOpcode(Hexagon::SS2_storew_sp);
944 case Hexagon::S2_storeri_io:
946 Result.
setOpcode(Hexagon::SS2_storew_sp);
950 Result.
setOpcode(Hexagon::SS1_storew_io);
956 case Hexagon::A2_sxtb:
961 case Hexagon::A2_sxth:
966 case Hexagon::A2_tfr:
971 case Hexagon::C2_cmovenewif:
976 case Hexagon::C2_cmovenewit:
981 case Hexagon::C2_cmoveif:
986 case Hexagon::C2_cmoveit:
991 case Hexagon::A2_tfrsi:
993 if (Absolute && Value == -1) {
1004 case Hexagon::A2_zxtb:
1010 case Hexagon::A2_zxth:
1021 case Hexagon::S2_storeri_io:
1022 case Hexagon::S2_storerb_io:
1023 case Hexagon::S2_storerh_io:
1024 case Hexagon::S2_storerd_io:
1025 case Hexagon::S4_storeiri_io:
1026 case Hexagon::S4_storeirb_io:
1027 case Hexagon::S2_allocframe:
1043 for (
unsigned distance = 1; distance < numInstrInPacket; ++distance) {
1046 (j < numInstrInPacket) && (k < numInstrInPacket); ++j, ++k) {
1049 bool bisReversable =
true;
1052 LLVM_DEBUG(
dbgs() <<
"skip out of order write pair: " << k <<
"," << j
1054 bisReversable =
false;
1057 bisReversable =
false;
1065 bisReversable, STI)) {
1084 if (bisReversable) {
1090 bisReversable, STI)) {
1099 <<
"adding pair:" << k <<
"," << j <<
":" 1104 <<
"skipping pair: " << k <<
"," << j <<
":"
const_iterator end(StringRef path)
Get end iterator over path.
bool subInstWouldBeExtended(MCInst const &potentialDuplex)
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
This class represents lattice values for constants.
LLVM_NODISCARD bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
bool isDuplexPair(MCInst const &MIa, MCInst const &MIb)
Symmetrical. See if these two instructions are fit for duplex pair.
void push_back(const T &Elt)
static const std::pair< unsigned, unsigned > opcodeData[]
bool isIntRegForSubInst(unsigned Reg)
bool isBundle(MCInst const &MCI)
bool isDblRegForSubInst(unsigned Reg)
unsigned getReg() const
Returns the register number.
const MCInst * getInst() const
const MCExpr * getExpr() const
Instances of this class represent a single low-level machine instruction.
bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
unsigned getDuplexCandidateGroup(MCInst const &MI)
Interface to description of machine instruction set.
unsigned getNumOperands() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static void addOps(MCInst &subInstPtr, MCInst const &Inst, unsigned opNum)
void setOpcode(unsigned Op)
size_t const bundleInstructionsOffset
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
const MCOperand & getOperand(unsigned i) const
int64_t minConstant(MCInst const &MCI, size_t Index)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
bool isMemReorderDisabled(MCInst const &MCI)
MCInst deriveSubInst(MCInst const &Inst)
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
Generic base class for all target subtargets.
static bool isStoreInst(unsigned opCode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isPredReg(unsigned Reg)
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
bool isIntReg(unsigned Reg)
void addOperand(const MCOperand &Op)
unsigned getOpcode() const
unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb)
bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, bool bisReversable, MCSubtargetInfo const &STI)
non-Symmetrical. See if these two instructions are fit for duplex pair.