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25 #define DEBUG_TYPE "hexagon-shuffle"
31 cl::desc(
"Disable Hexagon instruction shuffling"));
33 void HexagonMCShuffler::init(
MCInst &MCB) {
35 MCInst const *Extender =
nullptr;
55 void HexagonMCShuffler::init(
MCInst &MCB,
MCInst const &AddMI,
56 bool bInsertAtFront) {
60 MCInst const *Extender =
nullptr;
84 for (
auto &
I : *
this) {
86 MCInst const *Extender =
I.getExtender();
152 bool doneShuffling =
false;
153 while (possibleDuplexes.size() > 0 && (!doneShuffling)) {
159 if (MCS.
size() == 1) {
171 if (!doneShuffling) {
176 return doneShuffling;
181 MCInst const &AddMI,
int fixupCount) {
191 if (fixupCount >= 2) {
213 if (bhasDuplex &&
bundleSize >= maxBundleSize)
This is an optimization pass for GlobalISel generic memory operations.
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
static MCOperand createImm(int64_t Val)
Context object for machine code objects.
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool HexagonMCShuffle(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
bool isImmext(MCInst const &MCI)
LLVM_NODISCARD T pop_back_val()
Instances of this class represent a single low-level machine instruction.
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool hasImmExt(MCInst const &MCI)
bool isBundle(MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
size_t bundleSize(MCInst const &MCI)
static MCOperand createInst(const MCInst *Val)
void addOperand(const MCOperand Op)
initializer< Ty > init(const Ty &Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
const MCSubtargetInfo & STI
void append(MCInst const &ID, MCInst const *Extender, unsigned S)
bool isPseudo(uint64_t TSFlags)
bool reshuffleTo(MCInst &MCB)
Interface to description of machine instruction set.
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
static cl::opt< bool > DisableShuffle("disable-hexagon-shuffle", cl::Hidden, cl::init(false), cl::desc("Disable Hexagon instruction shuffling"))
const MCOperand & getOperand(unsigned i) const
#define HEXAGON_PACKET_SIZE
Generic base class for all target subtargets.