LLVM  14.0.0git
HexagonShuffler.cpp
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1 //===- HexagonShuffler.cpp - Instruction bundle shuffling -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the shuffling of insns inside a bundle according to the
10 // packet formation rules of the Hexagon ISA.
11 //
12 //===----------------------------------------------------------------------===//
13 
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrDesc.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/SourceMgr.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <utility>
32 #include <vector>
33 
34 #define DEBUG_TYPE "hexagon-shuffle"
35 
36 using namespace llvm;
37 
38 namespace {
39 
40 // Insn shuffling priority.
41 class HexagonBid {
42  // The priority is directly proportional to how restricted the insn is based
43  // on its flexibility to run on the available slots. So, the fewer slots it
44  // may run on, the higher its priority.
45  enum { MAX = 360360 }; // LCD of 1/2, 1/3, 1/4,... 1/15.
46  unsigned Bid = 0;
47 
48 public:
49  HexagonBid() = default;
50  HexagonBid(unsigned B) { Bid = B ? MAX / countPopulation(B) : 0; }
51 
52  // Check if the insn priority is overflowed.
53  bool isSold() const { return (Bid >= MAX); }
54 
55  HexagonBid &operator+=(const HexagonBid &B) {
56  Bid += B.Bid;
57  return *this;
58  }
59 };
60 
61 // Slot shuffling allocation.
62 class HexagonUnitAuction {
63  HexagonBid Scores[HEXAGON_PACKET_SIZE];
64  // Mask indicating which slot is unavailable.
65  unsigned isSold : HEXAGON_PACKET_SIZE;
66 
67 public:
68  HexagonUnitAuction(unsigned cs = 0) : isSold(cs) {}
69 
70  // Allocate slots.
71  bool bid(unsigned B) {
72  // Exclude already auctioned slots from the bid.
73  unsigned b = B & ~isSold;
74  if (b) {
75  for (unsigned i = 0; i < HEXAGON_PACKET_SIZE; ++i)
76  if (b & (1 << i)) {
77  // Request candidate slots.
78  Scores[i] += HexagonBid(b);
79  isSold |= Scores[i].isSold() << i;
80  }
81  return true;
82  } else
83  // Error if the desired slots are already full.
84  return false;
85  }
86 };
87 
88 } // end anonymous namespace
89 
90 unsigned HexagonResource::setWeight(unsigned s) {
91  const unsigned SlotWeight = 8;
92  const unsigned MaskWeight = SlotWeight - 1;
93  unsigned Units = getUnits();
94  unsigned Key = ((1u << s) & Units) != 0;
95 
96  // Calculate relative weight of the insn for the given slot, weighing it the
97  // heavier the more restrictive the insn is and the lowest the slots that the
98  // insn may be executed in.
99  if (Key == 0 || Units == 0 || (SlotWeight * s >= 32))
100  return Weight = 0;
101 
102  unsigned Ctpop = countPopulation(Units);
103  unsigned Cttz = countTrailingZeros(Units);
104  Weight = (1u << (SlotWeight * s)) * ((MaskWeight - Ctpop) << Cttz);
105  return Weight;
106 }
107 
109  MCSubtargetInfo const &STI,
110  unsigned s,
111  MCInst const *id)
112  : HexagonResource(s) {
113 
114  const unsigned ItinUnits = HexagonMCInstrInfo::getCVIResources(MCII, STI, *id);
115  unsigned Lanes;
116  const unsigned Units = HexagonConvertUnits(ItinUnits, &Lanes);
117 
118  if (Units == 0 && Lanes == 0) {
119  // For core insns.
120  Valid = false;
121  setUnits(0);
122  setLanes(0);
123  setLoad(false);
124  setStore(false);
125  } else {
126  // For an HVX insn.
127  Valid = true;
128  setUnits(Units);
129  setLanes(Lanes);
130  setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad());
131  setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore());
132  }
133 }
134 
135 struct CVIUnits {
136  unsigned Units;
137  unsigned Lanes;
138 };
140 
141 static unsigned makeAllBits(unsigned startBit, unsigned Lanes)
142 {
143  for (unsigned i = 1; i < Lanes; ++i)
144  startBit = (startBit << 1) | startBit;
145  return startBit;
146 }
147 
148 static bool checkHVXPipes(const HVXInstsT &hvxInsts, unsigned startIdx,
149  unsigned usedUnits) {
150  if (startIdx < hvxInsts.size()) {
151  if (!hvxInsts[startIdx].Units)
152  return checkHVXPipes(hvxInsts, startIdx + 1, usedUnits);
153  for (unsigned b = 0x1; b <= 0x8; b <<= 1) {
154  if ((hvxInsts[startIdx].Units & b) == 0)
155  continue;
156  unsigned allBits = makeAllBits(b, hvxInsts[startIdx].Lanes);
157  if ((allBits & usedUnits) == 0) {
158  if (checkHVXPipes(hvxInsts, startIdx + 1, usedUnits | allBits))
159  return true;
160  }
161  }
162  return false;
163  }
164  return true;
165 }
166 
168  MCInstrInfo const &MCII,
169  MCSubtargetInfo const &STI)
170  : Context(Context), MCII(MCII), STI(STI), ReportErrors(ReportErrors) {
171  reset();
172 }
173 
175  Packet.clear();
176  BundleFlags = 0;
177  CheckFailure = false;
178 }
179 
180 void HexagonShuffler::append(MCInst const &ID, MCInst const *Extender,
181  unsigned S) {
182  HexagonInstr PI(MCII, STI, &ID, Extender, S);
183 
184  Packet.push_back(PI);
185 }
186 
187 
188 static const unsigned Slot0Mask = 1 << 0;
189 static const unsigned Slot1Mask = 1 << 1;
190 static const unsigned Slot3Mask = 1 << 3;
191 static const unsigned slotSingleLoad = Slot0Mask;
192 static const unsigned slotSingleStore = Slot0Mask;
193 
194 void HexagonShuffler::restrictSlot1AOK(HexagonPacketSummary const &Summary) {
195  if (Summary.Slot1AOKLoc)
196  for (HexagonInstr &ISJ : insts()) {
197  MCInst const &Inst = ISJ.getDesc();
198  const unsigned Type = HexagonMCInstrInfo::getType(MCII, Inst);
202  const unsigned Units = ISJ.Core.getUnits();
203 
204  if (Units & Slot1Mask) {
205  AppliedRestrictions.push_back(std::make_pair(
206  Inst.getLoc(),
207  "Instruction was restricted from being in slot 1"));
208  AppliedRestrictions.push_back(std::make_pair(
209  *Summary.Slot1AOKLoc, "Instruction can only be combined "
210  "with an ALU instruction in slot 1"));
211  ISJ.Core.setUnits(Units & ~Slot1Mask);
212  }
213  }
214  }
215 }
216 
218  HexagonPacketSummary const &Summary) {
219  // If this packet contains an instruction that bars slot-1 stores,
220  // we should mask off slot 1 from all of the store instructions in
221  // this packet.
222 
223  if (!Summary.NoSlot1StoreLoc)
224  return;
225 
226  bool AppliedRestriction = false;
227 
228  for (HexagonInstr &ISJ : insts()) {
229  MCInst const &Inst = ISJ.getDesc();
230  if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) {
231  unsigned Units = ISJ.Core.getUnits();
232  if (Units & Slot1Mask) {
233  AppliedRestriction = true;
234  AppliedRestrictions.push_back(std::make_pair(
235  Inst.getLoc(), "Instruction was restricted from being in slot 1"));
236  ISJ.Core.setUnits(Units & ~Slot1Mask);
237  }
238  }
239  }
240 
241  if (AppliedRestriction)
242  AppliedRestrictions.push_back(
243  std::make_pair(*Summary.NoSlot1StoreLoc,
244  "Instruction does not allow a store in slot 1"));
245 }
246 
248  HexagonPacketSummary const &Summary) {
249  // These restrictions can modify the slot masks in the instructions
250  // in the Packet member. They should run unconditionally and their
251  // order does not matter.
252  restrictSlot1AOK(Summary);
253  restrictNoSlot1Store(Summary);
254 
255  permitNonSlot();
256 
257  // These restrictions can modify the slot masks in the instructions
258  // in the Packet member, but they can also detect constraint failures
259  // which are fatal.
260  if (!CheckFailure)
261  restrictStoreLoadOrder(Summary);
262  if (!CheckFailure)
263  restrictBranchOrder(Summary);
264  if (!CheckFailure)
265  restrictPreferSlot3(Summary);
266  return !CheckFailure;
267 }
268 
269 void HexagonShuffler::restrictBranchOrder(HexagonPacketSummary const &Summary) {
270  // preserve branch order
271  const bool HasMultipleBranches = Summary.branchInsts.size() > 1;
272  if (!HasMultipleBranches)
273  return;
274 
275  if (Summary.branchInsts.size() > 2) {
276  reportError(Twine("too many branches in packet"));
277  return;
278  }
279 
280  const static std::pair<unsigned, unsigned> jumpSlots[] = {
281  {8, 4}, {8, 2}, {8, 1}, {4, 2}, {4, 1}, {2, 1}};
282  // try all possible choices
283  for (std::pair<unsigned, unsigned> jumpSlot : jumpSlots) {
284  // validate first jump with this slot rule
285  if (!(jumpSlot.first & Summary.branchInsts[0]->Core.getUnits()))
286  continue;
287 
288  // validate second jump with this slot rule
289  if (!(jumpSlot.second & Summary.branchInsts[1]->Core.getUnits()))
290  continue;
291 
292  // both valid for this configuration, set new slot rules
293  const HexagonPacket PacketSave = Packet;
294  Summary.branchInsts[0]->Core.setUnits(jumpSlot.first);
295  Summary.branchInsts[1]->Core.setUnits(jumpSlot.second);
296 
297  const bool HasShuffledPacket = tryAuction(Summary).hasValue();
298  if (HasShuffledPacket)
299  return;
300 
301  // if yes, great, if not then restore original slot mask
302  // restore original values
303  Packet = PacketSave;
304  }
305 
306  reportError("invalid instruction packet: out of slots");
307 }
308 
309 
311  for (HexagonInstr &ISJ : insts()) {
312  const bool RequiresSlot = HexagonMCInstrInfo::requiresSlot(STI, *ISJ.ID);
313  if (!RequiresSlot)
314  ISJ.Core.setAllUnits();
315  }
316 }
317 
318 bool HexagonShuffler::ValidResourceUsage(HexagonPacketSummary const &Summary) {
319  Optional<HexagonPacket> ShuffledPacket = tryAuction(Summary);
320 
321  if (!ShuffledPacket) {
322  reportError("invalid instruction packet: slot error");
323  return false;
324  } else {
325  Packet = *ShuffledPacket;
326  }
327 
328  // Verify the CVI slot subscriptions.
330  // create vector of hvx instructions to check
331  HVXInstsT hvxInsts;
332  hvxInsts.clear();
333  for (const_iterator I = cbegin(); I != cend(); ++I) {
334  struct CVIUnits inst;
335  inst.Units = I->CVI.getUnits();
336  inst.Lanes = I->CVI.getLanes();
337  if (inst.Units == 0)
338  continue; // not an hvx inst or an hvx inst that doesn't uses any pipes
339  hvxInsts.push_back(inst);
340  }
341 
342  // if there are any hvx instructions in this packet, check pipe usage
343  if (hvxInsts.size() > 0) {
344  unsigned startIdx, usedUnits;
345  startIdx = usedUnits = 0x0;
346  if (!checkHVXPipes(hvxInsts, startIdx, usedUnits)) {
347  // too many pipes used to be valid
348  reportError(Twine("invalid instruction packet: slot error"));
349  return false;
350  }
351  }
352  return true;
353 }
354 
356  HexagonPacketSummary const &Summary) {
357  // Modify packet accordingly.
358  // TODO: need to reserve slots #0 and #1 for duplex insns.
359  static const unsigned slotFirstLoadStore = Slot1Mask;
360  static const unsigned slotLastLoadStore = Slot0Mask;
361  unsigned slotLoadStore = slotFirstLoadStore;
362 
363  for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
364  MCInst const &ID = ISJ->getDesc();
365 
366  if (!ISJ->Core.getUnits())
367  // Error if insn may not be executed in any slot.
368  return false;
369 
370  // A single load must use slot #0.
372  if (Summary.loads == 1 && Summary.loads == Summary.memory &&
373  Summary.memops == 0)
374  // Pin the load to slot #0.
375  switch (ID.getOpcode()) {
376  case Hexagon::V6_vgathermw:
377  case Hexagon::V6_vgathermh:
378  case Hexagon::V6_vgathermhw:
379  case Hexagon::V6_vgathermwq:
380  case Hexagon::V6_vgathermhq:
381  case Hexagon::V6_vgathermhwq:
382  // Slot1 only loads
383  break;
384  default:
385  ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleLoad);
386  break;
387  }
388  else if (Summary.loads >= 1 && isMemReorderDisabled()) { // }:mem_noshuf
389  // Loads must keep the original order ONLY if
390  // isMemReorderDisabled() == true
391  if (slotLoadStore < slotLastLoadStore) {
392  // Error if no more slots available for loads.
393  reportError("invalid instruction packet: too many loads");
394  return false;
395  }
396  // Pin the load to the highest slot available to it.
397  ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore);
398  // Update the next highest slot available to loads.
399  slotLoadStore >>= 1;
400  }
401  }
402 
403  // A single store must use slot #0.
404  if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) {
405  if (!Summary.store0) {
406  const bool PacketHasNoOnlySlot0 =
407  llvm::none_of(insts(), [&](HexagonInstr const &I) {
408  return I.Core.getUnits() == Slot0Mask &&
409  I.ID->getOpcode() != ID.getOpcode();
410  });
411  const bool SafeToMoveToSlot0 =
412  (Summary.loads == 0) ||
413  (!isMemReorderDisabled() && PacketHasNoOnlySlot0);
414 
415  if (Summary.stores == 1 && SafeToMoveToSlot0)
416  // Pin the store to slot #0 only if isMemReorderDisabled() == false
417  ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleStore);
418  else if (Summary.stores >= 1) {
419  if (slotLoadStore < slotLastLoadStore) {
420  // Error if no more slots available for stores.
421  reportError("invalid instruction packet: too many stores");
422  return false;
423  }
424  // Pin the store to the highest slot available to it.
425  ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore);
426  // Update the next highest slot available to stores.
427  slotLoadStore >>= 1;
428  }
429  }
430  if (Summary.store1 && Summary.stores > 1) {
431  // Error if a single store with another store.
432  reportError("invalid instruction packet: too many stores");
433  return false;
434  }
435  }
436  }
437 
438  return true;
439 }
440 
441 HexagonShuffler::HexagonPacketSummary HexagonShuffler::GetPacketSummary() {
442  HexagonPacketSummary Summary = HexagonPacketSummary();
443 
444  // Collect information from the insns in the packet.
445  for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
446  MCInst const &ID = ISJ->getDesc();
447 
449  Summary.Slot1AOKLoc = ID.getLoc();
451  Summary.NoSlot1StoreLoc = ID.getLoc();
452 
454  ++Summary.pSlot3Cnt;
455  Summary.PrefSlot3Inst = ISJ;
456  }
457  Summary.ReservedSlotMask |=
459 
460  switch (HexagonMCInstrInfo::getType(MCII, ID)) {
464  break;
465  case HexagonII::TypeJ:
466  Summary.branchInsts.push_back(ISJ);
467  break;
474  ++Summary.NonZCVIloads;
477  ++Summary.AllCVIloads;
479  case HexagonII::TypeLD:
480  ++Summary.loads;
481  ++Summary.memory;
482  if (ISJ->Core.getUnits() == slotSingleLoad ||
484  ++Summary.load0;
485  if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn())
486  Summary.branchInsts.push_back(ISJ);
487  break;
496  ++Summary.CVIstores;
498  case HexagonII::TypeST:
499  ++Summary.stores;
500  ++Summary.memory;
501  if (ISJ->Core.getUnits() == slotSingleStore ||
503  ++Summary.store0;
504  break;
506  ++Summary.loads;
507  ++Summary.stores;
508  ++Summary.store1;
509  ++Summary.memops;
510  ++Summary.memory;
511  break;
512  case HexagonII::TypeNCJ:
513  ++Summary.memory; // NV insns are memory-like.
514  Summary.branchInsts.push_back(ISJ);
515  break;
517  if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) {
518  ++Summary.loads;
519  ++Summary.memory;
520  if (ISJ->Core.getUnits() == slotSingleLoad ||
523  ++Summary.load0;
524  } else {
526  ++Summary.memory;
527  ++Summary.stores;
528  }
529  break;
530  case HexagonII::TypeCR:
531  // Legacy conditional branch predicated on a register.
532  case HexagonII::TypeCJ:
534  Summary.branchInsts.push_back(ISJ);
535  break;
536  case HexagonII::TypeDUPLEX: {
537  ++Summary.duplex;
538  MCInst const &Inst0 = *ID.getOperand(0).getInst();
539  MCInst const &Inst1 = *ID.getOperand(1).getInst();
541  Summary.branchInsts.push_back(ISJ);
543  Summary.branchInsts.push_back(ISJ);
544  if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isReturn())
545  Summary.branchInsts.push_back(ISJ);
546  if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isReturn())
547  Summary.branchInsts.push_back(ISJ);
548  break;
549  }
550  }
551  }
552  return Summary;
553 }
554 
556  HexagonPacketSummary const &Summary) const {
557  // Check if the packet is legal.
558  const unsigned ZCVIloads = Summary.AllCVIloads - Summary.NonZCVIloads;
559  const bool ValidHVXMem =
560  Summary.NonZCVIloads <= 1 && ZCVIloads <= 1 && Summary.CVIstores <= 1;
561  const bool InvalidPacket =
562  ((Summary.load0 > 1 || Summary.store0 > 1 || !ValidHVXMem) ||
563  (Summary.duplex > 1 || (Summary.duplex && Summary.memory)));
564 
565  return !InvalidPacket;
566 }
567 
568 void HexagonShuffler::restrictPreferSlot3(HexagonPacketSummary const &Summary) {
569  // flag if an instruction requires to be in slot 3
570  const bool HasOnlySlot3 = llvm::any_of(insts(), [&](HexagonInstr const &I) {
571  return (I.Core.getUnits() == Slot3Mask);
572  });
573  const bool NeedsPrefSlot3Shuffle =
574  (Summary.branchInsts.size() <= 1 && !HasOnlySlot3 &&
575  Summary.pSlot3Cnt == 1 && Summary.PrefSlot3Inst);
576 
577  if (!NeedsPrefSlot3Shuffle)
578  return;
579 
580  HexagonInstr *PrefSlot3Inst = *Summary.PrefSlot3Inst;
581  // save off slot mask of instruction marked with A_PREFER_SLOT3
582  // and then pin it to slot #3
583  const unsigned saveUnits = PrefSlot3Inst->Core.getUnits();
584  PrefSlot3Inst->Core.setUnits(saveUnits & Slot3Mask);
585  const bool HasShuffledPacket = tryAuction(Summary).hasValue();
586  if (HasShuffledPacket)
587  return;
588 
589  PrefSlot3Inst->Core.setUnits(saveUnits);
590 }
591 
592 /// Check that the packet is legal and enforce relative insn order.
594  const HexagonPacketSummary Summary = GetPacketSummary();
595  if (!applySlotRestrictions(Summary))
596  return false;
597 
598  if (!ValidPacketMemoryOps(Summary)) {
599  reportError("invalid instruction packet");
600  return false;
601  }
602 
603  ValidResourceUsage(Summary);
604 
605  return !CheckFailure;
606 }
607 
609 HexagonShuffler::tryAuction(HexagonPacketSummary const &Summary) const {
610  HexagonPacket PacketResult = Packet;
611  HexagonUnitAuction AuctionCore(Summary.ReservedSlotMask);
613 
614  const bool ValidSlots =
615  llvm::all_of(insts(PacketResult), [&AuctionCore](HexagonInstr const &I) {
616  return AuctionCore.bid(I.Core.getUnits());
617  });
618 
619  LLVM_DEBUG(
620  dbgs() << "Shuffle attempt: " << (ValidSlots ? "passed" : "failed")
621  << "\n";
622  for (HexagonInstr const &ISJ : insts(PacketResult))
623  dbgs() << "\t" << HexagonMCInstrInfo::getName(MCII, *ISJ.ID) << ": "
624  << llvm::format_hex(ISJ.Core.getUnits(), 4, true) << "\n";
625  );
626 
628  if (ValidSlots)
629  Res = PacketResult;
630 
631  return Res;
632 }
633 
635  if (size() > HEXAGON_PACKET_SIZE) {
636  // Ignore a packet with with more than what a packet can hold
637  // or with compound or duplex insns for now.
638  reportError(Twine("invalid instruction packet"));
639  return false;
640  }
641 
642  // Check and prepare packet.
643  bool Ok = true;
644  if (size() > 1 && (Ok = check()))
645  // Reorder the handles for each slot.
646  for (unsigned nSlot = 0, emptySlots = 0; nSlot < HEXAGON_PACKET_SIZE;
647  ++nSlot) {
648  iterator ISJ, ISK;
649  unsigned slotSkip, slotWeight;
650 
651  // Prioritize the handles considering their restrictions.
652  for (ISJ = ISK = Packet.begin(), slotSkip = slotWeight = 0;
653  ISK != Packet.end(); ++ISK, ++slotSkip)
654  if (slotSkip < nSlot - emptySlots)
655  // Note which handle to begin at.
656  ++ISJ;
657  else
658  // Calculate the weight of the slot.
659  slotWeight += ISK->Core.setWeight(HEXAGON_PACKET_SIZE - nSlot - 1);
660 
661  if (slotWeight)
662  // Sort the packet, favoring source order,
663  // beginning after the previous slot.
664  std::stable_sort(ISJ, Packet.end());
665  else
666  // Skip unused slot.
667  ++emptySlots;
668  }
669 
670  LLVM_DEBUG(
671  for (HexagonInstr const &ISJ : insts()) {
672  dbgs().write_hex(ISJ.Core.getUnits());
673  if (ISJ.CVI.isValid()) {
674  dbgs() << '/';
675  dbgs().write_hex(ISJ.CVI.getUnits()) << '|';
676  dbgs() << ISJ.CVI.getLanes();
677  }
678  dbgs() << ':'
679  << HexagonMCInstrInfo::getDesc(MCII, ISJ.getDesc()).getOpcode()
680  << '\n';
681  } dbgs() << '\n';
682  );
683 
684  return Ok;
685 }
686 
688  CheckFailure = true;
689  if (ReportErrors) {
690  for (auto const &I : AppliedRestrictions) {
691  auto SM = Context.getSourceManager();
692  if (SM)
693  SM->PrintMessage(I.first, SourceMgr::DK_Note, I.second);
694  }
695  Context.reportError(Loc, Msg);
696  }
697 }
i
i
Definition: README.txt:29
HexagonMCTargetDesc.h
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Definition: HexagonShuffler.h:174
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Definition: HexagonShuffler.cpp:192
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const_iterator cend() const
Definition: HexagonShuffler.h:221
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Definition: HexagonMCTargetDesc.cpp:150
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1614
llvm::HexagonII::TypeCVI_VM_VP_LDU
@ TypeCVI_VM_VP_LDU
Definition: HexagonDepITypes.h:41
llvm::HexagonCVIResource::HexagonCVIResource
HexagonCVIResource(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, unsigned s, MCInst const *id)
Definition: HexagonShuffler.cpp:108
llvm::HexagonShuffler::CheckFailure
bool CheckFailure
Definition: HexagonShuffler.h:178
llvm::HexagonCVIResource::mayLoad
bool mayLoad() const
Definition: HexagonShuffler.h:103
llvm::HexagonII::TypeCR
@ TypeCR
Definition: HexagonDepITypes.h:23
MCInstrDesc.h
llvm::HexagonMCInstrInfo::isRestrictSlot1AOK
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
Definition: HexagonMCInstrInfo.cpp:768
llvm::HexagonShuffler::restrictStoreLoadOrder
bool restrictStoreLoadOrder(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:355
llvm::HexagonShuffler::Loc
SMLoc Loc
Definition: HexagonShuffler.h:176
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::HexagonResource::setUnits
void setUnits(unsigned s)
Definition: HexagonShuffler.h:45
llvm::HexagonShuffler::isMemReorderDisabled
bool isMemReorderDisabled() const
Definition: HexagonShuffler.h:214
llvm::HexagonII::TypeLD
@ TypeLD
Definition: HexagonDepITypes.h:54
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
HexagonShuffler.h
llvm::HexagonMCInstrInfo::getCVIResources
unsigned getCVIResources(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the resources used by this instruction.
Definition: HexagonMCInstrInfo.cpp:423
llvm::HexagonShuffler::iterator
HexagonPacket::iterator iterator
Definition: HexagonShuffler.h:197
llvm::HexagonII::TypeALU32_3op
@ TypeALU32_3op
Definition: HexagonDepITypes.h:19
Slot0Mask
static const unsigned Slot0Mask
Definition: HexagonShuffler.cpp:188
llvm::HexagonShuffler::restrictNoSlot1Store
void restrictNoSlot1Store(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:217
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::HexagonII::TypeST
@ TypeST
Definition: HexagonDepITypes.h:59
llvm::HexagonII::TypeCVI_GATHER_RST
@ TypeCVI_GATHER_RST
Definition: HexagonDepITypes.h:27
llvm::HexagonResource::getUnits
unsigned getUnits() const
Definition: HexagonShuffler.h:55
llvm::Optional
Definition: APInt.h:33
llvm::HexagonII::TypeCVI_ZW
@ TypeCVI_ZW
Definition: HexagonDepITypes.h:49
llvm::SourceMgr::DK_Note
@ DK_Note
Definition: SourceMgr.h:37
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
slotSingleLoad
static const unsigned slotSingleLoad
Definition: HexagonShuffler.cpp:191
llvm::HexagonMCInstrInfo::prefersSlot3
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:936
llvm::HexagonII::TypeCVI_GATHER_DV
@ TypeCVI_GATHER_DV
Definition: HexagonDepITypes.h:26
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
HexagonBaseInfo.h
llvm::HexagonShuffler::permitNonSlot
void permitNonSlot()
Definition: HexagonShuffler.cpp:310
llvm::HexagonMCInstrInfo::getOtherReservedSlots
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of.
Definition: HexagonMCInstrInfo.cpp:454
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
makeAllBits
static unsigned makeAllBits(unsigned startBit, unsigned Lanes)
Definition: HexagonShuffler.cpp:141
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::HexagonII::TypeV2LDST
@ TypeV2LDST
Definition: HexagonDepITypes.h:63
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1600
Slot1Mask
static const unsigned Slot1Mask
Definition: HexagonShuffler.cpp:189
llvm::HexagonII::TypeCVI_VM_NEW_ST
@ TypeCVI_VM_NEW_ST
Definition: HexagonDepITypes.h:37
llvm::HexagonInstr::lessCVI
static bool lessCVI(const HexagonInstr &A, const HexagonInstr &B)
Definition: HexagonShuffler.h:136
llvm::HexagonShuffler::restrictSlot1AOK
void restrictSlot1AOK(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:194
llvm::HexagonMCInstrInfo::requiresSlot
bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:948
HexagonMCInstrInfo.h
llvm::HexagonII::TypeCVI_SCATTER_RST
@ TypeCVI_SCATTER_RST
Definition: HexagonDepITypes.h:33
llvm::HexagonShuffler::restrictBranchOrder
void restrictBranchOrder(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:269
llvm::HexagonCVIResource::mayStore
bool mayStore() const
Definition: HexagonShuffler.h:104
Twine.h
MCContext.h
llvm::HexagonShuffler::size
unsigned size() const
Definition: HexagonShuffler.h:212
llvm::operator+=
std::string & operator+=(std::string &buffer, StringRef string)
Definition: StringRef.h:940
llvm::HexagonShuffler::insts
packet_range insts()
Definition: HexagonShuffler.h:228
b
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
Definition: README.txt:418
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:481
MCInst.h
llvm::HexagonMCInstrInfo::getName
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:367
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MCSubtargetInfo.h
llvm::HexagonII::TypeV4LDST
@ TypeV4LDST
Definition: HexagonDepITypes.h:64
llvm::HexagonShuffler::Context
MCContext & Context
Definition: HexagonShuffler.h:172
llvm::HexagonII::TypeCVI_SCATTER_NEW_ST
@ TypeCVI_SCATTER_NEW_ST
Definition: HexagonDepITypes.h:32
llvm::HexagonMCInstrInfo::isRestrictNoSlot1Store
bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:775
llvm::HexagonShuffler::check
bool check()
Check that the packet is legal and enforce relative insn order.
Definition: HexagonShuffler.cpp:593
SourceMgr.h
llvm::HexagonShuffler::end
iterator end()
Definition: HexagonShuffler.h:219
llvm::HexagonII::TypeS_2op
@ TypeS_2op
Definition: HexagonDepITypes.h:61
llvm::MCInstrDesc::mayLoad
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:429
llvm::countPopulation
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:567
llvm::HexagonInstr
Definition: HexagonShuffler.h:108
llvm::HexagonII::TypeALU64
@ TypeALU64
Definition: HexagonDepITypes.h:21
llvm::SourceMgr::PrintMessage
void PrintMessage(raw_ostream &OS, SMLoc Loc, DiagKind Kind, const Twine &Msg, ArrayRef< SMRange > Ranges={}, ArrayRef< SMFixIt > FixIts={}, bool ShowColors=true) const
Emit a message about the specified location with the specified string.
Definition: SourceMgr.cpp:341
s
multiplies can be turned into SHL s
Definition: README.txt:370
llvm::HexagonII::TypeCVI_GATHER
@ TypeCVI_GATHER
Definition: HexagonDepITypes.h:25
llvm::HexagonShuffler::cbegin
const_iterator cbegin() const
Definition: HexagonShuffler.h:220
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::HexagonShuffler::applySlotRestrictions
bool applySlotRestrictions(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:247
llvm::HexagonShuffler::AppliedRestrictions
std::vector< std::pair< SMLoc, std::string > > AppliedRestrictions
Definition: HexagonShuffler.h:179
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCContext::reportError
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:963
isBranch
static bool isBranch(unsigned Opcode)
Definition: R600InstrInfo.cpp:647
llvm::HexagonShuffler::BundleFlags
int64_t BundleFlags
Definition: HexagonShuffler.h:173
llvm::HexagonII::TypeCVI_SCATTER
@ TypeCVI_SCATTER
Definition: HexagonDepITypes.h:29
llvm::HexagonII::TypeALU32_2op
@ TypeALU32_2op
Definition: HexagonDepITypes.h:18
llvm::HexagonII::TypeCVI_VM_LD
@ TypeCVI_VM_LD
Definition: HexagonDepITypes.h:36
llvm::HexagonShuffler::STI
const MCSubtargetInfo & STI
Definition: HexagonShuffler.h:175
llvm::HexagonShuffler::append
void append(MCInst const &ID, MCInst const *Extender, unsigned S)
Definition: HexagonShuffler.cpp:180
llvm::HexagonShuffler::ValidResourceUsage
bool ValidResourceUsage(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:318
llvm::HexagonII::TypeDUPLEX
@ TypeDUPLEX
Definition: HexagonDepITypes.h:50
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1607
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
llvm::HexagonResource
Definition: HexagonShuffler.h:37
llvm::HexagonII::TypeCVI_SCATTER_NEW_RST
@ TypeCVI_SCATTER_NEW_RST
Definition: HexagonDepITypes.h:31
llvm::HexagonResource::setWeight
unsigned setWeight(unsigned s)
Definition: HexagonShuffler.cpp:90
Compiler.h
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::HexagonII::TypeCJ
@ TypeCJ
Definition: HexagonDepITypes.h:22
llvm::HexagonShuffler::reset
void reset()
Definition: HexagonShuffler.cpp:174
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
CVIUnits
Definition: HexagonShuffler.cpp:135
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::MCInst::getLoc
SMLoc getLoc() const
Definition: MCInst.h:204
llvm::stable_sort
void stable_sort(R &&Range)
Definition: STLExtras.h:1735
CVIUnits::Units
unsigned Units
Definition: HexagonShuffler.cpp:136
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::HexagonMCInstrInfo::getType
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
Definition: HexagonMCInstrInfo.cpp:416
llvm::HexagonII::TypeS_3op
@ TypeS_3op
Definition: HexagonDepITypes.h:62
Slot3Mask
static const unsigned Slot3Mask
Definition: HexagonShuffler.cpp:190
checkHVXPipes
static bool checkHVXPipes(const HVXInstsT &hvxInsts, unsigned startIdx, unsigned usedUnits)
Definition: HexagonShuffler.cpp:148
llvm::HexagonShuffler::ValidPacketMemoryOps
bool ValidPacketMemoryOps(HexagonPacketSummary const &Summary) const
Definition: HexagonShuffler.cpp:555
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:585
llvm::HexagonII::TypeCVI_VM_ST
@ TypeCVI_VM_ST
Definition: HexagonDepITypes.h:38
llvm::HexagonShuffler::HexagonShuffler
HexagonShuffler(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI)
Definition: HexagonShuffler.cpp:167
llvm::HexagonII::TypeCVI_VM_STU
@ TypeCVI_VM_STU
Definition: HexagonDepITypes.h:39
llvm::HexagonII::TypeNCJ
@ TypeNCJ
Definition: HexagonDepITypes.h:57
llvm::HexagonShuffler::ReportErrors
bool ReportErrors
Definition: HexagonShuffler.h:177
SmallVector.h
llvm::MCContext::getSourceManager
const SourceMgr * getSourceManager() const
Definition: MCContext.h:410
llvm::HexagonII::TypeCVI_SCATTER_DV
@ TypeCVI_SCATTER_DV
Definition: HexagonDepITypes.h:30
llvm::HexagonInstr::lessCore
static bool lessCore(const HexagonInstr &A, const HexagonInstr &B)
Definition: HexagonShuffler.h:131
CVIUnits::Lanes
unsigned Lanes
Definition: HexagonShuffler.cpp:137
llvm::HexagonII::TypeJ
@ TypeJ
Definition: HexagonDepITypes.h:53
llvm::HexagonShuffler::restrictPreferSlot3
void restrictPreferSlot3(HexagonPacketSummary const &Summary)
Definition: HexagonShuffler.cpp:568
raw_ostream.h
HEXAGON_PACKET_SIZE
#define HEXAGON_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
llvm::format_hex
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
Definition: Format.h:186
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::HexagonII::TypeCVI_VM_TMP_LD
@ TypeCVI_VM_TMP_LD
Definition: HexagonDepITypes.h:40
Debug.h
llvm::HexagonShuffler::tryAuction
Optional< HexagonPacket > tryAuction(HexagonPacketSummary const &Summary) const
Definition: HexagonShuffler.cpp:609
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::HexagonShuffler::const_iterator
HexagonPacket::const_iterator const_iterator
Definition: HexagonShuffler.h:198
llvm::raw_ostream::write_hex
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
Definition: raw_ostream.cpp:140