LLVM  10.0.0svn
Disassembler.cpp
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1 //===-- lib/MC/Disassembler.cpp - Disassembler Public C Interface ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "Disassembler.h"
10 #include "llvm-c/Disassembler.h"
11 #include "llvm/ADT/ArrayRef.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/Triple.h"
14 #include "llvm/MC/MCAsmInfo.h"
15 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstPrinter.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSchedule.h"
31 #include <cassert>
32 #include <cstddef>
33 #include <cstring>
34 
35 using namespace llvm;
36 
37 // LLVMCreateDisasm() creates a disassembler for the TripleName. Symbolic
38 // disassembly is supported by passing a block of information in the DisInfo
39 // parameter and specifying the TagType and callback functions as described in
40 // the header llvm-c/Disassembler.h . The pointer to the block and the
41 // functions can all be passed as NULL. If successful, this returns a
42 // disassembler context. If not, it returns NULL.
43 //
45 LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU,
46  const char *Features, void *DisInfo, int TagType,
47  LLVMOpInfoCallback GetOpInfo,
48  LLVMSymbolLookupCallback SymbolLookUp) {
49  // Get the target.
50  std::string Error;
51  const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
52  if (!TheTarget)
53  return nullptr;
54 
55  std::unique_ptr<const MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TT));
56  if (!MRI)
57  return nullptr;
58 
59  // Get the assembler info needed to setup the MCContext.
60  std::unique_ptr<const MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TT));
61  if (!MAI)
62  return nullptr;
63 
64  std::unique_ptr<const MCInstrInfo> MII(TheTarget->createMCInstrInfo());
65  if (!MII)
66  return nullptr;
67 
68  std::unique_ptr<const MCSubtargetInfo> STI(
69  TheTarget->createMCSubtargetInfo(TT, CPU, Features));
70  if (!STI)
71  return nullptr;
72 
73  // Set up the MCContext for creating symbols and MCExpr's.
74  std::unique_ptr<MCContext> Ctx(new MCContext(MAI.get(), MRI.get(), nullptr));
75  if (!Ctx)
76  return nullptr;
77 
78  // Set up disassembler.
79  std::unique_ptr<MCDisassembler> DisAsm(
80  TheTarget->createMCDisassembler(*STI, *Ctx));
81  if (!DisAsm)
82  return nullptr;
83 
84  std::unique_ptr<MCRelocationInfo> RelInfo(
85  TheTarget->createMCRelocationInfo(TT, *Ctx));
86  if (!RelInfo)
87  return nullptr;
88 
89  std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer(
90  TT, GetOpInfo, SymbolLookUp, DisInfo, Ctx.get(), std::move(RelInfo)));
91  DisAsm->setSymbolizer(std::move(Symbolizer));
92 
93  // Set up the instruction printer.
94  int AsmPrinterVariant = MAI->getAssemblerDialect();
95  std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
96  Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI));
97  if (!IP)
98  return nullptr;
99 
101  TT, DisInfo, TagType, GetOpInfo, SymbolLookUp, TheTarget, std::move(MAI),
102  std::move(MRI), std::move(STI), std::move(MII), std::move(Ctx),
103  std::move(DisAsm), std::move(IP));
104  if (!DC)
105  return nullptr;
106 
107  DC->setCPU(CPU);
108  return DC;
109 }
110 
112 LLVMCreateDisasmCPU(const char *TT, const char *CPU, void *DisInfo, int TagType,
113  LLVMOpInfoCallback GetOpInfo,
114  LLVMSymbolLookupCallback SymbolLookUp) {
115  return LLVMCreateDisasmCPUFeatures(TT, CPU, "", DisInfo, TagType, GetOpInfo,
116  SymbolLookUp);
117 }
118 
119 LLVMDisasmContextRef LLVMCreateDisasm(const char *TT, void *DisInfo,
120  int TagType, LLVMOpInfoCallback GetOpInfo,
121  LLVMSymbolLookupCallback SymbolLookUp) {
122  return LLVMCreateDisasmCPUFeatures(TT, "", "", DisInfo, TagType, GetOpInfo,
123  SymbolLookUp);
124 }
125 
126 //
127 // LLVMDisasmDispose() disposes of the disassembler specified by the context.
128 //
130  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
131  delete DC;
132 }
133 
134 /// Emits the comments that are stored in \p DC comment stream.
135 /// Each comment in the comment stream must end with a newline.
137  formatted_raw_ostream &FormattedOS) {
138  // Flush the stream before taking its content.
139  StringRef Comments = DC->CommentsToEmit.str();
140  // Get the default information for printing a comment.
141  const MCAsmInfo *MAI = DC->getAsmInfo();
142  StringRef CommentBegin = MAI->getCommentString();
143  unsigned CommentColumn = MAI->getCommentColumn();
144  bool IsFirst = true;
145  while (!Comments.empty()) {
146  if (!IsFirst)
147  FormattedOS << '\n';
148  // Emit a line of comments.
149  FormattedOS.PadToColumn(CommentColumn);
150  size_t Position = Comments.find('\n');
151  FormattedOS << CommentBegin << ' ' << Comments.substr(0, Position);
152  // Move after the newline character.
153  Comments = Comments.substr(Position+1);
154  IsFirst = false;
155  }
156  FormattedOS.flush();
157 
158  // Tell the comment stream that the vector changed underneath it.
159  DC->CommentsToEmit.clear();
160 }
161 
162 /// Gets latency information for \p Inst from the itinerary
163 /// scheduling model, based on \p DC information.
164 /// \return The maximum expected latency over all the operands or -1
165 /// if no information is available.
166 static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
167  const int NoInformationAvailable = -1;
168 
169  // Check if we have a CPU to get the itinerary information.
170  if (DC->getCPU().empty())
171  return NoInformationAvailable;
172 
173  // Get itinerary information.
174  const MCSubtargetInfo *STI = DC->getSubtargetInfo();
176  // Get the scheduling class of the requested instruction.
177  const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
178  unsigned SCClass = Desc.getSchedClass();
179 
180  int Latency = 0;
181  for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd;
182  ++OpIdx)
183  Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx));
184 
185  return Latency;
186 }
187 
188 /// Gets latency information for \p Inst, based on \p DC information.
189 /// \return The maximum expected latency over all the definitions or -1
190 /// if no information is available.
191 static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
192  // Try to compute scheduling information.
193  const MCSubtargetInfo *STI = DC->getSubtargetInfo();
194  const MCSchedModel SCModel = STI->getSchedModel();
195  const int NoInformationAvailable = -1;
196 
197  // Check if we have a scheduling model for instructions.
198  if (!SCModel.hasInstrSchedModel())
199  // Try to fall back to the itinerary model if the scheduling model doesn't
200  // have a scheduling table. Note the default does not have a table.
201  return getItineraryLatency(DC, Inst);
202 
203  // Get the scheduling class of the requested instruction.
204  const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
205  unsigned SCClass = Desc.getSchedClass();
206  const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass);
207  // Resolving the variant SchedClass requires an MI to pass to
208  // SubTargetInfo::resolveSchedClass.
209  if (!SCDesc || !SCDesc->isValid() || SCDesc->isVariant())
210  return NoInformationAvailable;
211 
212  // Compute output latency.
213  int16_t Latency = 0;
214  for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
215  DefIdx != DefEnd; ++DefIdx) {
216  // Lookup the definition's write latency in SubtargetInfo.
217  const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc,
218  DefIdx);
219  Latency = std::max(Latency, WLEntry->Cycles);
220  }
221 
222  return Latency;
223 }
224 
225 /// Emits latency information in DC->CommentStream for \p Inst, based
226 /// on the information available in \p DC.
227 static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
228  int Latency = getLatency(DC, Inst);
229 
230  // Report only interesting latencies.
231  if (Latency < 2)
232  return;
233 
234  DC->CommentStream << "Latency: " << Latency << '\n';
235 }
236 
237 //
238 // LLVMDisasmInstruction() disassembles a single instruction using the
239 // disassembler context specified in the parameter DC. The bytes of the
240 // instruction are specified in the parameter Bytes, and contains at least
241 // BytesSize number of bytes. The instruction is at the address specified by
242 // the PC parameter. If a valid instruction can be disassembled its string is
243 // returned indirectly in OutString which whos size is specified in the
244 // parameter OutStringSize. This function returns the number of bytes in the
245 // instruction or zero if there was no valid instruction. If this function
246 // returns zero the caller will have to pick how many bytes they want to step
247 // over by printing a .byte, .long etc. to continue.
248 //
249 size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes,
250  uint64_t BytesSize, uint64_t PC, char *OutString,
251  size_t OutStringSize){
252  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
253  // Wrap the pointer to the Bytes, BytesSize and PC in a MemoryObject.
254  ArrayRef<uint8_t> Data(Bytes, BytesSize);
255 
256  uint64_t Size;
257  MCInst Inst;
258  const MCDisassembler *DisAsm = DC->getDisAsm();
259  MCInstPrinter *IP = DC->getIP();
261  SmallVector<char, 64> InsnStr;
263  S = DisAsm->getInstruction(Inst, Size, Data, PC,
264  /*REMOVE*/ nulls(), Annotations);
265  switch (S) {
268  // FIXME: Do something different for soft failure modes?
269  return 0;
270 
272  StringRef AnnotationsStr = Annotations.str();
273 
274  SmallVector<char, 64> InsnStr;
275  raw_svector_ostream OS(InsnStr);
276  formatted_raw_ostream FormattedOS(OS);
277  IP->printInst(&Inst, FormattedOS, AnnotationsStr, *DC->getSubtargetInfo());
278 
280  emitLatency(DC, Inst);
281 
282  emitComments(DC, FormattedOS);
283 
284  assert(OutStringSize != 0 && "Output buffer cannot be zero size");
285  size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());
286  std::memcpy(OutString, InsnStr.data(), OutputSize);
287  OutString[OutputSize] = '\0'; // Terminate string.
288 
289  return Size;
290  }
291  }
292  llvm_unreachable("Invalid DecodeStatus!");
293 }
294 
295 //
296 // LLVMSetDisasmOptions() sets the disassembler's options. It returns 1 if it
297 // can set all the Options and 0 otherwise.
298 //
299 int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options){
300  if (Options & LLVMDisassembler_Option_UseMarkup){
301  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
302  MCInstPrinter *IP = DC->getIP();
303  IP->setUseMarkup(true);
304  DC->addOptions(LLVMDisassembler_Option_UseMarkup);
305  Options &= ~LLVMDisassembler_Option_UseMarkup;
306  }
308  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
309  MCInstPrinter *IP = DC->getIP();
310  IP->setPrintImmHex(true);
311  DC->addOptions(LLVMDisassembler_Option_PrintImmHex);
312  Options &= ~LLVMDisassembler_Option_PrintImmHex;
313  }
315  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
316  // Try to set up the new instruction printer.
317  const MCAsmInfo *MAI = DC->getAsmInfo();
318  const MCInstrInfo *MII = DC->getInstrInfo();
319  const MCRegisterInfo *MRI = DC->getRegisterInfo();
320  int AsmPrinterVariant = MAI->getAssemblerDialect();
321  AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
323  Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI);
324  if (IP) {
325  DC->setIP(IP);
326  DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
327  Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;
328  }
329  }
331  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
332  MCInstPrinter *IP = DC->getIP();
334  DC->addOptions(LLVMDisassembler_Option_SetInstrComments);
335  Options &= ~LLVMDisassembler_Option_SetInstrComments;
336  }
337  if (Options & LLVMDisassembler_Option_PrintLatency) {
338  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
339  DC->addOptions(LLVMDisassembler_Option_PrintLatency);
340  Options &= ~LLVMDisassembler_Option_PrintLatency;
341  }
342  return (Options == 0);
343 }
void setIP(MCInstPrinter *NewIP)
Definition: Disassembler.h:115
#define LLVMDisassembler_Option_SetInstrComments
Definition: Disassembler.h:82
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI)=0
Print the specified MCInst to the specified raw_ostream.
LLVMDisasmContextRef LLVMCreateDisasm(const char *TT, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName.
DecodeStatus
Ternary decode status.
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Superclass for all disassemblers.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:179
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
static void emitComments(LLVMDisasmContext *DC, formatted_raw_ostream &FormattedOS)
Emits the comments that are stored in DC comment stream.
void setPrintImmHex(bool Value)
Definition: MCInstPrinter.h:92
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:530
MCDisassembler * createMCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) const
#define LLVMDisassembler_Option_UseMarkup
Definition: Disassembler.h:76
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
Definition: MCSchedule.h:346
static const Target * lookupTarget(const std::string &Triple, std::string &Error)
lookupTarget - Lookup a target based on a target triple.
LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *TT, const char *CPU, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName and a specific CPU.
static ManagedStatic< DebugCounter > DC
MCInstPrinter * createMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) const
MCInstPrinter * getIP()
Definition: Disassembler.h:114
static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Emits latency information in DC->CommentStream for Inst, based on the information available in DC...
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:592
void * LLVMDisasmContextRef
An opaque reference to a disassembler context.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:140
Position
Position to insert a new instruction relative to an existing instruction.
const MCRegisterInfo * getRegisterInfo() const
Definition: Disassembler.h:112
StringRef str() const
Explicit conversion to StringRef.
Definition: SmallString.h:266
Context object for machine code objects.
Definition: MCContext.h:65
raw_svector_ostream CommentStream
Definition: Disassembler.h:83
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
Itinerary data supplied by a subtarget to be used by a target.
bool isValid() const
Definition: MCSchedule.h:127
static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst, based on DC information.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:601
unsigned const MachineRegisterInfo * MRI
unsigned getAssemblerDialect() const
Definition: MCAsmInfo.h:526
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:110
void setCommentStream(raw_ostream &OS)
Specify a stream to emit comments to.
Definition: MCInstPrinter.h:72
#define LLVMDisassembler_Option_PrintImmHex
Definition: Disassembler.h:78
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
const MCSubtargetInfo * getSubtargetInfo() const
Definition: Disassembler.h:113
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:299
StringRef getCommentString() const
Definition: MCAsmInfo.h:503
MCRegisterInfo * createMCRegInfo(StringRef TT) const
createMCRegInfo - Create a MCRegisterInfo implementation.
unsigned getNumOperands() const
Definition: MCInst.h:181
size_t size() const
Definition: SmallVector.h:52
static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst from the itinerary scheduling model, based on DC information...
const MCInstrInfo * getInstrInfo() const
Definition: Disassembler.h:111
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
Definition: MCSchedule.h:320
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:78
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:389
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
const MCAsmInfo * getAsmInfo() const
Definition: Disassembler.h:110
StringRef str()
Return a StringRef for the vector contents.
Definition: raw_ostream.h:555
const Target * getTarget() const
Definition: Disassembler.h:108
LLVMDisasmContextRef LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU, const char *Features, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName, a specific CPU and specific feature string.
MCAsmInfo * createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TheTriple) const
createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple.
Target - Wrapper for Target specific information.
bool isVariant() const
Definition: MCSchedule.h:130
void setUseMarkup(bool Value)
Definition: MCInstPrinter.h:86
size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes, uint64_t BytesSize, uint64_t PC, char *OutString, size_t OutStringSize)
Disassemble a single instruction using the disassembler context specified in the parameter DC...
int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options)
Set the disassembler&#39;s options.
MCSubtargetInfo * createMCSubtargetInfo(StringRef TheTriple, StringRef CPU, StringRef Features) const
createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
#define LLVMDisassembler_Option_AsmPrinterVariant
Definition: Disassembler.h:80
StringRef getCPU() const
Definition: Disassembler.h:118
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:39
pointer data()
Return a pointer to the vector&#39;s buffer, even if empty().
Definition: SmallVector.h:144
uint64_t getOptions() const
Definition: Disassembler.h:116
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
void LLVMDisasmDispose(LLVMDisasmContextRef DCR)
Dispose of a disassembler context.
Generic base class for all target subtargets.
MCSymbolizer * createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo) const
createMCSymbolizer - Create a target specific MCSymbolizer.
uint32_t Size
Definition: Profile.cpp:46
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getCommentColumn() const
This indicates the column (zero-based) at which asm comments should be printed.
Definition: MCAsmInfo.h:501
MCRelocationInfo * createMCRelocationInfo(StringRef TT, MCContext &Ctx) const
createMCRelocationInfo - Create a target specific MCRelocationInfo.
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
raw_ostream & nulls()
This returns a reference to a raw_ostream which simply discards output.
uint16_t NumWriteLatencyEntries
Definition: MCSchedule.h:123
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
void addOptions(uint64_t Options)
Definition: Disassembler.h:117
void setCPU(const char *CPU)
Definition: Disassembler.h:119
const std::string & getTripleName() const
Definition: Disassembler.h:101
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned getOpcode() const
Definition: MCInst.h:171
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &VStream, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
const MCDisassembler * getDisAsm() const
Definition: Disassembler.h:109
Annotations lets you mark points and ranges inside source code, for tests:
Definition: Annotations.h:46
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
SmallString< 128 > CommentsToEmit
Definition: Disassembler.h:82
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.
#define LLVMDisassembler_Option_PrintLatency
Definition: Disassembler.h:84