LLVM 17.0.0git
Disassembler.cpp
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1//===-- lib/MC/Disassembler.cpp - Disassembler Public C Interface ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "Disassembler.h"
10#include "llvm-c/Disassembler.h"
11#include "llvm/ADT/ArrayRef.h"
13#include "llvm/ADT/Triple.h"
14#include "llvm/MC/MCAsmInfo.h"
15#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCSchedule.h"
32#include <cassert>
33#include <cstring>
34
35using namespace llvm;
36
37// LLVMCreateDisasm() creates a disassembler for the TripleName. Symbolic
38// disassembly is supported by passing a block of information in the DisInfo
39// parameter and specifying the TagType and callback functions as described in
40// the header llvm-c/Disassembler.h . The pointer to the block and the
41// functions can all be passed as NULL. If successful, this returns a
42// disassembler context. If not, it returns NULL.
43//
45LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU,
46 const char *Features, void *DisInfo, int TagType,
47 LLVMOpInfoCallback GetOpInfo,
48 LLVMSymbolLookupCallback SymbolLookUp) {
49 // Get the target.
50 std::string Error;
51 const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
52 if (!TheTarget)
53 return nullptr;
54
55 std::unique_ptr<const MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TT));
56 if (!MRI)
57 return nullptr;
58
59 MCTargetOptions MCOptions;
60 // Get the assembler info needed to setup the MCContext.
61 std::unique_ptr<const MCAsmInfo> MAI(
62 TheTarget->createMCAsmInfo(*MRI, TT, MCOptions));
63 if (!MAI)
64 return nullptr;
65
66 std::unique_ptr<const MCInstrInfo> MII(TheTarget->createMCInstrInfo());
67 if (!MII)
68 return nullptr;
69
70 std::unique_ptr<const MCSubtargetInfo> STI(
71 TheTarget->createMCSubtargetInfo(TT, CPU, Features));
72 if (!STI)
73 return nullptr;
74
75 // Set up the MCContext for creating symbols and MCExpr's.
76 std::unique_ptr<MCContext> Ctx(
77 new MCContext(Triple(TT), MAI.get(), MRI.get(), STI.get()));
78 if (!Ctx)
79 return nullptr;
80
81 // Set up disassembler.
82 std::unique_ptr<MCDisassembler> DisAsm(
83 TheTarget->createMCDisassembler(*STI, *Ctx));
84 if (!DisAsm)
85 return nullptr;
86
87 std::unique_ptr<MCRelocationInfo> RelInfo(
88 TheTarget->createMCRelocationInfo(TT, *Ctx));
89 if (!RelInfo)
90 return nullptr;
91
92 std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer(
93 TT, GetOpInfo, SymbolLookUp, DisInfo, Ctx.get(), std::move(RelInfo)));
94 DisAsm->setSymbolizer(std::move(Symbolizer));
95
96 // Set up the instruction printer.
97 int AsmPrinterVariant = MAI->getAssemblerDialect();
98 std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
99 Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI));
100 if (!IP)
101 return nullptr;
102
104 TT, DisInfo, TagType, GetOpInfo, SymbolLookUp, TheTarget, std::move(MAI),
105 std::move(MRI), std::move(STI), std::move(MII), std::move(Ctx),
106 std::move(DisAsm), std::move(IP));
107 if (!DC)
108 return nullptr;
109
110 DC->setCPU(CPU);
111 return DC;
112}
113
115LLVMCreateDisasmCPU(const char *TT, const char *CPU, void *DisInfo, int TagType,
116 LLVMOpInfoCallback GetOpInfo,
117 LLVMSymbolLookupCallback SymbolLookUp) {
118 return LLVMCreateDisasmCPUFeatures(TT, CPU, "", DisInfo, TagType, GetOpInfo,
119 SymbolLookUp);
120}
121
122LLVMDisasmContextRef LLVMCreateDisasm(const char *TT, void *DisInfo,
123 int TagType, LLVMOpInfoCallback GetOpInfo,
124 LLVMSymbolLookupCallback SymbolLookUp) {
125 return LLVMCreateDisasmCPUFeatures(TT, "", "", DisInfo, TagType, GetOpInfo,
126 SymbolLookUp);
127}
128
129//
130// LLVMDisasmDispose() disposes of the disassembler specified by the context.
131//
133 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
134 delete DC;
135}
136
137/// Emits the comments that are stored in \p DC comment stream.
138/// Each comment in the comment stream must end with a newline.
140 formatted_raw_ostream &FormattedOS) {
141 // Flush the stream before taking its content.
142 StringRef Comments = DC->CommentsToEmit.str();
143 // Get the default information for printing a comment.
144 const MCAsmInfo *MAI = DC->getAsmInfo();
145 StringRef CommentBegin = MAI->getCommentString();
146 unsigned CommentColumn = MAI->getCommentColumn();
147 bool IsFirst = true;
148 while (!Comments.empty()) {
149 if (!IsFirst)
150 FormattedOS << '\n';
151 // Emit a line of comments.
152 FormattedOS.PadToColumn(CommentColumn);
153 size_t Position = Comments.find('\n');
154 FormattedOS << CommentBegin << ' ' << Comments.substr(0, Position);
155 // Move after the newline character.
156 Comments = Comments.substr(Position+1);
157 IsFirst = false;
158 }
159 FormattedOS.flush();
160
161 // Tell the comment stream that the vector changed underneath it.
162 DC->CommentsToEmit.clear();
163}
164
165/// Gets latency information for \p Inst from the itinerary
166/// scheduling model, based on \p DC information.
167/// \return The maximum expected latency over all the operands or -1
168/// if no information is available.
169static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
170 const int NoInformationAvailable = -1;
171
172 // Check if we have a CPU to get the itinerary information.
173 if (DC->getCPU().empty())
174 return NoInformationAvailable;
175
176 // Get itinerary information.
177 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
179 // Get the scheduling class of the requested instruction.
180 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
181 unsigned SCClass = Desc.getSchedClass();
182
183 int Latency = 0;
184 for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd;
185 ++OpIdx)
186 Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx));
187
188 return Latency;
189}
190
191/// Gets latency information for \p Inst, based on \p DC information.
192/// \return The maximum expected latency over all the definitions or -1
193/// if no information is available.
194static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
195 // Try to compute scheduling information.
196 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
197 const MCSchedModel SCModel = STI->getSchedModel();
198 const int NoInformationAvailable = -1;
199
200 // Check if we have a scheduling model for instructions.
201 if (!SCModel.hasInstrSchedModel())
202 // Try to fall back to the itinerary model if the scheduling model doesn't
203 // have a scheduling table. Note the default does not have a table.
204 return getItineraryLatency(DC, Inst);
205
206 // Get the scheduling class of the requested instruction.
207 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
208 unsigned SCClass = Desc.getSchedClass();
209 const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass);
210 // Resolving the variant SchedClass requires an MI to pass to
211 // SubTargetInfo::resolveSchedClass.
212 if (!SCDesc || !SCDesc->isValid() || SCDesc->isVariant())
213 return NoInformationAvailable;
214
215 // Compute output latency.
216 int16_t Latency = 0;
217 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
218 DefIdx != DefEnd; ++DefIdx) {
219 // Lookup the definition's write latency in SubtargetInfo.
220 const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc,
221 DefIdx);
222 Latency = std::max(Latency, WLEntry->Cycles);
223 }
224
225 return Latency;
226}
227
228/// Emits latency information in DC->CommentStream for \p Inst, based
229/// on the information available in \p DC.
230static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
231 int Latency = getLatency(DC, Inst);
232
233 // Report only interesting latencies.
234 if (Latency < 2)
235 return;
236
237 DC->CommentStream << "Latency: " << Latency << '\n';
238}
239
240//
241// LLVMDisasmInstruction() disassembles a single instruction using the
242// disassembler context specified in the parameter DC. The bytes of the
243// instruction are specified in the parameter Bytes, and contains at least
244// BytesSize number of bytes. The instruction is at the address specified by
245// the PC parameter. If a valid instruction can be disassembled its string is
246// returned indirectly in OutString which whos size is specified in the
247// parameter OutStringSize. This function returns the number of bytes in the
248// instruction or zero if there was no valid instruction. If this function
249// returns zero the caller will have to pick how many bytes they want to step
250// over by printing a .byte, .long etc. to continue.
251//
253 uint64_t BytesSize, uint64_t PC, char *OutString,
254 size_t OutStringSize){
255 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
256 // Wrap the pointer to the Bytes, BytesSize and PC in a MemoryObject.
257 ArrayRef<uint8_t> Data(Bytes, BytesSize);
258
260 MCInst Inst;
261 const MCDisassembler *DisAsm = DC->getDisAsm();
262 MCInstPrinter *IP = DC->getIP();
264 SmallVector<char, 64> InsnStr;
266 S = DisAsm->getInstruction(Inst, Size, Data, PC, Annotations);
267 switch (S) {
270 // FIXME: Do something different for soft failure modes?
271 return 0;
272
274 StringRef AnnotationsStr = Annotations.str();
275
276 SmallVector<char, 64> InsnStr;
277 raw_svector_ostream OS(InsnStr);
278 formatted_raw_ostream FormattedOS(OS);
279 IP->printInst(&Inst, PC, AnnotationsStr, *DC->getSubtargetInfo(),
280 FormattedOS);
281
283 emitLatency(DC, Inst);
284
285 emitComments(DC, FormattedOS);
286
287 assert(OutStringSize != 0 && "Output buffer cannot be zero size");
288 size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());
289 std::memcpy(OutString, InsnStr.data(), OutputSize);
290 OutString[OutputSize] = '\0'; // Terminate string.
291
292 return Size;
293 }
294 }
295 llvm_unreachable("Invalid DecodeStatus!");
296}
297
298//
299// LLVMSetDisasmOptions() sets the disassembler's options. It returns 1 if it
300// can set all the Options and 0 otherwise.
301//
304 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
305 MCInstPrinter *IP = DC->getIP();
306 IP->setUseMarkup(true);
308 Options &= ~LLVMDisassembler_Option_UseMarkup;
309 }
311 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
312 MCInstPrinter *IP = DC->getIP();
313 IP->setPrintImmHex(true);
315 Options &= ~LLVMDisassembler_Option_PrintImmHex;
316 }
318 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
319 // Try to set up the new instruction printer.
320 const MCAsmInfo *MAI = DC->getAsmInfo();
321 const MCInstrInfo *MII = DC->getInstrInfo();
322 const MCRegisterInfo *MRI = DC->getRegisterInfo();
323 int AsmPrinterVariant = MAI->getAssemblerDialect();
324 AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
326 Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI);
327 if (IP) {
328 DC->setIP(IP);
330 Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;
331 }
332 }
334 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
335 MCInstPrinter *IP = DC->getIP();
338 Options &= ~LLVMDisassembler_Option_SetInstrComments;
339 }
341 LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
343 Options &= ~LLVMDisassembler_Option_PrintLatency;
344 }
345 return (Options == 0);
346}
unsigned const MachineRegisterInfo * MRI
This header is deprecated in favour of llvm/TargetParser/Triple.h.
static void emitComments(LLVMDisasmContext *DC, formatted_raw_ostream &FormattedOS)
Emits the comments that are stored in DC comment stream.
static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst from the itinerary scheduling model, based on DC information.
static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst, based on DC information.
static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Emits latency information in DC->CommentStream for Inst, based on the information available in DC.
uint64_t Size
static LVOptions Options
Definition: LVOptions.cpp:25
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
Annotations lets you mark points and ranges inside source code, for tests:
Definition: Annotations.h:53
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Lightweight error class with error context and mandatory checking.
Definition: Error.h:156
Itinerary data supplied by a subtarget to be used by a target.
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
const MCDisassembler * getDisAsm() const
Definition: Disassembler.h:109
void setCPU(const char *CPU)
Definition: Disassembler.h:119
void addOptions(uint64_t Options)
Definition: Disassembler.h:117
raw_svector_ostream CommentStream
Definition: Disassembler.h:83
void setIP(MCInstPrinter *NewIP)
Definition: Disassembler.h:115
const MCSubtargetInfo * getSubtargetInfo() const
Definition: Disassembler.h:113
const MCAsmInfo * getAsmInfo() const
Definition: Disassembler.h:110
uint64_t getOptions() const
Definition: Disassembler.h:116
const MCRegisterInfo * getRegisterInfo() const
Definition: Disassembler.h:112
SmallString< 128 > CommentsToEmit
Definition: Disassembler.h:82
MCInstPrinter * getIP()
Definition: Disassembler.h:114
StringRef getCPU() const
Definition: Disassembler.h:118
const MCInstrInfo * getInstrInfo() const
Definition: Disassembler.h:111
const Target * getTarget() const
Definition: Disassembler.h:108
const std::string & getTripleName() const
Definition: Disassembler.h:101
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
unsigned getAssemblerDialect() const
Definition: MCAsmInfo.h:686
StringRef getCommentString() const
Definition: MCAsmInfo.h:655
unsigned getCommentColumn() const
This indicates the column (zero-based) at which asm comments should be printed.
Definition: MCAsmInfo.h:653
Context object for machine code objects.
Definition: MCContext.h:76
Superclass for all disassemblers.
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:44
void setCommentStream(raw_ostream &OS)
Specify a stream to emit comments to.
Definition: MCInstPrinter.h:93
void setPrintImmHex(bool Value)
void setUseMarkup(bool Value)
virtual void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS)=0
Print the specified MCInst to the specified raw_ostream.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getNumOperands() const
Definition: MCInst.h:208
unsigned getOpcode() const
Definition: MCInst.h:198
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:596
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
StringRef str() const
Explicit conversion to StringRef.
Definition: SmallString.h:261
size_t size() const
Definition: SmallVector.h:91
pointer data()
Return a pointer to the vector's buffer, even if empty().
Definition: SmallVector.h:289
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:559
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:295
Target - Wrapper for Target specific information.
MCSubtargetInfo * createMCSubtargetInfo(StringRef TheTriple, StringRef CPU, StringRef Features) const
createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
MCSymbolizer * createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo) const
createMCSymbolizer - Create a target specific MCSymbolizer.
MCRelocationInfo * createMCRelocationInfo(StringRef TT, MCContext &Ctx) const
createMCRelocationInfo - Create a target specific MCRelocationInfo.
MCRegisterInfo * createMCRegInfo(StringRef TT) const
createMCRegInfo - Create a MCRegisterInfo implementation.
MCDisassembler * createMCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) const
MCAsmInfo * createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TheTriple, const MCTargetOptions &Options) const
createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple.
MCInstPrinter * createMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) const
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:672
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
LLVMDisasmContextRef LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU, const char *Features, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName, a specific CPU and specific feature string.
void LLVMDisasmDispose(LLVMDisasmContextRef DCR)
Dispose of a disassembler context.
#define LLVMDisassembler_Option_PrintImmHex
Definition: Disassembler.h:77
#define LLVMDisassembler_Option_UseMarkup
Definition: Disassembler.h:75
size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes, uint64_t BytesSize, uint64_t PC, char *OutString, size_t OutStringSize)
Disassemble a single instruction using the disassembler context specified in the parameter DC.
#define LLVMDisassembler_Option_PrintLatency
Definition: Disassembler.h:83
#define LLVMDisassembler_Option_SetInstrComments
Definition: Disassembler.h:81
LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *TT, const char *CPU, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName and a specific CPU.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
LLVMDisasmContextRef LLVMCreateDisasm(const char *TT, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName.
int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options)
Set the disassembler's options.
#define LLVMDisassembler_Option_AsmPrinterVariant
Definition: Disassembler.h:79
void * LLVMDisasmContextRef
An opaque reference to a disassembler context.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Definition: MCSchedule.h:109
bool isValid() const
Definition: MCSchedule.h:127
bool isVariant() const
Definition: MCSchedule.h:130
uint16_t NumWriteLatencyEntries
Definition: MCSchedule.h:123
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
Definition: MCSchedule.h:346
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
Definition: MCSchedule.h:320
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:77
static const Target * lookupTarget(const std::string &Triple, std::string &Error)
lookupTarget - Lookup a target based on a target triple.