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46 const char *Features,
void *DisInfo,
int TagType,
61 std::unique_ptr<const MCAsmInfo> MAI(
70 std::unique_ptr<const MCSubtargetInfo> STI(
76 std::unique_ptr<MCContext> Ctx(
82 std::unique_ptr<MCDisassembler> DisAsm(
87 std::unique_ptr<MCRelocationInfo> RelInfo(
93 TT, GetOpInfo, SymbolLookUp, DisInfo, Ctx.get(),
std::move(RelInfo)));
94 DisAsm->setSymbolizer(
std::move(Symbolizer));
97 int AsmPrinterVariant = MAI->getAssemblerDialect();
99 Triple(TT), AsmPrinterVariant, *MAI, *MII, *
MRI));
104 TT, DisInfo, TagType, GetOpInfo, SymbolLookUp, TheTarget,
std::move(MAI),
148 while (!Comments.
empty()) {
153 size_t Position = Comments.
find(
'\n');
154 FormattedOS << CommentBegin <<
' ' << Comments.
substr(0, Position);
156 Comments = Comments.
substr(Position+1);
162 DC->CommentsToEmit.clear();
170 const int NoInformationAvailable = -1;
173 if (
DC->getCPU().empty())
174 return NoInformationAvailable;
184 for (
unsigned OpIdx = 0, OpIdxEnd = Inst.
getNumOperands(); OpIdx != OpIdxEnd;
198 const int NoInformationAvailable = -1;
213 return NoInformationAvailable;
218 DefIdx != DefEnd; ++DefIdx) {
237 DC->CommentStream <<
"Latency: " <<
Latency <<
'\n';
254 size_t OutStringSize){
279 IP->printInst(&Inst, PC, AnnotationsStr, *
DC->getSubtargetInfo(),
287 assert(OutStringSize != 0 &&
"Output buffer cannot be zero size");
288 size_t OutputSize =
std::min(OutStringSize-1, InsnStr.size());
289 std::memcpy(OutString, InsnStr.data(), OutputSize);
290 OutString[OutputSize] =
'\0';
306 IP->setUseMarkup(
true);
313 IP->setPrintImmHex(
true);
324 AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
326 Triple(
DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *
MRI);
336 IP->setCommentStream(
DC->CommentStream);
This is an optimization pass for GlobalISel generic memory operations.
StringRef getCommentString() const
uint16_t NumWriteLatencyEntries
size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes, uint64_t BytesSize, uint64_t PC, char *OutString, size_t OutStringSize)
Disassemble a single instruction using the disassembler context specified in the parameter DC.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Context object for machine code objects.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Target - Wrapper for Target specific information.
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
void LLVMDisasmDispose(LLVMDisasmContextRef DCR)
Dispose of a disassembler context.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
MCAsmInfo * createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TheTriple, const MCTargetOptions &Options) const
createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple.
LLVMDisasmContextRef LLVMCreateDisasm(const char *TT, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName.
void * LLVMDisasmContextRef
An opaque reference to a disassembler context.
static void emitComments(LLVMDisasmContext *DC, formatted_raw_ostream &FormattedOS)
Emits the comments that are stored in DC comment stream.
Triple - Helper class for working with autoconf configuration names.
MCRelocationInfo * createMCRelocationInfo(StringRef TT, MCContext &Ctx) const
createMCRelocationInfo - Create a target specific MCRelocationInfo.
#define LLVMDisassembler_Option_PrintImmHex
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
unsigned getAssemblerDialect() const
Instances of this class represent a single low-level machine instruction.
static const Target * lookupTarget(const std::string &Triple, std::string &Error)
lookupTarget - Lookup a target based on a target triple.
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
unsigned getNumOperands() const
#define LLVMDisassembler_Option_UseMarkup
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
Annotations lets you mark points and ranges inside source code, for tests:
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
MCRegisterInfo * createMCRegInfo(StringRef TT) const
createMCRegInfo - Create a MCRegisterInfo implementation.
#define LLVMDisassembler_Option_PrintLatency
const typedef char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
#define LLVMDisassembler_Option_SetInstrComments
Summarize the scheduling resources required for an instruction of a particular scheduling class.
static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst, based on DC information.
LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *TT, const char *CPU, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName and a specific CPU.
static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst from the itinerary scheduling model, based on DC information.
Describe properties that are true of each instruction in the target description file.
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
DecodeStatus
Ternary decode status.
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
#define LLVMDisassembler_Option_AsmPrinterVariant
Specify the latency in cpu cycles for a particular scheduling class and def index.
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Superclass for all disassemblers.
MCSymbolizer * createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo) const
createMCSymbolizer - Create a target specific MCSymbolizer.
MCDisassembler * createMCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
<%struct.s * > cast struct s *S to sbyte *< sbyte * > sbyte uint cast struct s *agg result to sbyte *< sbyte * > sbyte uint cast struct s *memtmp to sbyte *< sbyte * > sbyte uint ret void llc ends up issuing two memcpy or custom lower memcpy(of small size) to be ldmia/stmia. I think option 2 is better but the current register allocator cannot allocate a chunk of registers at a time. A feasible temporary solution is to use specific physical registers at the lowering time for small(<
static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Emits latency information in DC->CommentStream for Inst, based on the information available in DC.
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static ManagedStatic< DebugCounter > DC
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
MCSubtargetInfo * createMCSubtargetInfo(StringRef TheTriple, StringRef CPU, StringRef Features) const
createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
Interface to description of machine instruction set.
MCInstPrinter * createMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) const
Lightweight error class with error context and mandatory checking.
unsigned getOpcode() const
Machine model for scheduling, bundling, and heuristics.
LLVMDisasmContextRef LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU, const char *Features, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName, a specific CPU and specific feature string.
A raw_ostream that writes to an SmallVector or SmallString.
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
unsigned getCommentColumn() const
This indicates the column (zero-based) at which asm comments should be printed.
int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options)
Set the disassembler's options.
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
Generic base class for all target subtargets.
Itinerary data supplied by a subtarget to be used by a target.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.