LLVM  16.0.0git
DispatchStage.cpp
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1 //===--------------------- DispatchStage.cpp --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file models the dispatch component of an instruction pipeline.
11 ///
12 /// The DispatchStage is responsible for updating instruction dependencies
13 /// and communicating to the simulated instruction scheduler that an instruction
14 /// is ready to be scheduled for execution.
15 ///
16 //===----------------------------------------------------------------------===//
17 
21 #include "llvm/Support/Debug.h"
22 
23 #define DEBUG_TYPE "llvm-mca"
24 
25 namespace llvm {
26 namespace mca {
27 
29  const MCRegisterInfo &MRI,
30  unsigned MaxDispatchWidth, RetireControlUnit &R,
31  RegisterFile &F)
32  : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
33  CarryOver(0U), STI(Subtarget), RCU(R), PRF(F) {
34  if (!DispatchWidth)
35  DispatchWidth = Subtarget.getSchedModel().IssueWidth;
36 }
37 
38 void DispatchStage::notifyInstructionDispatched(const InstRef &IR,
39  ArrayRef<unsigned> UsedRegs,
40  unsigned UOps) const {
41  LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: #" << IR << '\n');
42  notifyEvent<HWInstructionEvent>(
43  HWInstructionDispatchedEvent(IR, UsedRegs, UOps));
44 }
45 
46 bool DispatchStage::checkPRF(const InstRef &IR) const {
48  for (const WriteState &RegDef : IR.getInstruction()->getDefs())
49  RegDefs.emplace_back(RegDef.getRegisterID());
50 
51  const unsigned RegisterMask = PRF.isAvailable(RegDefs);
52  // A mask with all zeroes means: register files are available.
53  if (RegisterMask) {
54  notifyEvent<HWStallEvent>(
55  HWStallEvent(HWStallEvent::RegisterFileStall, IR));
56  return false;
57  }
58 
59  return true;
60 }
61 
62 bool DispatchStage::checkRCU(const InstRef &IR) const {
63  const unsigned NumMicroOps = IR.getInstruction()->getNumMicroOps();
64  if (RCU.isAvailable(NumMicroOps))
65  return true;
66  notifyEvent<HWStallEvent>(
68  return false;
69 }
70 
71 bool DispatchStage::canDispatch(const InstRef &IR) const {
72  bool CanDispatch = checkRCU(IR);
73  CanDispatch &= checkPRF(IR);
74  CanDispatch &= checkNextStage(IR);
75  return CanDispatch;
76 }
77 
78 Error DispatchStage::dispatch(InstRef IR) {
79  assert(!CarryOver && "Cannot dispatch another instruction!");
80  Instruction &IS = *IR.getInstruction();
81  const unsigned NumMicroOps = IS.getNumMicroOps();
82  if (NumMicroOps > DispatchWidth) {
83  assert(AvailableEntries == DispatchWidth);
84  AvailableEntries = 0;
85  CarryOver = NumMicroOps - DispatchWidth;
86  CarriedOver = IR;
87  } else {
88  assert(AvailableEntries >= NumMicroOps);
89  AvailableEntries -= NumMicroOps;
90  }
91 
92  // Check if this instructions ends the dispatch group.
93  if (IS.getEndGroup())
94  AvailableEntries = 0;
95 
96  // Check if this is an optimizable reg-reg move or an XCHG-like instruction.
97  if (IS.isOptimizableMove())
98  if (PRF.tryEliminateMoveOrSwap(IS.getDefs(), IS.getUses()))
99  IS.setEliminated();
100 
101  // A dependency-breaking instruction doesn't have to wait on the register
102  // input operands, and it is often optimized at register renaming stage.
103  // Update RAW dependencies if this instruction is not a dependency-breaking
104  // instruction. A dependency-breaking instruction is a zero-latency
105  // instruction that doesn't consume hardware resources.
106  // An example of dependency-breaking instruction on X86 is a zero-idiom XOR.
107  //
108  // We also don't update data dependencies for instructions that have been
109  // eliminated at register renaming stage.
110  if (!IS.isEliminated()) {
111  for (ReadState &RS : IS.getUses())
112  PRF.addRegisterRead(RS, STI);
113  }
114 
115  // By default, a dependency-breaking zero-idiom is expected to be optimized
116  // at register renaming stage. That means, no physical register is allocated
117  // to the instruction.
118  SmallVector<unsigned, 4> RegisterFiles(PRF.getNumRegisterFiles());
119  for (WriteState &WS : IS.getDefs())
120  PRF.addRegisterWrite(WriteRef(IR.getSourceIndex(), &WS), RegisterFiles);
121 
122  // Reserve entries in the reorder buffer.
123  unsigned RCUTokenID = RCU.dispatch(IR);
124  // Notify the instruction that it has been dispatched.
125  IS.dispatch(RCUTokenID);
126 
127  // Notify listeners of the "instruction dispatched" event,
128  // and move IR to the next stage.
129  notifyInstructionDispatched(IR, RegisterFiles,
130  std::min(DispatchWidth, NumMicroOps));
131  return moveToTheNextStage(IR);
132 }
133 
135  // The retire stage is responsible for calling method `cycleStart`
136  // on the PRF.
137  if (!CarryOver) {
138  AvailableEntries = DispatchWidth;
139  return ErrorSuccess();
140  }
141 
142  AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
143  unsigned DispatchedOpcodes = DispatchWidth - AvailableEntries;
144  CarryOver -= DispatchedOpcodes;
145  assert(CarriedOver && "Invalid dispatched instruction");
146 
147  SmallVector<unsigned, 8> RegisterFiles(PRF.getNumRegisterFiles(), 0U);
148  notifyInstructionDispatched(CarriedOver, RegisterFiles, DispatchedOpcodes);
149  if (!CarryOver)
150  CarriedOver = InstRef();
151  return ErrorSuccess();
152 }
153 
155  // Conservatively bail out if there are no available dispatch entries.
156  if (!AvailableEntries)
157  return false;
158 
159  const Instruction &Inst = *IR.getInstruction();
160  unsigned NumMicroOps = Inst.getNumMicroOps();
161  unsigned Required = std::min(NumMicroOps, DispatchWidth);
162  if (Required > AvailableEntries)
163  return false;
164 
165  if (Inst.getBeginGroup() && AvailableEntries != DispatchWidth)
166  return false;
167 
168  // The dispatch logic doesn't internally buffer instructions. It only accepts
169  // instructions that can be successfully moved to the next stage during this
170  // same cycle.
171  return canDispatch(IR);
172 }
173 
175  assert(canDispatch(IR) && "Cannot dispatch another instruction!");
176  return dispatch(IR);
177 }
178 
179 #ifndef NDEBUG
180 void DispatchStage::dump() const {
181  PRF.dump();
182  RCU.dump();
183 }
184 #endif
185 } // namespace mca
186 } // namespace llvm
llvm::mca::DispatchStage::dump
void dump() const
Definition: DispatchStage.cpp:180
llvm::mca::DispatchStage::execute
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
Definition: DispatchStage.cpp:174
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This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
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@ Error
Definition: LLToken.h:21
llvm::mca::RegisterFile::tryEliminateMoveOrSwap
bool tryEliminateMoveOrSwap(MutableArrayRef< WriteState > Writes, MutableArrayRef< ReadState > Reads)
Definition: RegisterFile.cpp:426
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const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Definition: MCSubtargetInfo.h:163
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This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1182
llvm::mca::RetireControlUnit
This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO back...
Definition: RetireControlUnit.h:36
llvm::mca::HWStallEvent::RegisterFileStall
@ RegisterFileStall
Definition: HWEventListener.h:111
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An instruction propagated through the simulated instruction pipeline.
Definition: Instruction.h:600
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#define LLVM_DEBUG(X)
Definition: Debug.h:101
F
#define F(x, y, z)
Definition: MD5.cpp:55
DispatchStage.h
llvm::mca::RegisterFile::getNumRegisterFiles
unsigned getNumRegisterFiles() const
Definition: RegisterFile.h:293
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::mca::DispatchStage::DispatchStage
DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI, unsigned MaxDispatchWidth, RetireControlUnit &R, RegisterFile &F)
Definition: DispatchStage.cpp:28
llvm::mca::DispatchStage::cycleStart
Error cycleStart() override
Called once at the start of each cycle.
Definition: DispatchStage.cpp:134
llvm::mca::RegisterFile::isAvailable
unsigned isAvailable(ArrayRef< MCPhysReg > Regs) const
Definition: RegisterFile.cpp:660
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void dump() const
Definition: RetireControlUnit.cpp:96
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Definition: CommandLine.h:117
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Definition: Lint.cpp:746
llvm::mca::HWStallEvent::RetireControlUnitStall
@ RetireControlUnitStall
Definition: HWEventListener.h:112
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unsigned IssueWidth
Definition: MCSchedule.h:256
llvm::ErrorSuccess
Subclass of Error for the sole purpose of identifying the success path in the type system.
Definition: Error.h:327
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Scheduler.h
llvm::mca::RetireControlUnit::dispatch
unsigned dispatch(const InstRef &IS)
Definition: RetireControlUnit.cpp:43
llvm::mca::InstRef
An InstRef contains both a SourceMgr index and Instruction pair.
Definition: Instruction.h:720
llvm::mca::Stage::checkNextStage
bool checkNextStage(const InstRef &IR) const
Definition: Stage.h:65
llvm::mca::InstructionBase::getNumMicroOps
unsigned getNumMicroOps() const
Definition: Instruction.h:542
llvm::ArrayRef< unsigned >
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Definition: FileCheck.cpp:357
llvm::mca::InstructionBase::getBeginGroup
bool getBeginGroup() const
Definition: Instruction.h:591
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::mca::RegisterFile::addRegisterRead
void addRegisterRead(ReadState &RS, const MCSubtargetInfo &STI) const
Definition: RegisterFile.cpp:618
llvm::mca::RegisterFile
Manages hardware register files, and tracks register definitions for register renaming purposes.
Definition: RegisterFile.h:83
HWEventListener.h
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::mca::RegisterFile::addRegisterWrite
void addRegisterWrite(WriteRef Write, MutableArrayRef< unsigned > UsedPhysRegs)
Definition: RegisterFile.cpp:228
llvm::ISD::RegisterMask
@ RegisterMask
Definition: ISDOpcodes.h:75
llvm::mca::Stage::moveToTheNextStage
Error moveToTheNextStage(InstRef &IR)
Called when an instruction is ready to move the next pipeline stage.
Definition: Stage.h:73
llvm::mca::RetireControlUnit::isAvailable
bool isAvailable(unsigned Quantity=1) const
Definition: RetireControlUnit.h:84
llvm::mca::DispatchStage::isAvailable
bool isAvailable(const InstRef &IR) const override
Returns true if it can execute IR during this cycle.
Definition: DispatchStage.cpp:154
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Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
Debug.h
llvm::mca::RegisterFile::dump
void dump() const
Definition: RegisterFile.cpp:717
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reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:924
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Definition: HWEventListener.h:73