23 #define DEBUG_TYPE "llvm-mca"
32 : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
33 CarryOver(0U), STI(Subtarget), RCU(R), PRF(
F) {
38 void DispatchStage::notifyInstructionDispatched(
const InstRef &
IR,
40 unsigned UOps)
const {
42 notifyEvent<HWInstructionEvent>(
46 bool DispatchStage::checkPRF(
const InstRef &
IR)
const {
48 for (
const WriteState &RegDef :
IR.getInstruction()->getDefs())
54 notifyEvent<HWStallEvent>(
62 bool DispatchStage::checkRCU(
const InstRef &
IR)
const {
63 const unsigned NumMicroOps =
IR.getInstruction()->getNumMicroOps();
66 notifyEvent<HWStallEvent>(
71 bool DispatchStage::canDispatch(
const InstRef &
IR)
const {
72 bool CanDispatch = checkRCU(
IR);
73 CanDispatch &= checkPRF(
IR);
78 Error DispatchStage::dispatch(InstRef
IR) {
79 assert(!CarryOver &&
"Cannot dispatch another instruction!");
80 Instruction &IS = *
IR.getInstruction();
81 const unsigned NumMicroOps = IS.getNumMicroOps();
82 if (NumMicroOps > DispatchWidth) {
83 assert(AvailableEntries == DispatchWidth);
85 CarryOver = NumMicroOps - DispatchWidth;
88 assert(AvailableEntries >= NumMicroOps);
89 AvailableEntries -= NumMicroOps;
97 if (IS.isOptimizableMove())
110 if (!IS.isEliminated()) {
111 for (ReadState &RS : IS.getUses())
119 for (WriteState &WS : IS.getDefs())
125 IS.dispatch(RCUTokenID);
129 notifyInstructionDispatched(
IR, RegisterFiles,
130 std::min(DispatchWidth, NumMicroOps));
138 AvailableEntries = DispatchWidth;
142 AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
143 unsigned DispatchedOpcodes = DispatchWidth - AvailableEntries;
144 CarryOver -= DispatchedOpcodes;
145 assert(CarriedOver &&
"Invalid dispatched instruction");
148 notifyInstructionDispatched(CarriedOver, RegisterFiles, DispatchedOpcodes);
156 if (!AvailableEntries)
165 if (Inst.
getBeginGroup() && AvailableEntries != DispatchWidth)
171 return canDispatch(
IR);
175 assert(canDispatch(
IR) &&
"Cannot dispatch another instruction!");