LLVM  13.0.0git
HWEventListener.h
Go to the documentation of this file.
1 //===----------------------- HWEventListener.h ------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file defines the main interface for hardware event listeners.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MCA_HWEVENTLISTENER_H
15 #define LLVM_MCA_HWEVENTLISTENER_H
16 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/MCA/Instruction.h"
19 #include "llvm/MCA/Support.h"
20 
21 namespace llvm {
22 namespace mca {
23 
24 // An HWInstructionEvent represents state changes of instructions that
25 // listeners might be interested in. Listeners can choose to ignore any event
26 // they are not interested in.
28 public:
29  // This is the list of event types that are shared by all targets, that
30  // generic subtarget-agnostic classes (e.g., Pipeline, HWInstructionEvent,
31  // ...) and generic Views can manipulate.
32  // Subtargets are free to define additional event types, that are goin to be
33  // handled by generic components as opaque values, but can still be
34  // emitted by subtarget-specific pipeline stages (e.g., ExecuteStage,
35  // DispatchStage, ...) and interpreted by subtarget-specific EventListener
36  // implementations.
38  Invalid = 0,
39  // Events generated by the Retire Control Unit.
41  // Events generated by the Scheduler.
46  // Events generated by the Dispatch logic.
48 
50  };
51 
52  HWInstructionEvent(unsigned type, const InstRef &Inst)
53  : Type(type), IR(Inst) {}
54 
55  // The event type. The exact meaning depends on the subtarget.
56  const unsigned Type;
57 
58  // The instruction this event was generated for.
59  const InstRef &IR;
60 };
61 
63 public:
64  using ResourceRef = std::pair<uint64_t, uint64_t>;
66  ArrayRef<std::pair<ResourceRef, ResourceCycles>> UR)
68 
70 };
71 
73 public:
75  unsigned UOps)
77  UsedPhysRegs(Regs), MicroOpcodes(UOps) {}
78  // Number of physical register allocated for this instruction. There is one
79  // entry per register file.
81  // Number of micro opcodes dispatched.
82  // This field is often set to the total number of micro-opcodes specified by
83  // the instruction descriptor of IR.
84  // The only exception is when IR declares a number of micro opcodes
85  // which exceeds the processor DispatchWidth, and - by construction - it
86  // requires multiple cycles to be fully dispatched. In that particular case,
87  // the dispatch logic would generate more than one dispatch event (one per
88  // cycle), and each event would declare how many micro opcodes are effectively
89  // been dispatched to the schedulers.
90  unsigned MicroOpcodes;
91 };
92 
94 public:
97  FreedPhysRegs(Regs) {}
98  // Number of register writes that have been architecturally committed. There
99  // is one entry per register file.
101 };
102 
103 // A HWStallEvent represents a pipeline stall caused by the lack of hardware
104 // resources.
106 public:
108  Invalid = 0,
109  // Generic stall events generated by the DispatchStage.
112  // Generic stall events generated by the Scheduler.
118  };
119 
120  HWStallEvent(unsigned type, const InstRef &Inst) : Type(type), IR(Inst) {}
121 
122  // The exact meaning of the stall event type depends on the subtarget.
123  const unsigned Type;
124 
125  // The instruction this event was generated for.
126  const InstRef &IR;
127 };
128 
129 // A HWPressureEvent describes an increase in backend pressure caused by
130 // the presence of data dependencies or unavailability of pipeline resources.
132 public:
134  INVALID = 0,
135  // Scheduler was unable to issue all the ready instructions because some
136  // pipeline resources were unavailable.
138  // Instructions could not be issued because of register data dependencies.
140  // Instructions could not be issued because of memory dependencies.
142  };
143 
145  uint64_t Mask = 0)
146  : Reason(reason), AffectedInstructions(Insts), ResourceMask(Mask) {}
147 
148  // Reason for this increase in backend pressure.
150 
151  // Instructions affected (i.e. delayed) by this increase in backend pressure.
153 
154  // A mask of unavailable processor resources.
155  const uint64_t ResourceMask;
156 };
157 
159 public:
160  // Generic events generated by the pipeline.
161  virtual void onCycleBegin() {}
162  virtual void onCycleEnd() {}
163 
164  virtual void onEvent(const HWInstructionEvent &Event) {}
165  virtual void onEvent(const HWStallEvent &Event) {}
166  virtual void onEvent(const HWPressureEvent &Event) {}
167 
168  using ResourceRef = std::pair<uint64_t, uint64_t>;
169  virtual void onResourceAvailable(const ResourceRef &RRef) {}
170 
171  // Events generated by the Scheduler when buffered resources are
172  // consumed/freed for an instruction.
173  virtual void onReservedBuffers(const InstRef &Inst,
174  ArrayRef<unsigned> Buffers) {}
175  virtual void onReleasedBuffers(const InstRef &Inst,
176  ArrayRef<unsigned> Buffers) {}
177 
178  virtual ~HWEventListener() {}
179 
180 private:
181  virtual void anchor();
182 };
183 } // namespace mca
184 } // namespace llvm
185 
186 #endif // LLVM_MCA_HWEVENTLISTENER_H
llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:23
llvm::mca::HWPressureEvent::GenericReason
GenericReason
Definition: HWEventListener.h:133
llvm::mca::HWEventListener::onReservedBuffers
virtual void onReservedBuffers(const InstRef &Inst, ArrayRef< unsigned > Buffers)
Definition: HWEventListener.h:173
llvm::mca::HWInstructionIssuedEvent
Definition: HWEventListener.h:62
llvm::mca::HWEventListener::onCycleBegin
virtual void onCycleBegin()
Definition: HWEventListener.h:161
llvm::mca::HWEventListener::onResourceAvailable
virtual void onResourceAvailable(const ResourceRef &RRef)
Definition: HWEventListener.h:169
llvm::mca::HWInstructionIssuedEvent::UsedResources
ArrayRef< std::pair< ResourceRef, ResourceCycles > > UsedResources
Definition: HWEventListener.h:69
llvm::mca::HWStallEvent::HWStallEvent
HWStallEvent(unsigned type, const InstRef &Inst)
Definition: HWEventListener.h:120
llvm::mca::HWInstructionDispatchedEvent::HWInstructionDispatchedEvent
HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef< unsigned > Regs, unsigned UOps)
Definition: HWEventListener.h:74
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::mca::HWStallEvent::RegisterFileStall
@ RegisterFileStall
Definition: HWEventListener.h:110
llvm::mca::HWEventListener::onReleasedBuffers
virtual void onReleasedBuffers(const InstRef &Inst, ArrayRef< unsigned > Buffers)
Definition: HWEventListener.h:175
llvm::mca::HWInstructionEvent::Dispatched
@ Dispatched
Definition: HWEventListener.h:47
llvm::mca::HWStallEvent::StoreQueueFull
@ StoreQueueFull
Definition: HWEventListener.h:116
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
Instruction.h
llvm::mca::HWInstructionEvent::Type
const unsigned Type
Definition: HWEventListener.h:56
llvm::mca::HWEventListener::onCycleEnd
virtual void onCycleEnd()
Definition: HWEventListener.h:162
llvm::mca::HWInstructionEvent::IR
const InstRef & IR
Definition: HWEventListener.h:59
llvm::mca::HWInstructionEvent::Issued
@ Issued
Definition: HWEventListener.h:44
llvm::mca::HWStallEvent::DispatchGroupStall
@ DispatchGroupStall
Definition: HWEventListener.h:113
llvm::mca::HWStallEvent::LastGenericEvent
@ LastGenericEvent
Definition: HWEventListener.h:117
llvm::mca::HWPressureEvent
Definition: HWEventListener.h:131
llvm::mca::HWInstructionIssuedEvent::ResourceRef
std::pair< uint64_t, uint64_t > ResourceRef
Definition: HWEventListener.h:64
llvm::mca::HWInstructionRetiredEvent::HWInstructionRetiredEvent
HWInstructionRetiredEvent(const InstRef &IR, ArrayRef< unsigned > Regs)
Definition: HWEventListener.h:95
llvm::mca::HWInstructionEvent::HWInstructionEvent
HWInstructionEvent(unsigned type, const InstRef &Inst)
Definition: HWEventListener.h:52
llvm::mca::HWStallEvent::GenericEventType
GenericEventType
Definition: HWEventListener.h:107
llvm::mca::HWInstructionDispatchedEvent::UsedPhysRegs
ArrayRef< unsigned > UsedPhysRegs
Definition: HWEventListener.h:80
llvm::mca::HWPressureEvent::AffectedInstructions
ArrayRef< InstRef > AffectedInstructions
Definition: HWEventListener.h:152
llvm::mca::HWStallEvent::SchedulerQueueFull
@ SchedulerQueueFull
Definition: HWEventListener.h:114
llvm::mca::HWPressureEvent::RESOURCES
@ RESOURCES
Definition: HWEventListener.h:137
type
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference and DH registers in an instruction requiring REX prefix divb and mulb both produce results in AH If isel emits a CopyFromReg which gets turned into a movb and that can be allocated a r8b r15b To get around isel emits a CopyFromReg from AX and then right shift it down by and truncate it It s not pretty but it works We need some register allocation magic to make the hack go which would often require a callee saved register Callees usually need to keep this value live for most of their body so it doesn t add a significant burden on them We currently implement this in however this is suboptimal because it means that it would be quite awkward to implement the optimization for callers A better implementation would be to relax the LLVM IR rules for sret arguments to allow a function with an sret argument to have a non void return type
Definition: README-X86-64.txt:70
llvm::mca::HWInstructionDispatchedEvent::MicroOpcodes
unsigned MicroOpcodes
Definition: HWEventListener.h:90
llvm::mca::HWEventListener::onEvent
virtual void onEvent(const HWInstructionEvent &Event)
Definition: HWEventListener.h:164
llvm::mca::HWStallEvent::RetireControlUnitStall
@ RetireControlUnitStall
Definition: HWEventListener.h:111
llvm::mca::HWInstructionEvent::Ready
@ Ready
Definition: HWEventListener.h:43
llvm::mca::HWInstructionEvent::Invalid
@ Invalid
Definition: HWEventListener.h:38
llvm::mca::HWEventListener::~HWEventListener
virtual ~HWEventListener()
Definition: HWEventListener.h:178
ArrayRef.h
llvm::mca::HWStallEvent::IR
const InstRef & IR
Definition: HWEventListener.h:126
llvm::mca::HWInstructionEvent::Pending
@ Pending
Definition: HWEventListener.h:42
llvm::mca::HWInstructionEvent
Definition: HWEventListener.h:27
llvm::mca::InstRef
An InstRef contains both a SourceMgr index and Instruction pair.
Definition: Instruction.h:563
llvm::mca::HWInstructionEvent::GenericEventType
GenericEventType
Definition: HWEventListener.h:37
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::mca::HWStallEvent::LoadQueueFull
@ LoadQueueFull
Definition: HWEventListener.h:115
llvm::mca::HWPressureEvent::HWPressureEvent
HWPressureEvent(GenericReason reason, ArrayRef< InstRef > Insts, uint64_t Mask=0)
Definition: HWEventListener.h:144
llvm::mca::HWInstructionIssuedEvent::HWInstructionIssuedEvent
HWInstructionIssuedEvent(const InstRef &IR, ArrayRef< std::pair< ResourceRef, ResourceCycles >> UR)
Definition: HWEventListener.h:65
llvm::mca::HWStallEvent::Type
const unsigned Type
Definition: HWEventListener.h:123
llvm::mca::HWInstructionRetiredEvent
Definition: HWEventListener.h:93
llvm::mca::HWPressureEvent::INVALID
@ INVALID
Definition: HWEventListener.h:134
llvm::mca::HWStallEvent
Definition: HWEventListener.h:105
llvm::mca::HWPressureEvent::ResourceMask
const uint64_t ResourceMask
Definition: HWEventListener.h:155
llvm::mca::HWPressureEvent::MEMORY_DEPS
@ MEMORY_DEPS
Definition: HWEventListener.h:141
llvm::mca::HWEventListener::onEvent
virtual void onEvent(const HWPressureEvent &Event)
Definition: HWEventListener.h:166
llvm::mca::HWStallEvent::Invalid
@ Invalid
Definition: HWEventListener.h:108
llvm::mca::HWInstructionEvent::LastGenericEventType
@ LastGenericEventType
Definition: HWEventListener.h:49
llvm::mca::HWEventListener
Definition: HWEventListener.h:158
llvm::mca::HWPressureEvent::REGISTER_DEPS
@ REGISTER_DEPS
Definition: HWEventListener.h:139
llvm::mca::HWEventListener::ResourceRef
std::pair< uint64_t, uint64_t > ResourceRef
Definition: HWEventListener.h:168
llvm::mca::HWEventListener::onEvent
virtual void onEvent(const HWStallEvent &Event)
Definition: HWEventListener.h:165
llvm::mca::HWInstructionRetiredEvent::FreedPhysRegs
ArrayRef< unsigned > FreedPhysRegs
Definition: HWEventListener.h:100
Support.h
llvm::mca::HWInstructionEvent::Executed
@ Executed
Definition: HWEventListener.h:45
llvm::mca::HWPressureEvent::Reason
GenericReason Reason
Definition: HWEventListener.h:149
llvm::mca::HWInstructionDispatchedEvent
Definition: HWEventListener.h:72
llvm::mca::HWInstructionEvent::Retired
@ Retired
Definition: HWEventListener.h:40