LLVM
15.0.0git
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Classes | |
class | AMDGPUCustomBehaviour |
class | AMDGPUInstrPostProcess |
class | CodeEmitter |
A utility class used to compute instruction encodings for a code region. More... | |
class | Context |
struct | CriticalDependency |
A critical data dependency descriptor. More... | |
class | CustomBehaviour |
Class which can be overriden by targets to enforce instruction dependencies and behaviours that aren't expressed well enough within the scheduling model for mca to automatically simulate them properly. More... | |
class | CycleSegment |
A sequence of cycles. More... | |
class | DefaultResourceStrategy |
Default resource allocation strategy used by processor resource groups and processor resources with multiple units. More... | |
class | DefaultSchedulerStrategy |
Default instruction selection strategy used by class Scheduler. More... | |
class | DispatchStage |
class | EntryStage |
class | ExecuteStage |
class | HardwareUnit |
class | HWEventListener |
class | HWInstructionDispatchedEvent |
class | HWInstructionEvent |
class | HWInstructionIssuedEvent |
class | HWInstructionRetiredEvent |
class | HWPressureEvent |
class | HWStallEvent |
class | InOrderIssueStage |
class | InstrBuilder |
A builder class that knows how to construct Instruction objects. More... | |
struct | InstrDesc |
An instruction descriptor. More... | |
class | InstRef |
An InstRef contains both a SourceMgr index and Instruction pair. More... | |
class | InstrPostProcess |
Class which can be overriden by targets to modify the mca::Instruction objects before the pipeline starts. More... | |
class | Instruction |
An instruction propagated through the simulated instruction pipeline. More... | |
class | InstructionBase |
Base class for instructions consumed by the simulation pipeline. More... | |
class | InstructionError |
class | InstructionTables |
class | LSUnit |
Default Load/Store Unit (LS Unit) for simulated processors. More... | |
class | LSUnitBase |
Abstract base interface for LS (load/store) units in llvm-mca. More... | |
class | MCAOperand |
A representation of an mca::Instruction operand for use in mca::CustomBehaviour. More... | |
class | MemoryGroup |
A node of a memory dependency graph. More... | |
class | MicroOpQueueStage |
A stage that simulates a queue of instruction opcodes. More... | |
class | Pipeline |
A pipeline for a specific subtarget. More... | |
struct | PipelineOptions |
This is a convenience struct to hold the parameters necessary for creating the pre-built "default" out-of-order pipeline. More... | |
struct | ReadDescriptor |
A register read descriptor. More... | |
class | ReadState |
Tracks register operand latency in cycles. More... | |
class | RegisterFile |
Manages hardware register files, and tracks register definitions for register renaming purposes. More... | |
class | ResourceCycles |
This class represents the number of cycles per resource (fractions of cycles). More... | |
class | ResourceManager |
A resource manager for processor resource units and groups. More... | |
class | ResourceState |
A processor resource descriptor. More... | |
class | ResourceStrategy |
Resource allocation strategy used by hardware scheduler resources. More... | |
struct | ResourceUsage |
Helper used by class InstrDesc to describe how hardware resources are used. More... | |
struct | RetireControlUnit |
This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO backend. More... | |
class | RetireStage |
class | Scheduler |
Class Scheduler is responsible for issuing instructions to pipeline resources. More... | |
class | SchedulerStrategy |
class | SourceMgr |
class | Stage |
struct | StallInfo |
class | View |
struct | WaitCntInfo |
struct | WriteDescriptor |
A register write descriptor. More... | |
class | WriteRef |
A reference to a register write. More... | |
class | WriteState |
Tracks uses of a register definition (e.g. More... | |
class | X86InstrPostProcess |
Typedefs | |
using | ResourceRef = std::pair< uint64_t, uint64_t > |
A resource unit identifier. More... | |
typedef std::pair< unsigned, unsigned > | BufferUsageEntry |
using | ResourceUse = std::pair< ResourceRef, ResourceCycles > |
typedef std::pair< unsigned, const Instruction & > | SourceRef |
Enumerations | |
enum | ResourceStateEvent { RS_BUFFER_AVAILABLE, RS_BUFFER_UNAVAILABLE, RS_RESERVED } |
Used to notify the internal state of a processor resource. More... | |
Variables | |
constexpr int | UNKNOWN_CYCLES = -512 |
typedef std::pair<unsigned, unsigned> llvm::mca::BufferUsageEntry |
Definition at line 301 of file ResourceManager.h.
typedef std::pair< uint64_t, uint64_t > llvm::mca::ResourceRef |
A resource unit identifier.
This is used to identify a specific processor resource unit using a pair of indices where the 'first' index is a processor resource mask, and the 'second' index is an index for a "sub-resource" (i.e. unit).
Definition at line 297 of file ResourceManager.h.
using llvm::mca::ResourceUse = typedef std::pair<ResourceRef, ResourceCycles> |
Definition at line 63 of file HWEventListener.h.
typedef std::pair<unsigned, const Instruction &> llvm::mca::SourceRef |
Definition at line 26 of file SourceMgr.h.
Used to notify the internal state of a processor resource.
A processor resource is available if it is not reserved, and there are available slots in the buffer. A processor resource is unavailable if it is either reserved, or the associated buffer is full. A processor resource with a buffer size of -1 is always available if it is not reserved.
Values of type ResourceStateEvent are returned by method ResourceManager::canBeDispatched()
The naming convention for resource state events is:
Enumerator | |
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RS_BUFFER_AVAILABLE | |
RS_BUFFER_UNAVAILABLE | |
RS_RESERVED |
Definition at line 40 of file ResourceManager.h.
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Return a number of cycles left until register requirements of the instructions are met.
Definition at line 103 of file InOrderIssueStage.cpp.
References llvm::mca::RegisterFile::checkRAWHazards(), llvm::mca::RegisterFile::RAWHazard::CyclesLeft, llvm::mca::RegisterFile::RAWHazard::hasUnknownCycles(), IR, and llvm::mca::RegisterFile::RAWHazard::isValid().
double llvm::mca::computeBlockRThroughput | ( | const MCSchedModel & | SM, |
unsigned | DispatchWidth, | ||
unsigned | NumMicroOps, | ||
ArrayRef< unsigned > | ProcResourceUsage | ||
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Compute the reciprocal block throughput from a set of processor resource cycles.
The reciprocal block throughput is computed as the MAX between:
Definition at line 82 of file Support.cpp.
References E, llvm::MCSchedModel::getNumProcResourceKinds(), llvm::MCSchedModel::getProcResource(), I, llvm::max(), and llvm::MCProcResourceDesc::NumUnits.
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Definition at line 247 of file InstrBuilder.cpp.
References llvm::MCSchedModel::computeInstrLatency(), llvm::MCInstrDesc::isCall(), and llvm::Latency.
void llvm::mca::computeProcResourceMasks | ( | const MCSchedModel & | SM, |
MutableArrayRef< uint64_t > | Masks | ||
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Populates vector Masks with processor resource masks.
The number of bits set in a mask depends on the processor resource type. Each processor resource mask has at least one bit set. For groups, the number of bits set in the mask is equal to the cardinality of the group plus one. Excluding the most significant bit, the remaining bits in the mask identify processor resources that are part of the group.
Example:
ResourceA – Mask: 0b001 ResourceB – Mask: 0b010 ResourceAB – Mask: 0b100 U (ResourceA::Mask | ResourceB::Mask) == 0b111
ResourceAB is a processor resource group containing ResourceA and ResourceB. Each resource mask uniquely identifies a resource; both ResourceA and ResourceB only have one bit set. ResourceAB is a group; excluding the most significant bit in the mask, the remaining bits identify the composition of the group.
Resource masks are used by the ResourceManager to solve set membership problems with simple bit manipulation operations.
Definition at line 39 of file Support.cpp.
References assert(), llvm::dbgs(), E, llvm::format_decimal(), llvm::format_hex(), llvm::MCSchedModel::getNumProcResourceKinds(), llvm::MCSchedModel::getProcResource(), I, LLVM_DEBUG, llvm::MCProcResourceDesc::Name, llvm::MCProcResourceDesc::NumUnits, llvm::ArrayRef< T >::size(), and llvm::MCProcResourceDesc::SubUnitsIdxBegin.
Referenced by llvm::mca::InstrBuilder::InstrBuilder(), llvm::mca::InstructionTables::InstructionTables(), and llvm::mca::ResourceManager::ResourceManager().
Definition at line 88 of file InOrderIssueStage.cpp.
References IR, llvm::min(), and UNKNOWN_CYCLES.
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Definition at line 100 of file Support.h.
References assert(), llvm::countLeadingZeros(), and llvm::BitmaskEnumDetail::Mask().
Referenced by llvm::mca::ResourceManager::checkAvailability(), initializeUsedResources(), llvm::mca::ResourceManager::releaseBuffers(), llvm::mca::ResourceManager::releaseResource(), llvm::mca::ResourceManager::reserveBuffers(), llvm::mca::ResourceManager::reserveResource(), llvm::mca::ResourceManager::resolveResourceMask(), llvm::mca::ResourceManager::ResourceManager(), llvm::mca::ResourceState::ResourceState(), and selectImpl().
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Definition at line 105 of file ResourceManager.cpp.
References llvm::mca::ResourceState::getNumUnits(), llvm::mca::ResourceState::getReadyMask(), and llvm::mca::ResourceState::isAResourceGroup().
Referenced by llvm::mca::ResourceManager::ResourceManager().
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Definition at line 79 of file InOrderIssueStage.cpp.
References llvm::dbgs(), IR, LLVM_DEBUG, and llvm::AArch64::RM.
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Definition at line 38 of file InstrBuilder.cpp.
References assert(), B, llvm::MCProcResourceDesc::BufferSize, llvm::countPopulation(), llvm::MCWriteProcResEntry::Cycles, llvm::dbgs(), E, llvm::SmallVectorImpl< T >::emplace_back(), llvm::find_if(), llvm::format_hex(), llvm::MCSchedModel::getNumProcResourceKinds(), llvm::MCSchedModel::getProcResource(), getResourceStateIndex(), llvm::MCSubtargetInfo::getSchedModel(), llvm::MCSubtargetInfo::getWriteProcResBegin(), llvm::APInt::getZExtValue(), I, LLVM_DEBUG, llvm::BitmaskEnumDetail::Mask(), llvm::MCProcResourceDesc::Name, llvm::MCSchedClassDesc::Name, llvm::WithColor::note(), llvm::MCSchedClassDesc::NumWriteProcResEntries, llvm::PowerOf2Floor(), llvm::MCWriteProcResEntry::ProcResourceIdx, llvm::APInt::setBit(), llvm::sort(), llvm::MCProcResourceDesc::SuperIdx, llvm::WithColor::warning(), and while().
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Definition at line 740 of file Instruction.h.
References IR.
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Definition at line 26 of file ResourceManager.cpp.
References getResourceStateIndex().
Referenced by llvm::mca::DefaultResourceStrategy::select().
HWStallEvent::GenericEventType llvm::mca::toHWStallEventType | ( | Scheduler::Status | Status | ) |
Definition at line 26 of file ExecuteStage.cpp.
References llvm::mca::HWStallEvent::DispatchGroupStall, llvm::mca::HWStallEvent::Invalid, llvm_unreachable, llvm::mca::HWStallEvent::LoadQueueFull, llvm::mca::Scheduler::SC_AVAILABLE, llvm::mca::Scheduler::SC_BUFFERS_FULL, llvm::mca::Scheduler::SC_DISPATCH_GROUP_STALL, llvm::mca::Scheduler::SC_LOAD_QUEUE_FULL, llvm::mca::Scheduler::SC_STORE_QUEUE_FULL, llvm::mca::HWStallEvent::SchedulerQueueFull, and llvm::mca::HWStallEvent::StoreQueueFull.
Referenced by llvm::mca::ExecuteStage::isAvailable().
Definition at line 161 of file ExecuteStage.cpp.
References assert(), llvm::mca::InstructionBase::getMayLoad(), llvm::mca::InstructionBase::getMayStore(), IR, llvm::mca::Instruction::isEliminated(), and llvm::mca::Instruction::isReady().
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Definition at line 262 of file InstrBuilder.cpp.
References E, llvm::MCInstrDesc::getNumDefs(), llvm::MCInst::getNumOperands(), llvm::MCInstrDesc::getNumOperands(), llvm::MCInst::getOperand(), llvm::MCInstrDesc::hasOptionalDef(), and I.
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Definition at line 34 of file Instruction.h.
Referenced by llvm::mca::WriteState::addUser(), llvm::mca::RegisterFile::checkRAWHazards(), llvm::mca::WriteState::cycleEvent(), llvm::mca::ReadState::cycleEvent(), findFirstWriteBackCycle(), llvm::mca::WriteState::isExecuted(), llvm::mca::RegisterFile::onInstructionExecuted(), llvm::mca::WriteState::onInstructionIssued(), llvm::mca::RegisterFile::removeRegisterWrite(), and llvm::mca::ReadState::writeStartEvent().