llvm::mca Namespace Reference

Classes
class	CodeEmitter
	A utility class used to compute instruction encodings for a code region. More...
class	Context
struct	CriticalDependency
	A critical data dependency descriptor. More...
class	CycleSegment
	A sequence of cycles. More...
class	DefaultResourceStrategy
	Default resource allocation strategy used by processor resource groups and processor resources with multiple units. More...
class	DefaultSchedulerStrategy
	Default instruction selection strategy used by class Scheduler. More...
class	DispatchStage
class	EntryStage
class	ExecuteStage
class	HardwareUnit
class	HWEventListener
class	HWInstructionDispatchedEvent
class	HWInstructionEvent
class	HWInstructionIssuedEvent
class	HWInstructionRetiredEvent
class	HWPressureEvent
class	HWStallEvent
class	InstrBuilder
	A builder class that knows how to construct Instruction objects. More...
struct	InstrDesc
	An instruction descriptor. More...
class	InstRef
	An InstRef contains both a SourceMgr index and Instruction pair. More...
class	Instruction
	An instruction propagated through the simulated instruction pipeline. More...
class	InstructionBase
	Base class for instructions consumed by the simulation pipeline. More...
class	InstructionError
class	InstructionTables
class	LSUnit
	Default Load/Store Unit (LS Unit) for simulated processors. More...
class	LSUnitBase
	Abstract base interface for LS (load/store) units in llvm-mca. More...
class	MemoryGroup
	A node of a memory dependency graph. More...
class	MicroOpQueueStage
	A stage that simulates a queue of instruction opcodes. More...
class	Pipeline
	A pipeline for a specific subtarget. More...
struct	PipelineOptions
	This is a convenience struct to hold the parameters necessary for creating the pre-built "default" out-of-order pipeline. More...
struct	ReadDescriptor
	A register read descriptor. More...
class	ReadState
	Tracks register operand latency in cycles. More...
class	RegisterFile
	Manages hardware register files, and tracks register definitions for register renaming purposes. More...
class	ResourceCycles
	This class represents the number of cycles per resource (fractions of cycles). More...
class	ResourceManager
	A resource manager for processor resource units and groups. More...
class	ResourceState
	A processor resource descriptor. More...
class	ResourceStrategy
	Resource allocation strategy used by hardware scheduler resources. More...
struct	ResourceUsage
	Helper used by class InstrDesc to describe how hardware resources are used. More...
struct	RetireControlUnit
	This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO backend. More...
class	RetireStage
class	Scheduler
	Class Scheduler is responsible for issuing instructions to pipeline resources. More...
class	SchedulerStrategy
class	SourceMgr
class	Stage
struct	WriteDescriptor
	A register write descriptor. More...
class	WriteRef
	A reference to a register write. More...
class	WriteState
	Tracks uses of a register definition (e.g. More...

Typedefs
typedef std::pair< uint64_t, uint64_t >	ResourceRef
	A resource unit identifier. More...
typedef std::pair< unsigned, unsigned >	BufferUsageEntry
typedef std::pair< unsigned, const Instruction & >	SourceRef

Enumerations
enum	ResourceStateEvent { RS_BUFFER_AVAILABLE, RS_BUFFER_UNAVAILABLE, RS_RESERVED }
	Used to notify the internal state of a processor resource. More...

Functions
raw_ostream &	operator<< (raw_ostream &OS, const InstRef &IR)
void	computeProcResourceMasks (const MCSchedModel &SM, MutableArrayRef< uint64_t > Masks)
	Populates vector Masks with processor resource masks. More...
unsigned	getResourceStateIndex (uint64_t Mask)
double	computeBlockRThroughput (const MCSchedModel &SM, unsigned DispatchWidth, unsigned NumMicroOps, ArrayRef< unsigned > ProcResourceUsage)
	Compute the reciprocal block throughput from a set of processor resource cycles. More...
static uint64_t	selectImpl (uint64_t CandidateMask, uint64_t &NextInSequenceMask)
static std::unique_ptr< ResourceStrategy >	getStrategyFor (const ResourceState &RS)
static void	initializeUsedResources (InstrDesc &ID, const MCSchedClassDesc &SCDesc, const MCSubtargetInfo &STI, ArrayRef< uint64_t > ProcResourceMasks)
static void	computeMaxLatency (InstrDesc &ID, const MCInstrDesc &MCDesc, const MCSchedClassDesc &SCDesc, const MCSubtargetInfo &STI)
static Error	verifyOperands (const MCInstrDesc &MCDesc, const MCInst &MCI)
HWStallEvent::GenericEventType	toHWStallEventType (Scheduler::Status Status)
static void	verifyInstructionEliminated (const InstRef &IR)

Variables
constexpr int	UNKNOWN_CYCLES = -512

Typedef Documentation

BufferUsageEntry

typedef std::pair<unsigned, unsigned> llvm::mca::BufferUsageEntry

Definition at line 301 of file ResourceManager.h.

ResourceRef

typedef std::pair<uint64_t, uint64_t> llvm::mca::ResourceRef

A resource unit identifier.

This is used to identify a specific processor resource unit using a pair of indices where the 'first' index is a processor resource mask, and the 'second' index is an index for a "sub-resource" (i.e. unit).

Definition at line 297 of file ResourceManager.h.

SourceRef

typedef std::pair<unsigned, const Instruction &> llvm::mca::SourceRef

Definition at line 26 of file SourceMgr.h.

Enumeration Type Documentation

ResourceStateEvent

enum llvm::mca::ResourceStateEvent

Used to notify the internal state of a processor resource.

A processor resource is available if it is not reserved, and there are available slots in the buffer. A processor resource is unavailable if it is either reserved, or the associated buffer is full. A processor resource with a buffer size of -1 is always available if it is not reserved.

Values of type ResourceStateEvent are returned by method ResourceManager::canBeDispatched()

The naming convention for resource state events is:

• Event names start with prefix RS_
• Prefix RS_ is followed by a string describing the actual resource state.

Enumerator
RS_BUFFER_AVAILABLE
RS_BUFFER_UNAVAILABLE
RS_RESERVED

Definition at line 40 of file ResourceManager.h.

Function Documentation

computeBlockRThroughput()

double llvm::mca::computeBlockRThroughput	(	const MCSchedModel &	SM,
		unsigned	DispatchWidth,
		unsigned	NumMicroOps,
		ArrayRef< unsigned >	ProcResourceUsage
	)

Compute the reciprocal block throughput from a set of processor resource cycles.

The reciprocal block throughput is computed as the MAX between:

• NumMicroOps / DispatchWidth
• ProcResourceCycles / #ProcResourceUnits (for every consumed resource).

Definition at line 82 of file Support.cpp.

References E, llvm::MCSchedModel::getNumProcResourceKinds(), llvm::MCSchedModel::getProcResource(), I, llvm::max(), llvm::MCProcResourceDesc::NumUnits, and llvm::mca::ResourceCycles::ResourceCycles().

Referenced by getResourceStateIndex().

computeMaxLatency()

static void llvm::mca::computeMaxLatency ( InstrDesc &  ID, const MCInstrDesc &  MCDesc, const MCSchedClassDesc &  SCDesc, const MCSubtargetInfo &  STI  )

static

Definition at line 206 of file InstrBuilder.cpp.

References llvm::MCSchedModel::computeInstrLatency(), llvm::MCInstrDesc::isCall(), llvm::Latency, and llvm::mca::InstrDesc::MaxLatency.

Referenced by verifyOperands().

computeProcResourceMasks()

void llvm::mca::computeProcResourceMasks	(	const MCSchedModel &	SM,
		MutableArrayRef< uint64_t >	Masks
	)

Populates vector Masks with processor resource masks.

The number of bits set in a mask depends on the processor resource type. Each processor resource mask has at least one bit set. For groups, the number of bits set in the mask is equal to the cardinality of the group plus one. Excluding the most significant bit, the remaining bits in the mask identify processor resources that are part of the group.

Example:

ResourceA – Mask: 0b001 ResourceB – Mask: 0b010 ResourceAB – Mask: 0b100 U (ResourceA::Mask | ResourceB::Mask) == 0b111

ResourceAB is a processor resource group containing ResourceA and ResourceB. Each resource mask uniquely identifies a resource; both ResourceA and ResourceB only have one bit set. ResourceAB is a group; excluding the most significant bit in the mask, the remaining bits identify the composition of the group.

Resource masks are used by the ResourceManager to solve set membership problems with simple bit manipulation operations.

Definition at line 39 of file Support.cpp.

References assert(), llvm::dbgs(), E, llvm::format_decimal(), llvm::format_hex(), llvm::MCSchedModel::getNumProcResourceKinds(), llvm::MCSchedModel::getProcResource(), I, LLVM_DEBUG, llvm::MCProcResourceDesc::Name, llvm::MCProcResourceDesc::NumUnits, llvm::ArrayRef< T >::size(), and llvm::MCProcResourceDesc::SubUnitsIdxBegin.

Referenced by llvm::mca::ResourceCycles::getDenominator(), llvm::mca::InstrBuilder::InstrBuilder(), llvm::mca::InstructionTables::InstructionTables(), and llvm::mca::ResourceManager::ResourceManager().

getResourceStateIndex()

unsigned llvm::mca::getResourceStateIndex ( uint64_t  Mask )

inline

Definition at line 99 of file Support.h.

References assert(), computeBlockRThroughput(), and llvm::countLeadingZeros().

Referenced by llvm::mca::ResourceManager::checkAvailability(), initializeUsedResources(), llvm::mca::ResourceManager::releaseBuffers(), llvm::mca::ResourceManager::releaseResource(), llvm::mca::ResourceManager::reserveBuffers(), llvm::mca::ResourceManager::reserveResource(), llvm::mca::ResourceManager::resolveResourceMask(), llvm::mca::ResourceManager::ResourceManager(), llvm::mca::ResourceState::ResourceState(), and selectImpl().

getStrategyFor()

static std::unique_ptr<ResourceStrategy> llvm::mca::getStrategyFor ( const ResourceState &  RS )

static

Definition at line 105 of file ResourceManager.cpp.

References llvm::mca::ResourceState::getNumUnits(), llvm::mca::ResourceState::getReadyMask(), and llvm::mca::ResourceState::isAResourceGroup().

Referenced by llvm::mca::ResourceManager::ResourceManager().

initializeUsedResources()

static void llvm::mca::initializeUsedResources ( InstrDesc &  ID, const MCSchedClassDesc &  SCDesc, const MCSubtargetInfo &  STI, ArrayRef< uint64_t >  ProcResourceMasks  )

static

Definition at line 38 of file InstrBuilder.cpp.

References assert(), B, llvm::MCProcResourceDesc::BufferSize, llvm::countPopulation(), llvm::MCWriteProcResEntry::Cycles, llvm::dbgs(), E, llvm::format_hex(), llvm::MCSchedModel::getNumProcResourceKinds(), llvm::MCSchedModel::getProcResource(), getResourceStateIndex(), llvm::MCSubtargetInfo::getSchedModel(), llvm::MCSubtargetInfo::getWriteProcResBegin(), llvm::APInt::getZExtValue(), I, LLVM_DEBUG, llvm::BitmaskEnumDetail::Mask(), llvm::mca::InstrDesc::MustIssueImmediately, llvm::MCProcResourceDesc::Name, llvm::MCSchedClassDesc::Name, llvm::WithColor::note(), llvm::MCSchedClassDesc::NumWriteProcResEntries, llvm::PowerOf2Floor(), llvm::MCWriteProcResEntry::ProcResourceIdx, llvm::mca::InstrDesc::Resources, llvm::APInt::setBit(), llvm::sort(), llvm::MCProcResourceDesc::SuperIdx, llvm::mca::InstrDesc::UsedBuffers, llvm::mca::InstrDesc::UsedProcResGroups, llvm::mca::InstrDesc::UsedProcResUnits, and llvm::WithColor::warning().

Referenced by verifyOperands().

operator<<()

raw_ostream& llvm::mca::operator<< ( raw_ostream &  OS, const InstRef &  IR  )

inline

Definition at line 591 of file Instruction.h.

References llvm::mca::InstRef::print().

selectImpl()

static uint64_t llvm::mca::selectImpl ( uint64_t  CandidateMask, uint64_t &  NextInSequenceMask  )

static

Definition at line 26 of file ResourceManager.cpp.

References getResourceStateIndex().

Referenced by getRegClassFromGRPhysReg(), getVectorSHLImm(), and llvm::mca::DefaultResourceStrategy::select().

toHWStallEventType()

HWStallEvent::GenericEventType llvm::mca::toHWStallEventType

(

Scheduler::Status

Status

)

Definition at line 26 of file ExecuteStage.cpp.

References llvm::mca::HWStallEvent::DispatchGroupStall, llvm::mca::HWStallEvent::Invalid, llvm_unreachable, llvm::mca::HWStallEvent::LoadQueueFull, llvm::mca::Scheduler::SC_AVAILABLE, llvm::mca::Scheduler::SC_BUFFERS_FULL, llvm::mca::Scheduler::SC_DISPATCH_GROUP_STALL, llvm::mca::Scheduler::SC_LOAD_QUEUE_FULL, llvm::mca::Scheduler::SC_STORE_QUEUE_FULL, llvm::mca::HWStallEvent::SchedulerQueueFull, and llvm::mca::HWStallEvent::StoreQueueFull.

Referenced by llvm::mca::ExecuteStage::isAvailable().

verifyInstructionEliminated()

static void llvm::mca::verifyInstructionEliminated ( const InstRef &  IR )

static

Definition at line 161 of file ExecuteStage.cpp.

References assert(), llvm::mca::Instruction::forceExecuted(), llvm::mca::InstructionBase::getDesc(), llvm::mca::InstRef::getInstruction(), llvm::mca::Instruction::isEliminated(), llvm::mca::Instruction::isReady(), llvm::mca::Stage::moveToTheNextStage(), llvm::mca::ExecuteStage::notifyInstructionExecuted(), llvm::mca::ExecuteStage::notifyInstructionIssued(), llvm::mca::ExecuteStage::notifyInstructionPending(), and llvm::mca::ExecuteStage::notifyInstructionReady().

verifyOperands()

static Error llvm::mca::verifyOperands ( const MCInstrDesc &  MCDesc, const MCInst &  MCI  )

static

Definition at line 221 of file InstrBuilder.cpp.

References assert(), computeMaxLatency(), llvm::MCWriteLatencyEntry::Cycles, llvm::dbgs(), E, llvm::MCInstrInfo::get(), llvm::MCInstrDesc::getImplicitDefs(), llvm::MCInstrDesc::getImplicitUses(), llvm::MCInstrInfo::getName(), llvm::MCRegisterInfo::getName(), llvm::MCInstrDesc::getNumDefs(), llvm::MCInstrDesc::getNumImplicitDefs(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInst::getNumOperands(), llvm::MCInstrDesc::getNumOperands(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCSchedModel::getProcessorID(), llvm::MCInstrDesc::getSchedClass(), llvm::MCSchedModel::getSchedClassDesc(), llvm::MCSubtargetInfo::getSchedModel(), llvm::MCSubtargetInfo::getWriteLatencyEntry(), llvm::MCSchedModel::hasInstrSchedModel(), llvm::MCInstrDesc::hasOptionalDef(), llvm::MCInstrDesc::hasUnmodeledSideEffects(), I, initializeUsedResources(), llvm::MCSchedClassDesc::InvalidNumMicroOps, llvm::MCInstrDesc::isCall(), llvm::mca::WriteDescriptor::IsOptionalDef, llvm::MCOperand::isReg(), llvm::MCInstrDesc::isReturn(), llvm::MCSchedClassDesc::isVariant(), llvm::mca::WriteDescriptor::Latency, LLVM_DEBUG, llvm::mca::InstrDesc::MaxLatency, llvm::MCInstrDesc::mayLoad(), llvm::MCInstrDesc::mayStore(), llvm::WithColor::note(), llvm::mca::InstrDesc::NumMicroOps, llvm::MCSchedClassDesc::NumWriteLatencyEntries, llvm::mca::WriteDescriptor::OpIndex, llvm::mca::ReadDescriptor::OpIndex, llvm::mca::InstrDesc::Reads, llvm::mca::WriteDescriptor::RegisterID, llvm::mca::ReadDescriptor::RegisterID, llvm::MCSubtargetInfo::resolveVariantSchedClass(), llvm::mca::InstrDesc::Resources, llvm::mca::ReadDescriptor::SchedClassID, llvm::mca::WriteDescriptor::SClassOrWriteResourceID, llvm::mca::InstrDesc::UsedBuffers, llvm::mca::ReadDescriptor::UseIndex, llvm::WithColor::warning(), llvm::MCWriteLatencyEntry::WriteResourceID, and llvm::mca::InstrDesc::Writes.

Variable Documentation

UNKNOWN_CYCLES

constexpr int llvm::mca::UNKNOWN_CYCLES = -512

Definition at line 34 of file Instruction.h.

Referenced by llvm::mca::WriteState::addUser(), llvm::mca::WriteState::cycleEvent(), llvm::mca::ReadState::cycleEvent(), llvm::mca::WriteState::onInstructionIssued(), llvm::mca::RegisterFile::removeRegisterWrite(), and llvm::mca::ReadState::writeStartEvent().