LLVM 19.0.0git
Classes | Typedefs | Enumerations | Functions | Variables
llvm::mca Namespace Reference


class  AMDGPUCustomBehaviour
class  AMDGPUInstrPostProcess
class  CircularSourceMgr
 The default implementation of SourceMgr. More...
class  CodeEmitter
 A utility class used to compute instruction encodings for a code region. More...
class  Context
struct  CriticalDependency
 A critical data dependency descriptor. More...
class  CustomBehaviour
 Class which can be overriden by targets to enforce instruction dependencies and behaviours that aren't expressed well enough within the scheduling model for mca to automatically simulate them properly. More...
class  CycleSegment
 A sequence of cycles. More...
class  DefaultResourceStrategy
 Default resource allocation strategy used by processor resource groups and processor resources with multiple units. More...
class  DefaultSchedulerStrategy
 Default instruction selection strategy used by class Scheduler. More...
class  DispatchStage
class  EntryStage
class  ExecuteStage
class  HardwareUnit
class  HWEventListener
class  HWInstructionDispatchedEvent
class  HWInstructionEvent
class  HWInstructionIssuedEvent
class  HWInstructionRetiredEvent
class  HWPressureEvent
class  HWStallEvent
class  IncrementalSourceMgr
 An implementation of SourceMgr that allows users to add new instructions incrementally / dynamically. More...
class  InOrderIssueStage
class  InstrBuilder
 A builder class that knows how to construct Instruction objects. More...
struct  InstrDesc
 An instruction descriptor. More...
class  InstRef
 An InstRef contains both a SourceMgr index and Instruction pair. More...
class  InstrPostProcess
 Class which can be overriden by targets to modify the mca::Instruction objects before the pipeline starts. More...
class  Instruction
 An instruction propagated through the simulated instruction pipeline. More...
class  InstructionBase
 Base class for instructions consumed by the simulation pipeline. More...
class  InstructionError
class  InstructionTables
class  Instrument
class  InstrumentManager
 This class allows targets to optionally customize the logic that resolves scheduling class IDs. More...
struct  InstStreamPause
 This is actually not an error but a marker to indicate that the instruction stream is paused. More...
class  LSUnit
 Default Load/Store Unit (LS Unit) for simulated processors. More...
class  LSUnitBase
 Abstract base interface for LS (load/store) units in llvm-mca. More...
class  MCAOperand
 A representation of an mca::Instruction operand for use in mca::CustomBehaviour. More...
class  MemoryGroup
 A node of a memory dependency graph. More...
class  MicroOpQueueStage
 A stage that simulates a queue of instruction opcodes. More...
class  Pipeline
 A pipeline for a specific subtarget. More...
struct  PipelineOptions
 This is a convenience struct to hold the parameters necessary for creating the pre-built "default" out-of-order pipeline. More...
struct  ReadDescriptor
 A register read descriptor. More...
class  ReadState
 Tracks register operand latency in cycles. More...
class  RecycledInstErr
class  RegisterFile
 Manages hardware register files, and tracks register definitions for register renaming purposes. More...
class  ReleaseAtCycles
 This class represents the number of cycles per resource (fractions of cycles). More...
class  ResourceManager
 A resource manager for processor resource units and groups. More...
class  ResourceState
 A processor resource descriptor. More...
class  ResourceStrategy
 Resource allocation strategy used by hardware scheduler resources. More...
struct  ResourceUsage
 Helper used by class InstrDesc to describe how hardware resources are used. More...
struct  RetireControlUnit
 This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO backend. More...
class  RetireStage
class  RISCVInstrumentManager
class  RISCVLMULInstrument
class  RISCVSEWInstrument
class  Scheduler
 Class Scheduler is responsible for issuing instructions to pipeline resources. More...
class  SchedulerStrategy
struct  SourceMgr
 Abstracting the input code sequence (a sequence of MCInst) and assigning unique identifiers to every instruction in the sequence. More...
class  Stage
struct  StallInfo
class  View
struct  WaitCntInfo
struct  WriteDescriptor
 A register write descriptor. More...
class  WriteRef
 A reference to a register write. More...
class  WriteState
 Tracks uses of a register definition (e.g. More...
class  X86InstrPostProcess


using UniqueInstrument = std::unique_ptr< Instrument >
using ResourceRef = std::pair< uint64_t, uint64_t >
 A resource unit identifier.
typedef std::pair< unsigned, unsignedBufferUsageEntry
using ResourceUse = std::pair< ResourceRef, ReleaseAtCycles >
typedef std::pair< unsigned, const Instruction & > SourceRef


 Used to notify the internal state of a processor resource. More...


raw_ostreamoperator<< (raw_ostream &OS, const InstRef &IR)
void computeProcResourceMasks (const MCSchedModel &SM, MutableArrayRef< uint64_t > Masks)
 Populates vector Masks with processor resource masks.
unsigned getResourceStateIndex (uint64_t Mask)
double computeBlockRThroughput (const MCSchedModel &SM, unsigned DispatchWidth, unsigned NumMicroOps, ArrayRef< unsigned > ProcResourceUsage)
 Compute the reciprocal block throughput from a set of processor resource cycles.
static uint64_t selectImpl (uint64_t CandidateMask, uint64_t &NextInSequenceMask)
static std::unique_ptr< ResourceStrategygetStrategyFor (const ResourceState &RS)
static void initializeUsedResources (InstrDesc &ID, const MCSchedClassDesc &SCDesc, const MCSubtargetInfo &STI, ArrayRef< uint64_t > ProcResourceMasks)
static void computeMaxLatency (InstrDesc &ID, const MCInstrDesc &MCDesc, const MCSchedClassDesc &SCDesc, const MCSubtargetInfo &STI, unsigned CallLatency)
static Error verifyOperands (const MCInstrDesc &MCDesc, const MCInst &MCI)
hash_code hashMCOperand (const MCOperand &MCO)
hash_code hashMCInst (const MCInst &MCI)
 STATISTIC (NumVariantInst, "Number of MCInsts that doesn't have static Desc")
HWStallEvent::GenericEventType toHWStallEventType (Scheduler::Status Status)
static void verifyInstructionEliminated (const InstRef &IR)
static bool hasResourceHazard (const ResourceManager &RM, const InstRef &IR)
static unsigned findFirstWriteBackCycle (const InstRef &IR)
static unsigned checkRegisterHazard (const RegisterFile &PRF, const MCSubtargetInfo &STI, const InstRef &IR)
 Return a number of cycles left until register requirements of the instructions are met.
static void addRegisterReadWrite (RegisterFile &PRF, Instruction &IS, unsigned SourceIndex, const MCSubtargetInfo &STI, SmallVectorImpl< unsigned > &UsedRegs)
static std::pair< uint8_t, uint8_t > getEEWAndEMUL (unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW)
bool opcodeHasEEWAndEMULInfo (unsigned short Opcode)


constexpr int UNKNOWN_CYCLES = -512

Typedef Documentation

◆ BufferUsageEntry

Definition at line 301 of file ResourceManager.h.

◆ ResourceRef

typedef std::pair< uint64_t, uint64_t > llvm::mca::ResourceRef

A resource unit identifier.

This is used to identify a specific processor resource unit using a pair of indices where the 'first' index is a processor resource mask, and the 'second' index is an index for a "sub-resource" (i.e. unit).

Definition at line 297 of file ResourceManager.h.

◆ ResourceUse

using llvm::mca::ResourceUse = typedef std::pair<ResourceRef, ReleaseAtCycles>

Definition at line 66 of file HWEventListener.h.

◆ SourceRef

Definition at line 25 of file SourceMgr.h.

◆ UniqueInstrument

using llvm::mca::UniqueInstrument = typedef std::unique_ptr<Instrument>

Definition at line 136 of file CustomBehaviour.h.

Enumeration Type Documentation

◆ ResourceStateEvent

Used to notify the internal state of a processor resource.

A processor resource is available if it is not reserved, and there are available slots in the buffer. A processor resource is unavailable if it is either reserved, or the associated buffer is full. A processor resource with a buffer size of -1 is always available if it is not reserved.

Values of type ResourceStateEvent are returned by method ResourceManager::canBeDispatched()

The naming convention for resource state events is:

  • Event names start with prefix RS_
  • Prefix RS_ is followed by a string describing the actual resource state.

Definition at line 40 of file ResourceManager.h.

Function Documentation

◆ addRegisterReadWrite()

static void llvm::mca::addRegisterReadWrite ( RegisterFile PRF,
Instruction IS,
unsigned  SourceIndex,
const MCSubtargetInfo STI,
SmallVectorImpl< unsigned > &  UsedRegs 

◆ checkRegisterHazard()

static unsigned llvm::mca::checkRegisterHazard ( const RegisterFile PRF,
const MCSubtargetInfo STI,
const InstRef IR 

Return a number of cycles left until register requirements of the instructions are met.

Definition at line 103 of file InOrderIssueStage.cpp.

References llvm::mca::RegisterFile::checkRAWHazards(), llvm::mca::RegisterFile::RAWHazard::CyclesLeft, llvm::mca::RegisterFile::RAWHazard::hasUnknownCycles(), IR, and llvm::mca::RegisterFile::RAWHazard::isValid().

◆ computeBlockRThroughput()

double llvm::mca::computeBlockRThroughput ( const MCSchedModel SM,
unsigned  DispatchWidth,
unsigned  NumMicroOps,
ArrayRef< unsigned ProcResourceUsage 

Compute the reciprocal block throughput from a set of processor resource cycles.

The reciprocal block throughput is computed as the MAX between:

  • NumMicroOps / DispatchWidth
  • ProcReleaseAtCycles / #ProcResourceUnits (for every consumed resource).

Definition at line 83 of file Support.cpp.

References E, llvm::MCSchedModel::getNumProcResourceKinds(), llvm::MCSchedModel::getProcResource(), I, and llvm::MCProcResourceDesc::NumUnits.

◆ computeMaxLatency()

static void llvm::mca::computeMaxLatency ( InstrDesc ID,
const MCInstrDesc MCDesc,
const MCSchedClassDesc SCDesc,
const MCSubtargetInfo STI,
unsigned  CallLatency 

◆ computeProcResourceMasks()

void llvm::mca::computeProcResourceMasks ( const MCSchedModel SM,
MutableArrayRef< uint64_t Masks 

Populates vector Masks with processor resource masks.

The number of bits set in a mask depends on the processor resource type. Each processor resource mask has at least one bit set. For groups, the number of bits set in the mask is equal to the cardinality of the group plus one. Excluding the most significant bit, the remaining bits in the mask identify processor resources that are part of the group.


ResourceA – Mask: 0b001 ResourceB – Mask: 0b010 ResourceAB – Mask: 0b100 U (ResourceA::Mask | ResourceB::Mask) == 0b111

ResourceAB is a processor resource group containing ResourceA and ResourceB. Each resource mask uniquely identifies a resource; both ResourceA and ResourceB only have one bit set. ResourceAB is a group; excluding the most significant bit in the mask, the remaining bits identify the composition of the group.

Resource masks are used by the ResourceManager to solve set membership problems with simple bit manipulation operations.

Definition at line 40 of file Support.cpp.

References assert(), llvm::dbgs(), E, llvm::format_decimal(), llvm::format_hex(), llvm::MCSchedModel::getNumProcResourceKinds(), llvm::MCSchedModel::getProcResource(), I, LLVM_DEBUG, and llvm::ArrayRef< T >::size().

Referenced by llvm::mca::InstrBuilder::InstrBuilder(), llvm::mca::InstructionTables::InstructionTables(), and llvm::mca::ResourceManager::ResourceManager().

◆ findFirstWriteBackCycle()

static unsigned llvm::mca::findFirstWriteBackCycle ( const InstRef IR)

Definition at line 88 of file InOrderIssueStage.cpp.

References IR, and UNKNOWN_CYCLES.

◆ getEEWAndEMUL()

static std::pair< uint8_t, uint8_t > llvm::mca::getEEWAndEMUL ( unsigned  Opcode,
uint8_t  SEW 

◆ getResourceStateIndex()

unsigned llvm::mca::getResourceStateIndex ( uint64_t  Mask)

◆ getStrategyFor()

static std::unique_ptr< ResourceStrategy > llvm::mca::getStrategyFor ( const ResourceState RS)

◆ hashMCInst()

hash_code llvm::mca::hashMCInst ( const MCInst MCI)

◆ hashMCOperand()

hash_code llvm::mca::hashMCOperand ( const MCOperand MCO)

◆ hasResourceHazard()

static bool llvm::mca::hasResourceHazard ( const ResourceManager RM,
const InstRef IR 

Definition at line 79 of file InOrderIssueStage.cpp.

References llvm::dbgs(), IR, and LLVM_DEBUG.

◆ initializeUsedResources()

static void llvm::mca::initializeUsedResources ( InstrDesc ID,
const MCSchedClassDesc SCDesc,
const MCSubtargetInfo STI,
ArrayRef< uint64_t ProcResourceMasks 

◆ opcodeHasEEWAndEMULInfo()

bool llvm::mca::opcodeHasEEWAndEMULInfo ( unsigned short  Opcode)

◆ operator<<()

raw_ostream & llvm::mca::operator<< ( raw_ostream OS,
const InstRef IR 

Definition at line 749 of file Instruction.h.

References IR, and OS.

◆ selectImpl()

static uint64_t llvm::mca::selectImpl ( uint64_t  CandidateMask,
uint64_t NextInSequenceMask 

Definition at line 26 of file ResourceManager.cpp.

References getResourceStateIndex().

Referenced by llvm::mca::DefaultResourceStrategy::select().


llvm::mca::STATISTIC ( NumVariantInst  ,
"Number of MCInsts that doesn't have static Desc"   

◆ toHWStallEventType()

HWStallEvent::GenericEventType llvm::mca::toHWStallEventType ( Scheduler::Status  Status)

◆ verifyInstructionEliminated()

static void llvm::mca::verifyInstructionEliminated ( const InstRef IR)

◆ verifyOperands()

static Error llvm::mca::verifyOperands ( const MCInstrDesc MCDesc,
const MCInst MCI 

Variable Documentation


constexpr int llvm::mca::UNKNOWN_CYCLES = -512