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15 #ifndef LLVM_MCA_INSTRUCTION_H
16 #define LLVM_MCA_INSTRUCTION_H
42 enum MCAOperandType :
unsigned char {
67 bool isValid()
const {
return Kind != kInvalid; }
68 bool isReg()
const {
return Kind == kRegister; }
69 bool isImm()
const {
return Kind == kImmediate; }
70 bool isSFPImm()
const {
return Kind == kSFPImmediate; }
71 bool isDFPImm()
const {
return Kind == kDFPImmediate; }
75 assert(
isReg() &&
"This is not a register operand!");
107 Op.Kind = kImmediate;
114 Op.Kind = kSFPImmediate;
121 Op.Kind = kDFPImmediate;
215 bool ClearsSuperRegs;
234 unsigned DependentWriteCyclesLeft;
249 bool clearsSuperRegs =
false,
bool writesZero =
false)
250 : WD(&Desc), CyclesLeft(
UNKNOWN_CYCLES), RegisterID(RegID), PRFID(0),
251 ClearsSuperRegs(clearsSuperRegs), WritesZero(writesZero),
252 IsEliminated(
false), DependentWrite(nullptr), PartialWrite(nullptr),
253 DependentWriteCyclesLeft(0), CRD() {}
265 return DependentWriteCyclesLeft;
281 unsigned NumUsers =
Users.size();
295 return !CyclesLeft || CyclesLeft <
getLatency();
306 assert(
Users.empty() &&
"Write is in an inconsistent state.");
311 void setPRF(
unsigned PRF) { PRFID = PRF; }
335 unsigned DependentWrites;
344 unsigned TotalCycles;
353 bool IndependentFromDef;
357 : RD(&Desc), RegisterID(RegID), PRFID(0), DependentWrites(0),
367 bool isPending()
const {
return !IndependentFromDef && CyclesLeft > 0; }
377 DependentWrites = Writes;
395 CycleSegment(
unsigned StartCycle,
unsigned EndCycle,
bool IsReserved =
false)
396 : Begin(StartCycle), End(EndCycle),
Reserved(IsReserved) {}
407 return Begin <
Other.Begin;
418 unsigned size()
const {
return End - Begin; };
424 unsigned begin()
const {
return Begin; }
425 unsigned end()
const {
return End; }
426 void setEnd(
unsigned NewEnd) { End = NewEnd; }
502 bool IsOptimizableMove;
513 std::vector<MCAOperand> Operands;
519 bool IsALoadBarrier : 1;
520 bool IsAStoreBarrier : 1;
525 bool HasSideEffects : 1;
533 IsALoadBarrier(
false), IsAStoreBarrier(
false) {}
553 return Op.getIndex() == Idx;
568 unsigned NumUsers = 0;
570 NumUsers +=
Def.getNumUsers();
578 bool isMemOp()
const {
return MayLoad || MayStore; }
612 enum InstrStage
Stage;
650 UsedBuffers(
D.UsedBuffers), CriticalRegDep(), CriticalMemDep(),
651 CriticalResourceMask(0), IsEliminated(
false) {}
706 CriticalMemDep = MemDep;
711 CriticalResourceMask = ResourceMask;
721 std::pair<unsigned, Instruction *> Data;
738 explicit operator bool()
const {
return Data.second !=
nullptr; }
758 #endif // LLVM_MCA_INSTRUCTION_H
uint64_t getDFPImm() const
bool isZeroLatency() const
raw_ostream & operator<<(raw_ostream &OS, const InstRef &IR)
unsigned MustIssueImmediately
This is an optimization pass for GlobalISel generic memory operations.
void dispatch(unsigned RCUTokenID)
CycleSegment & operator--()
InstRef(unsigned Index, Instruction *I)
bool operator<(const CycleSegment &Other) const
SmallVector< WriteDescriptor, 2 > Writes
ArrayRef< WriteState > getDefs() const
void setHasSideEffects(bool newVal)
void setEnd(unsigned NewEnd)
void setRegisterID(const MCPhysReg RegID)
Instruction(const InstrDesc &D, const unsigned Opcode)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
void subtract(unsigned Cycles)
unsigned getRegisterFileID() const
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getDependentWriteCyclesLeft() const
void setIndependentFromDef()
WriteState & operator=(const WriteState &Other)=default
unsigned SClassOrWriteResourceID
void setCriticalResourceMask(uint64_t ResourceMask)
unsigned getLSUTokenID() const
int getCyclesLeft() const
void setStoreBarrier(bool IsBarrier)
unsigned getLatency() const
An instruction propagated through the simulated instruction pipeline.
bool overlaps(const CycleSegment &CS) const
bool isEliminated() const
SmallVectorImpl< WriteState > & getDefs()
SmallPtrSet< MachineInstr *, 2 > Uses
CycleSegment(unsigned StartCycle, unsigned EndCycle, bool IsReserved=false)
Instruction * getInstruction()
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const CriticalDependency & getCriticalRegDep() const
bool isImplicitRead() const
void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles)
void setMayStore(bool newVal)
unsigned getSchedClass() const
unsigned getNumUsers() const
bool hasDependentUsers() const
void setRetireOOO(bool newVal)
bool getHasSideEffects() const
A representation of an mca::Instruction operand for use in mca::CustomBehaviour.
void execute(unsigned IID)
void setPRF(unsigned PRF)
const CriticalDependency & getCriticalRegDep() const
unsigned getSourceIndex() const
uint64_t getCriticalResourceMask() const
const CriticalDependency & getCriticalMemDep() const
SmallVector< std::pair< uint64_t, ResourceUsage >, 4 > Resources
uint64_t UsedProcResGroups
ArrayRef< ReadState > getUses() const
A possibly irreducible generalization of a Loop.
Tracks register operand latency in cycles.
This class implements an extremely fast bulk output stream that can only output to a stream.
Statically lint checks LLVM IR
int getCyclesLeft() const
void setBeginGroup(bool newVal)
A critical data dependency descriptor.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
void addUser(unsigned IID, ReadState *Use, int ReadAdvance)
unsigned getLatency() const
bool startsAfter(const CycleSegment &CS) const
unsigned getNumUsers() const
mir Rename Register Operands
Base class for instructions consumed by the simulation pipeline.
void addOperand(const MCAOperand Op)
void setLoadBarrier(bool IsBarrier)
void setEndGroup(bool newVal)
bool getRetireOOO() const
InstructionBase(const InstrDesc &D, const unsigned Opcode)
unsigned HasPartiallyOverlappingGroups
ResourceUsage(CycleSegment Cycles, unsigned Units=1)
const InstrDesc & getDesc() const
An instruction descriptor.
unsigned getNumOperands() const
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool contains(unsigned Cycle) const
unsigned getIndex() const
void print(raw_ostream &OS) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Helper used by class InstrDesc to describe how hardware resources are used.
WriteState(const WriteDescriptor &Desc, MCPhysReg RegID, bool clearsSuperRegs=false, bool writesZero=false)
MCPhysReg getRegisterID() const
unsigned getRCUTokenID() const
unsigned getRegisterFileID() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void setUsedBuffers(uint64_t Mask)
bool clearsSuperRegisters() const
const MCAOperand * getOperand(const unsigned Idx) const
Return the MCAOperand which corresponds to index Idx within the original MCInst.
void setOptimizableMove()
static MCAOperand createSFPImm(uint32_t Val)
constexpr int UNKNOWN_CYCLES
An InstRef contains both a SourceMgr index and Instruction pair.
unsigned getNumMicroOps() const
bool isIndependentFromDef() const
MCPhysReg getRegisterID() const
void setMayLoad(bool newVal)
void setDependentWrites(unsigned Writes)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
static MCAOperand createReg(unsigned Reg)
uint64_t UsedProcResUnits
bool operator<(const InstRef &Other) const
bool getBeginGroup() const
SmallVector< ReadDescriptor, 4 > Reads
void setDependentWrite(const WriteState *Other)
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
unsigned getWriteResourceID() const
void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles)
A register read descriptor.
bool operator==(const InstRef &Other) const
const Instruction * getInstruction() const
const ReadDescriptor & getDescriptor() const
uint32_t getSFPImm() const
void invalidate()
Invalidate this reference.
void setCriticalMemDep(const CriticalDependency &MemDep)
uint64_t getUsedBuffers() const
static MCAOperand createInvalid()
unsigned getReg() const
Returns the register number.
std::optional< std::vector< StOtherPiece > > Other
static MCAOperand createImm(int64_t Val)
const CriticalDependency & getCriticalRegDep() const
bool isImplicitWrite() const
void setIndex(const unsigned Idx)
SmallVectorImpl< ReadState > & getUses()
bool endsBefore(const CycleSegment &CS) const
void clearOptimizableMove()
bool isDispatched() const
bool isAStoreBarrier() const
static MCAOperand createDFPImm(uint64_t Val)
iv Induction Variable Users
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isOptimizableMove() const
unsigned getOpcode() const
bool isImplicitRead() const
bool isALoadBarrier() const
const WriteState * getDependentWrite() const
InstrDesc & operator=(const InstrDesc &Other)=delete
ReadState(const ReadDescriptor &Desc, MCPhysReg RegID)
const CriticalDependency & computeCriticalRegDep()
Tracks uses of a register definition (e.g.
bool isEliminated() const
void setLSUTokenID(unsigned LSUTok)
A Use represents the edge between a Value definition and its users.
bool operator!=(const InstRef &Other) const
A register write descriptor.
void onInstructionIssued(unsigned IID)