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26 DependentWriteCyclesLeft = Cycles;
27 DependentWrite =
nullptr;
40 if (TotalCycles < Cycles) {
47 if (!DependentWrites) {
48 CyclesLeft = TotalCycles;
49 IsReady = !CyclesLeft;
60 for (
const std::pair<ReadState *, int> &
User : Users) {
62 unsigned ReadCycles =
std::max(0, CyclesLeft -
User.second);
76 unsigned ReadCycles =
std::max(0, CyclesLeft - ReadAdvance);
77 User->writeStartEvent(IID, RegisterID, ReadCycles);
81 Users.emplace_back(
User, ReadAdvance);
86 User->writeStartEvent(IID, RegisterID,
std::max(0, CyclesLeft));
90 assert(!PartialWrite &&
"PartialWrite already set!");
92 User->setDependentWrite(
this);
102 if (DependentWriteCyclesLeft)
103 DependentWriteCyclesLeft--;
108 if (DependentWrites && TotalCycles) {
119 IsReady = !CyclesLeft;
139 if (CriticalRegDep.
Cycles)
140 return CriticalRegDep;
142 unsigned MaxLatency = 0;
145 if (WriteCRD.
Cycles > MaxLatency)
146 CriticalRegDep = WriteCRD;
151 if (ReadCRD.
Cycles > MaxLatency)
152 CriticalRegDep = ReadCRD;
155 return CriticalRegDep;
160 Stage = IS_DISPATCHED;
161 RCUTokenID = RCUToken;
170 Stage = IS_EXECUTING;
176 WS.onInstructionIssued(IID);
184 assert(
Stage == IS_READY &&
"Invalid internal state!");
207 return Use.isPending() ||
Use.isReady();
243 assert(CyclesLeft &&
"Instruction already executed?");
This class represents lattice values for constants.
void dispatch(unsigned RCUTokenID)
const WriteState * getWriteState() const
unsigned getLatency() const
unsigned getSourceIndex() const
SmallVectorImpl< WriteState > & getDefs()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles)
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
void execute(unsigned IID)
Tracks register operand latency in cycles.
int getCyclesLeft() const
A critical data dependency descriptor.
void addUser(unsigned IID, ReadState *Use, int ReadAdvance)
unsigned getLatency() const
MCPhysReg getRegisterID() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
constexpr int UNKNOWN_CYCLES
void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles)
SmallVectorImpl< ReadState > & getUses()
bool isDispatched() const
Align max(MaybeAlign Lhs, Align Rhs)
const CriticalDependency & computeCriticalRegDep()
Tracks uses of a register definition (e.g.
A Use represents the edge between a Value definition and its users.
void onInstructionIssued(unsigned IID)