LLVM 17.0.0git
RISCVCustomBehaviour.cpp
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1//===------------------- RISCVCustomBehaviour.cpp ---------------*-C++ -* -===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file implements methods from the RISCVCustomBehaviour class.
11///
12//===----------------------------------------------------------------------===//
13
16#include "RISCVInstrInfo.h"
19#include "llvm/Support/Debug.h"
20
21#define DEBUG_TYPE "llvm-mca-riscv-custombehaviour"
22
23// This brings in a table with primary key of
24// base instruction opcode and lmul and maps
25// to the opcode of the pseudo instruction.
27using namespace llvm;
28using namespace llvm::RISCV;
29
30struct PseudoInfo {
33 uint8_t VLMul;
34};
35
36#define GET_RISCVVInversePseudosTable_IMPL
37#define GET_RISCVVInversePseudosTable_DECL
38#include "RISCVGenSearchableTables.inc"
39
40} // end namespace RISCVVInversePseudosTable
41
42namespace llvm {
43namespace mca {
44
46
48 // Return true if not one of the valid LMUL strings
50 .Cases("M1", "M2", "M4", "M8", "MF2", "MF4", "MF8", true)
51 .Default(false);
52}
53
55 // assertion prevents us from needing llvm_unreachable in the StringSwitch
56 // below
58 "Cannot get LMUL because invalid Data value");
59 // These are the LMUL values that are used in RISC-V tablegen
61 .Case("M1", 0b000)
62 .Case("M2", 0b001)
63 .Case("M4", 0b010)
64 .Case("M8", 0b011)
65 .Case("MF2", 0b101)
66 .Case("MF4", 0b110)
67 .Case("MF8", 0b111);
68}
69
71 llvm::StringRef Type) const {
72 // Currently, only support for RISCVLMULInstrument type
74}
75
80 LLVM_DEBUG(dbgs() << "RVCB: Unknown instrumentation Desc: " << Desc
81 << '\n');
82 return nullptr;
83 }
85 LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": "
86 << Data << '\n');
87 return nullptr;
88 }
89 return std::make_unique<RISCVLMULInstrument>(Data);
90}
91
93 const MCInstrInfo &MCII, const MCInst &MCI,
94 const llvm::SmallVector<Instrument *> &IVec) const {
95 unsigned short Opcode = MCI.getOpcode();
96 unsigned SchedClassID = MCII.get(Opcode).getSchedClass();
97
98 for (const auto &I : IVec) {
99 // Unknown Instrument kind
100 if (I->getDesc() == RISCVLMULInstrument::DESC_NAME) {
101 uint8_t LMUL = static_cast<RISCVLMULInstrument *>(I)->getLMUL();
103 RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL);
104 // Not a RVV instr
105 if (!RVV) {
107 dbgs()
108 << "RVCB: Could not find PseudoInstruction for Opcode "
109 << MCII.getName(Opcode) << ", LMUL=" << I->getData()
110 << ". Ignoring instrumentation and using original SchedClassID="
111 << SchedClassID << '\n');
112 return SchedClassID;
113 }
114
115 // Override using pseudo
116 LLVM_DEBUG(dbgs() << "RVCB: Found Pseudo Instruction for Opcode "
117 << MCII.getName(Opcode) << ", LMUL=" << I->getData()
118 << ". Overriding original SchedClassID=" << SchedClassID
119 << " with " << MCII.getName(RVV->Pseudo) << '\n');
120 return MCII.get(RVV->Pseudo).getSchedClass();
121 }
122 }
123
124 // Unknown Instrument kind
126 dbgs() << "RVCB: Did not use instrumentation to override Opcode.\n");
127 return SchedClassID;
128}
129
130} // namespace mca
131} // namespace llvm
132
133using namespace llvm;
134using namespace mca;
135
136static InstrumentManager *
138 const MCInstrInfo &MCII) {
139 return new RISCVInstrumentManager(STI, MCII);
140}
141
142/// Extern function to initialize the targets for the RISC-V backend
148}
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
#define LLVM_DEBUG(X)
Definition: Debug.h:101
#define I(x, y, z)
Definition: MD5.cpp:58
static InstrumentManager * createRISCVInstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMCA()
Extern function to initialize the targets for the RISC-V backend.
This file defines the RISCVCustomBehaviour class which inherits from CustomBehaviour.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:601
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:70
Generic base class for all target subtargets.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
Definition: StringSwitch.h:90
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
This class allows targets to optionally customize the logic that resolves scheduling class IDs.
StringRef getData() const
bool supportsInstrumentType(StringRef Type) const override
unsigned getSchedClassID(const MCInstrInfo &MCII, const MCInst &MCI, const SmallVector< Instrument * > &IVec) const override
Using the Instrument, returns a SchedClassID to use instead of the SchedClassID that belongs to the M...
UniqueInstrument createInstrument(StringRef Desc, StringRef Data) override
Create a Instrument for RISC-V target.
static bool isDataValid(StringRef Data)
static const StringRef DESC_NAME
std::unique_ptr< Instrument > UniqueInstrument
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheRISCV32Target()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
Target & getTheRISCV64Target()
static void RegisterInstrumentManager(Target &T, Target::InstrumentManagerCtorTy Fn)
RegisterInstrumentManager - Register an InstrumentManager implementation for the given target.