21#define DEBUG_TYPE "llvm-mca-riscv-custombehaviour"
36#define GET_RISCVVInversePseudosTable_IMPL
37#define GET_RISCVVInversePseudosTable_DECL
38#include "RISCVGenSearchableTables.inc"
50 .
Cases(
"M1",
"M2",
"M4",
"M8",
"MF2",
"MF4",
"MF8",
true)
58 "Cannot get LMUL because invalid Data value");
80 LLVM_DEBUG(
dbgs() <<
"RVCB: Unknown instrumentation Desc: " << Desc
85 LLVM_DEBUG(
dbgs() <<
"RVCB: Bad data for instrument kind " << Desc <<
": "
89 return std::make_unique<RISCVLMULInstrument>(
Data);
98 for (
const auto &
I : IVec) {
103 RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL);
108 <<
"RVCB: Could not find PseudoInstruction for Opcode "
110 <<
". Ignoring instrumentation and using original SchedClassID="
111 << SchedClassID <<
'\n');
118 <<
". Overriding original SchedClassID=" << SchedClassID
126 dbgs() <<
"RVCB: Did not use instrumentation to override Opcode.\n");
#define LLVM_EXTERNAL_VISIBILITY
static InstrumentManager * createRISCVInstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMCA()
Extern function to initialize the targets for the RISC-V backend.
This file defines the RISCVCustomBehaviour class which inherits from CustomBehaviour.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Generic base class for all target subtargets.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
The instances of the Type class are immutable: once they are created, they are never changed.
This class allows targets to optionally customize the logic that resolves scheduling class IDs.
StringRef getData() const
bool supportsInstrumentType(StringRef Type) const override
unsigned getSchedClassID(const MCInstrInfo &MCII, const MCInst &MCI, const SmallVector< Instrument * > &IVec) const override
Using the Instrument, returns a SchedClassID to use instead of the SchedClassID that belongs to the M...
UniqueInstrument createInstrument(StringRef Desc, StringRef Data) override
Create a Instrument for RISC-V target.
static bool isDataValid(StringRef Data)
static const StringRef DESC_NAME
std::unique_ptr< Instrument > UniqueInstrument
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheRISCV32Target()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Target & getTheRISCV64Target()
static void RegisterInstrumentManager(Target &T, Target::InstrumentManagerCtorTy Fn)
RegisterInstrumentManager - Register an InstrumentManager implementation for the given target.