16#ifndef LLVM_MCA_STAGES_INSTRUCTIONTABLES_H
17#define LLVM_MCA_STAGES_INSTRUCTIONTABLES_H
35 : SM(Model), Masks(Model.getNumProcResourceKinds()) {
Legalize the Machine IR a function s Machine IR
A scheduler for Processor Resource Units and Processor Resource Groups.
This file defines the SmallVector class.
This file defines a stage.
Lightweight error class with error context and mandatory checking.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An InstRef contains both a SourceMgr index and Instruction pair.
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
bool hasWorkToComplete() const override
Returns true if some instructions are still executing this stage.
InstructionTables(const MCSchedModel &Model)
Helper functions used by various pipeline components.
void computeProcResourceMasks(const MCSchedModel &SM, MutableArrayRef< uint64_t > Masks)
Populates vector Masks with processor resource masks.
This is an optimization pass for GlobalISel generic memory operations.
Machine model for scheduling, bundling, and heuristics.