17 #define DEBUG_TYPE "llvm-mca"
23 : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
24 AvailableEntries(SM.isOutOfOrder() ? SM.MicroOpBufferSize : 0),
25 MaxRetirePerCycle(0) {
27 "RetireControlUnit is not available for in-order processors");
37 NumROBEntries = AvailableEntries;
38 assert(NumROBEntries &&
"Invalid reorder buffer size!");
39 Queue.resize(2 * NumROBEntries);
46 assert((AvailableEntries >= Entries) &&
"Reorder Buffer unavailable!");
48 unsigned TokenID = NextAvailableSlotIdx;
49 Queue[NextAvailableSlotIdx] = {
IR, Entries,
false};
50 NextAvailableSlotIdx +=
std::max(1U, Entries);
51 NextAvailableSlotIdx %= Queue.size();
54 AvailableEntries -= Entries;
62 assert(Inst &&
"Invalid RUToken in the RCU queue.");
67 unsigned RetireControlUnit::computeNextSlotIdx()
const {
69 unsigned NextSlotIdx = CurrentInstructionSlotIdx +
std::max(1U, Current.
NumSlots);
70 return NextSlotIdx % Queue.size();
74 return Queue[computeNextSlotIdx()];
83 CurrentInstructionSlotIdx %= Queue.size();
84 AvailableEntries += Current.
NumSlots;
85 Current = {
InstRef(), 0U,
false };
89 assert(Queue.size() > TokenID);
90 assert(Queue[TokenID].
IR.getInstruction() &&
"Instruction was not dispatched!");
91 assert(Queue[TokenID].Executed ==
false &&
"Instruction already executed!");
92 Queue[TokenID].Executed =
true;
97 dbgs() <<
"Retire Unit: { Total ROB Entries =" << NumROBEntries
98 <<
", Available ROB entries=" << AvailableEntries <<
" }\n";