Go to the documentation of this file.
56 cl::desc(
"enable coalescing of duplicate branches for PPC"));
59 cl::desc(
"Disable CTR loops for PPC"));
63 cl::desc(
"Disable PPC loop instr form prep"));
71 cl::desc(
"Disable VSX Swap Removal for PPC"));
75 cl::desc(
"Disable machine peepholes for PPC"));
79 cl::desc(
"Enable optimizations on complex GEPs"),
84 cl::desc(
"enable software prefetching on PPC"),
89 cl::desc(
"Add extra TOC register dependencies"),
94 cl::desc(
"Enable the machine combiner pass"),
99 cl::desc(
"Expand eligible cr-logical binary ops to branches"),
103 "enable-ppc-gen-scalar-mass",
cl::init(
false),
104 cl::desc(
"Enable lowering math functions to their corresponding MASS "
175 if (
is64Bit && (
T.isOSAIX() ||
T.isOSLinux()))
176 Ret +=
"-S128-v256:256:256-v512:512:512";
183 std::string FullFS = std::string(
FS);
188 FullFS =
"+64bit," + FullFS;
195 FullFS =
"+crbits," + FullFS;
202 FullFS =
"+invariant-function-descriptors," + FullFS;
204 FullFS =
"+invariant-function-descriptors";
209 FullFS =
"+aix," + FullFS;
219 return std::make_unique<TargetLoweringObjectFileXCOFF>();
221 return std::make_unique<PPC64LinuxTargetObjectFile>();
226 if (
Options.MCOptions.getABIName().startswith(
"elfv1"))
228 else if (
Options.MCOptions.getABIName().startswith(
"elfv2"))
232 "Unknown target-abi option!");
237 switch (TT.getArch()) {
250 "Invalid relocation model for AIX.");
279 assert(TT.isOSBinFormatELF() &&
"All remaining PPC OSes are ELF based.");
281 if (TT.isArch32Bit())
284 assert(TT.isArch64Bit() &&
"Unsupported PPC architecture.");
293 std::make_unique<PPCPreRASchedStrategy>(
C) :
294 std::make_unique<GenericScheduler>(
C));
297 if (
ST.hasStoreFusion())
310 std::make_unique<PPCPostRASchedStrategy>(
C) :
311 std::make_unique<PostGenericScheduler>(
C),
true);
313 if (
ST.hasStoreFusion())
344 Attribute CPUAttr =
F.getFnAttribute(
"target-cpu");
345 Attribute FSAttr =
F.getFnAttribute(
"target-features");
357 bool SoftFloat =
F.getFnAttribute(
"use-soft-float").getValueAsBool();
361 FS +=
FS.empty() ?
"-hard-float" :
",-hard-float";
363 auto &
I = SubtargetMap[CPU +
FS];
369 I = std::make_unique<PPCSubtarget>(
400 return getTM<PPCTargetMachine>();
403 void addIRPasses()
override;
404 bool addPreISel()
override;
405 bool addILPOpts()
override;
406 bool addInstSelector()
override;
407 void addMachineSSAOptimization()
override;
408 void addPreRegAlloc()
override;
409 void addPreSched2()
override;
410 void addPreEmitPass()
override;
411 void addPreEmitPass2()
override;
413 bool addIRTranslator()
override;
414 bool addLegalizeMachineIR()
override;
415 bool addRegBankSelect()
override;
416 bool addGlobalInstructionSelect()
override;
431 return new PPCPassConfig(*
this, PM);
434 void PPCPassConfig::addIRPasses() {
470 bool PPCPassConfig::addPreISel() {
480 bool PPCPassConfig::addILPOpts() {
489 bool PPCPassConfig::addInstSelector() {
502 void PPCPassConfig::addMachineSSAOptimization() {
524 void PPCPassConfig::addPreRegAlloc() {
532 if (getPPCTargetMachine().isPositionIndependent()) {
557 void PPCPassConfig::addPreSched2() {
562 void PPCPassConfig::addPreEmitPass() {
570 void PPCPassConfig::addPreEmitPass2() {
585 assert(Endianness != Endian::NOT_DETECTED &&
586 "Unable to determine endianness");
587 return Endianness == Endian::LITTLE;
592 "Run PowerPC PreRA specific scheduler",
597 "Run PowerPC PostRA specific scheduler",
601 bool PPCPassConfig::addIRTranslator() {
606 bool PPCPassConfig::addLegalizeMachineIR() {
611 bool PPCPassConfig::addRegBankSelect() {
616 bool PPCPassConfig::addGlobalInstructionSelect() {
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
void initializePPCPreEmitPeepholePass(PassRegistry &)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
static ScheduleDAGInstrs * createPPCPostMachineScheduler(MachineSchedContext *C)
void initializePPCGenScalarMASSEntriesPass(PassRegistry &)
~PPCTargetMachine() override
This is an optimization pass for GlobalISel generic memory operations.
constexpr support::endianness Endianness
The endianness of all multi-byte encoded values in MessagePack.
bool isValid() const
Return true if the attribute is any kind of attribute.
static cl::opt< bool > EnablePPCGenScalarMASSEntries("enable-ppc-gen-scalar-mass", cl::init(false), cl::desc("Enable lowering math functions to their corresponding MASS " "(scalar) entries"), cl::Hidden)
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
void initializePPCVSXFMAMutatePass(PassRegistry &)
PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
static bool is64Bit(const char *name)
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
Target - Wrapper for Target specific information.
MachineSchedRegistry provides a selection of available machine instruction schedulers.
FunctionPass * createPPCExpandISELPass()
FunctionPass * createPPCLoopInstrFormPrepPass(PPCTargetMachine &TM)
Triple - Helper class for working with autoconf configuration names.
FunctionPass * createPPCBoolRetToIntPass()
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
bool isLittleEndian() const
static std::string getDataLayoutString(const Triple &T)
Return the datalayout string of a subtarget.
static const char * getManglingComponent(const Triple &T)
std::unique_ptr< ScheduleDAGMutation > createPowerPCMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createPowerPCMacroFusionDAGMutation()); to PPCPassConfig::...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
static ScheduleDAGInstrs * createPPCMachineScheduler(MachineSchedContext *C)
FunctionPass * createPPCEarlyReturnPass()
FunctionPass * createPPCCTRLoopsVerify()
void initializePPCVSXCopyPass(PassRegistry &)
void initializePPCLoopInstrFormPrepPass(PassRegistry &)
void initializePPCExpandAtomicPseudoPass(PassRegistry &)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
static cl::opt< bool > DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden, cl::desc("Disable PPC loop instr form prep"))
void initializePPCLowerMASSVEntriesPass(PassRegistry &)
Target & getThePPC64LETarget()
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static cl::opt< bool > DisableMIPeephole("disable-ppc-peephole", cl::Hidden, cl::desc("Disable machine peepholes for PPC"))
(vector float) vec_cmpeq(*A, *B) C
static bool isLittleEndianTriple(const Triple &T)
std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
ModulePass * createPPCGenScalarMASSEntriesPass()
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
This pass is responsible for selecting generic machine instructions to target-specific instructions.
static cl::opt< bool > EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps", cl::desc("Add extra TOC register dependencies"), cl::init(true), cl::Hidden)
RegisterTargetMachine - Helper template for registering a target machine implementation,...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
void initializePPCBSelPass(PassRegistry &)
int getNumOccurrences() const
FunctionPass * createPPCCTRLoopsPass()
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
static cl::opt< bool > EnablePrefetch("enable-ppc-prefetching", cl::desc("enable software prefetching on PPC"), cl::init(false), cl::Hidden)
void initializePPCTOCRegDepsPass(PassRegistry &)
StringRef getValueAsString() const
Return the attribute's value as a string.
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
FunctionPass * createPPCVSXCopyPass()
Target-Independent Code Generator Pass Configuration Options.
const PPCSubtarget * getSubtargetImpl() const =delete
static cl::opt< bool > DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden, cl::desc("Disable VSX Swap Removal for PPC"))
static MachineSchedRegistry PPCPreRASchedRegistry("ppc-prera", "Run PowerPC PreRA specific scheduler", createPPCMachineScheduler)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget()
void initializePPCMIPeepholePass(PassRegistry &)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
static cl::opt< bool > EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden, cl::desc("enable coalescing of duplicate branches for PPC"))
ModulePass * createPPCLowerMASSVEntriesPass()
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_EXTERNAL_VISIBILITY
static cl::opt< bool > EnableGEPOpt("ppc-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(true))
FunctionPass * createPPCTLSDynamicCallPass()
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
initializer< Ty > init(const Ty &Val)
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
FunctionPass * createPPCTOCRegDepsPass()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static cl::opt< bool > DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, cl::desc("Disable CTR loops for PPC"))
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
static cl::opt< bool > VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"))
static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT, Optional< CodeModel::Model > CM, bool JIT)
static MachineSchedRegistry PPCPostRASchedRegistry("ppc-postra", "Run PowerPC PostRA specific scheduler", createPPCPostMachineScheduler)
void initializePPCCTRLoopsVerifyPass(PassRegistry &)
FunctionPass * createPPCBranchSelectionPass()
FunctionPass * createPPCPreEmitPeepholePass()
void initializePPCTLSDynamicCallPass(PassRegistry &)
StringRef - Represent a constant reference to a string, i.e.
FunctionPass * createHardwareLoopsPass()
Create Hardware Loop pass.
static cl::opt< bool > ReduceCRLogical("ppc-reduce-cr-logicals", cl::desc("Expand eligible cr-logical binary ops to branches"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
FunctionPass * createPPCBranchCoalescingPass()
createPPCBranchCoalescingPass - returns an instance of the Branch Coalescing Pass
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Target & getThePPC64Target()
FunctionPass * createPPCMIPeepholePass()
FunctionPass * createPPCVSXSwapRemovalPass()
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
FunctionPass * createPPCReduceCRLogicalsPass()
void initializePPCExpandISELPass(PassRegistry &)
This class describes a target machine that is implemented with the LLVM target-independent code gener...
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Common code between 32-bit and 64-bit PowerPC targets.
static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT, const TargetOptions &Options)
Target & getThePPC32LETarget()
void initializePPCEarlyReturnPass(PassRegistry &)
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
void initializePPCCTRLoopsPass(PassRegistry &)
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
void initializePPCBoolRetToIntPass(PassRegistry &)
const Triple & getTargetTriple() const
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
void initializePPCBranchCoalescingPass(PassRegistry &)
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
const char LLVMTargetMachineRef TM
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, const Triple &TT)
FunctionPass * createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL)
createPPCISelDag - This pass converts a legalized DAG into a PowerPC-specific DAG,...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
A ScheduleDAG for scheduling lists of MachineInstr.
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
void initializePPCReduceCRLogicalsPass(PassRegistry &)
void initializePPCVSXSwapRemovalPass(PassRegistry &)
FunctionPass * createPPCExpandAtomicPseudoPass()
FunctionPass * createLoopDataPrefetchPass()
Target & getThePPC32Target()