LLVM  15.0.0git
PPCTargetMachine.cpp
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1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCMacroFusion.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetObjectFile.h"
20 #include "PPCTargetTransformInfo.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/Triple.h"
34 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/InitializePasses.h"
40 #include "llvm/MC/TargetRegistry.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include <cassert>
48 #include <memory>
49 #include <string>
50 
51 using namespace llvm;
52 
53 
54 static cl::opt<bool>
55  EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
56  cl::desc("enable coalescing of duplicate branches for PPC"));
57 static cl::
58 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
59  cl::desc("Disable CTR loops for PPC"));
60 
61 static cl::
62 opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden,
63  cl::desc("Disable PPC loop instr form prep"));
64 
65 static cl::opt<bool>
66 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
67  cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
68 
69 static cl::
70 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
71  cl::desc("Disable VSX Swap Removal for PPC"));
72 
73 static cl::
74 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
75  cl::desc("Disable machine peepholes for PPC"));
76 
77 static cl::opt<bool>
78 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
79  cl::desc("Enable optimizations on complex GEPs"),
80  cl::init(true));
81 
82 static cl::opt<bool>
83 EnablePrefetch("enable-ppc-prefetching",
84  cl::desc("enable software prefetching on PPC"),
85  cl::init(false), cl::Hidden);
86 
87 static cl::opt<bool>
88 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
89  cl::desc("Add extra TOC register dependencies"),
90  cl::init(true), cl::Hidden);
91 
92 static cl::opt<bool>
93 EnableMachineCombinerPass("ppc-machine-combiner",
94  cl::desc("Enable the machine combiner pass"),
95  cl::init(true), cl::Hidden);
96 
97 static cl::opt<bool>
98  ReduceCRLogical("ppc-reduce-cr-logicals",
99  cl::desc("Expand eligible cr-logical binary ops to branches"),
100  cl::init(true), cl::Hidden);
101 
103  "enable-ppc-gen-scalar-mass", cl::init(false),
104  cl::desc("Enable lowering math functions to their corresponding MASS "
105  "(scalar) entries"),
106  cl::Hidden);
107 
109  // Register the targets
114 
116 #ifndef NDEBUG
118 #endif
138 }
139 
140 static bool isLittleEndianTriple(const Triple &T) {
141  return T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppcle;
142 }
143 
144 /// Return the datalayout string of a subtarget.
145 static std::string getDataLayoutString(const Triple &T) {
146  bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
147  std::string Ret;
148 
149  // Most PPC* platforms are big endian, PPC(64)LE is little endian.
150  if (isLittleEndianTriple(T))
151  Ret = "e";
152  else
153  Ret = "E";
154 
156 
157  // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
158  // pointers.
159  if (!is64Bit || T.getOS() == Triple::Lv2)
160  Ret += "-p:32:32";
161 
162  // Note, the alignment values for f64 and i64 on ppc64 in Darwin
163  // documentation are wrong; these are correct (i.e. "what gcc does").
164  Ret += "-i64:64";
165 
166  // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
167  if (is64Bit)
168  Ret += "-n32:64";
169  else
170  Ret += "-n32";
171 
172  // Specify the vector alignment explicitly. For v256i1 and v512i1, the
173  // calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
174  // which is 256 and 512 bytes - way over aligned.
175  if (is64Bit && (T.isOSAIX() || T.isOSLinux()))
176  Ret += "-S128-v256:256:256-v512:512:512";
177 
178  return Ret;
179 }
180 
182  const Triple &TT) {
183  std::string FullFS = std::string(FS);
184 
185  // Make sure 64-bit features are available when CPUname is generic
186  if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
187  if (!FullFS.empty())
188  FullFS = "+64bit," + FullFS;
189  else
190  FullFS = "+64bit";
191  }
192 
193  if (OL >= CodeGenOpt::Default) {
194  if (!FullFS.empty())
195  FullFS = "+crbits," + FullFS;
196  else
197  FullFS = "+crbits";
198  }
199 
200  if (OL != CodeGenOpt::None) {
201  if (!FullFS.empty())
202  FullFS = "+invariant-function-descriptors," + FullFS;
203  else
204  FullFS = "+invariant-function-descriptors";
205  }
206 
207  if (TT.isOSAIX()) {
208  if (!FullFS.empty())
209  FullFS = "+aix," + FullFS;
210  else
211  FullFS = "+aix";
212  }
213 
214  return FullFS;
215 }
216 
217 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
218  if (TT.isOSAIX())
219  return std::make_unique<TargetLoweringObjectFileXCOFF>();
220 
221  return std::make_unique<PPC64LinuxTargetObjectFile>();
222 }
223 
225  const TargetOptions &Options) {
226  if (Options.MCOptions.getABIName().startswith("elfv1"))
228  else if (Options.MCOptions.getABIName().startswith("elfv2"))
230 
231  assert(Options.MCOptions.getABIName().empty() &&
232  "Unknown target-abi option!");
233 
234  if (TT.isMacOSX())
236 
237  switch (TT.getArch()) {
238  case Triple::ppc64le:
240  case Triple::ppc64:
242  default:
244  }
245 }
246 
249  assert((!TT.isOSAIX() || !RM || *RM == Reloc::PIC_) &&
250  "Invalid relocation model for AIX.");
251 
252  if (RM)
253  return *RM;
254 
255  // Big Endian PPC and AIX default to PIC.
256  if (TT.getArch() == Triple::ppc64 || TT.isOSAIX())
257  return Reloc::PIC_;
258 
259  // Rest are static by default.
260  return Reloc::Static;
261 }
262 
265  bool JIT) {
266  if (CM) {
267  if (*CM == CodeModel::Tiny)
268  report_fatal_error("Target does not support the tiny CodeModel", false);
269  if (*CM == CodeModel::Kernel)
270  report_fatal_error("Target does not support the kernel CodeModel", false);
271  return *CM;
272  }
273 
274  if (JIT)
275  return CodeModel::Small;
276  if (TT.isOSAIX())
277  return CodeModel::Small;
278 
279  assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based.");
280 
281  if (TT.isArch32Bit())
282  return CodeModel::Small;
283 
284  assert(TT.isArch64Bit() && "Unsupported PPC architecture.");
285  return CodeModel::Medium;
286 }
287 
288 
290  const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
291  ScheduleDAGMILive *DAG =
292  new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
293  std::make_unique<PPCPreRASchedStrategy>(C) :
294  std::make_unique<GenericScheduler>(C));
295  // add DAG Mutations here.
296  DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
297  if (ST.hasStoreFusion())
298  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
299  if (ST.hasFusion())
300  DAG->addMutation(createPowerPCMacroFusionDAGMutation());
301 
302  return DAG;
303 }
304 
307  const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
308  ScheduleDAGMI *DAG =
309  new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
310  std::make_unique<PPCPostRASchedStrategy>(C) :
311  std::make_unique<PostGenericScheduler>(C), true);
312  // add DAG Mutations here.
313  if (ST.hasStoreFusion())
314  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
315  if (ST.hasFusion())
316  DAG->addMutation(createPowerPCMacroFusionDAGMutation());
317  return DAG;
318 }
319 
320 // The FeatureString here is a little subtle. We are modifying the feature
321 // string with what are (currently) non-function specific overrides as it goes
322 // into the LLVMTargetMachine constructor and then using the stored value in the
323 // Subtarget constructor below it.
325  StringRef CPU, StringRef FS,
326  const TargetOptions &Options,
329  CodeGenOpt::Level OL, bool JIT)
330  : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
331  computeFSAdditions(FS, OL, TT), Options,
333  getEffectivePPCCodeModel(TT, CM, JIT), OL),
334  TLOF(createTLOF(getTargetTriple())),
335  TargetABI(computeTargetABI(TT, Options)),
336  Endianness(isLittleEndianTriple(TT) ? Endian::LITTLE : Endian::BIG) {
337  initAsmInfo();
338 }
339 
341 
342 const PPCSubtarget *
344  Attribute CPUAttr = F.getFnAttribute("target-cpu");
345  Attribute FSAttr = F.getFnAttribute("target-features");
346 
347  std::string CPU =
348  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
349  std::string FS =
350  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
351 
352  // FIXME: This is related to the code below to reset the target options,
353  // we need to know whether or not the soft float flag is set on the
354  // function before we can generate a subtarget. We also need to use
355  // it as a key for the subtarget since that can be the only difference
356  // between two functions.
357  bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
358  // If the soft float attribute is set on the function turn on the soft float
359  // subtarget feature.
360  if (SoftFloat)
361  FS += FS.empty() ? "-hard-float" : ",-hard-float";
362 
363  auto &I = SubtargetMap[CPU + FS];
364  if (!I) {
365  // This needs to be done before we create a new subtarget since any
366  // creation will depend on the TM and the code generation flags on the
367  // function that reside in TargetOptions.
369  I = std::make_unique<PPCSubtarget>(
370  TargetTriple, CPU,
371  // FIXME: It would be good to have the subtarget additions here
372  // not necessary. Anything that turns them on/off (overrides) ends
373  // up being put at the end of the feature string, but the defaults
374  // shouldn't require adding them. Fixing this means pulling Feature64Bit
375  // out of most of the target cpus in the .td file and making it set only
376  // as part of initialization via the TargetTriple.
378  }
379  return I.get();
380 }
381 
382 //===----------------------------------------------------------------------===//
383 // Pass Pipeline Configuration
384 //===----------------------------------------------------------------------===//
385 
386 namespace {
387 
388 /// PPC Code Generator Pass Configuration Options.
389 class PPCPassConfig : public TargetPassConfig {
390 public:
391  PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
392  : TargetPassConfig(TM, PM) {
393  // At any optimization level above -O0 we use the Machine Scheduler and not
394  // the default Post RA List Scheduler.
395  if (TM.getOptLevel() != CodeGenOpt::None)
396  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
397  }
398 
399  PPCTargetMachine &getPPCTargetMachine() const {
400  return getTM<PPCTargetMachine>();
401  }
402 
403  void addIRPasses() override;
404  bool addPreISel() override;
405  bool addILPOpts() override;
406  bool addInstSelector() override;
407  void addMachineSSAOptimization() override;
408  void addPreRegAlloc() override;
409  void addPreSched2() override;
410  void addPreEmitPass() override;
411  void addPreEmitPass2() override;
412  // GlobalISEL
413  bool addIRTranslator() override;
414  bool addLegalizeMachineIR() override;
415  bool addRegBankSelect() override;
416  bool addGlobalInstructionSelect() override;
417 
419  createMachineScheduler(MachineSchedContext *C) const override {
421  }
423  createPostMachineScheduler(MachineSchedContext *C) const override {
425  }
426 };
427 
428 } // end anonymous namespace
429 
431  return new PPCPassConfig(*this, PM);
432 }
433 
434 void PPCPassConfig::addIRPasses() {
435  if (TM->getOptLevel() != CodeGenOpt::None)
436  addPass(createPPCBoolRetToIntPass());
437  addPass(createAtomicExpandPass());
438 
439  // Lower generic MASSV routines to PowerPC subtarget-specific entries.
441 
442  // Generate PowerPC target-specific entries for scalar math functions
443  // that are available in IBM MASS (scalar) library.
444  if (TM->getOptLevel() == CodeGenOpt::Aggressive &&
446  TM->Options.PPCGenScalarMASSEntries = EnablePPCGenScalarMASSEntries;
448  }
449 
450  // If explicitly requested, add explicit data prefetch intrinsics.
452  addPass(createLoopDataPrefetchPass());
453 
454  if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
455  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
456  // and lower a GEP with multiple indices to either arithmetic operations or
457  // multiple GEPs with single index.
459  // Call EarlyCSE pass to find and remove subexpressions in the lowered
460  // result.
461  addPass(createEarlyCSEPass());
462  // Do loop invariant code motion in case part of the lowered result is
463  // invariant.
464  addPass(createLICMPass());
465  }
466 
468 }
469 
470 bool PPCPassConfig::addPreISel() {
471  if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::None)
472  addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine()));
473 
474  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
475  addPass(createHardwareLoopsPass());
476 
477  return false;
478 }
479 
480 bool PPCPassConfig::addILPOpts() {
481  addPass(&EarlyIfConverterID);
482 
484  addPass(&MachineCombinerID);
485 
486  return true;
487 }
488 
489 bool PPCPassConfig::addInstSelector() {
490  // Install an instruction selector.
491  addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
492 
493 #ifndef NDEBUG
494  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
495  addPass(createPPCCTRLoopsVerify());
496 #endif
497 
498  addPass(createPPCVSXCopyPass());
499  return false;
500 }
501 
502 void PPCPassConfig::addMachineSSAOptimization() {
503  // PPCBranchCoalescingPass need to be done before machine sinking
504  // since it merges empty blocks.
505  if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
508  // For little endian, remove where possible the vector swap instructions
509  // introduced at code generation to normalize vector element order.
510  if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
512  addPass(createPPCVSXSwapRemovalPass());
513  // Reduce the number of cr-logical ops.
514  if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
516  // Target-specific peephole cleanups performed after instruction
517  // selection.
518  if (!DisableMIPeephole) {
519  addPass(createPPCMIPeepholePass());
521  }
522 }
523 
524 void PPCPassConfig::addPreRegAlloc() {
525  if (getOptLevel() != CodeGenOpt::None) {
529  }
530 
531  // FIXME: We probably don't need to run these for -fPIE.
532  if (getPPCTargetMachine().isPositionIndependent()) {
533  // FIXME: LiveVariables should not be necessary here!
534  // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
535  // LiveVariables. This (unnecessary) dependency has been removed now,
536  // however a stage-2 clang build fails without LiveVariables computed here.
537  addPass(&LiveVariablesID);
538  addPass(createPPCTLSDynamicCallPass());
539  }
541  addPass(createPPCTOCRegDepsPass());
542 
543  // Run CTR loops pass before MachinePipeliner pass.
544  // MachinePipeliner will pipeline all instructions before the terminator, but
545  // we don't want DecreaseCTRPseudo to be pipelined.
546  // Note we may lose some MachinePipeliner opportunities if we run CTR loops
547  // generation pass before MachinePipeliner and the loop is converted back to
548  // a normal loop. We can revisit this later for running PPCCTRLoops after
549  // MachinePipeliner and handling DecreaseCTRPseudo in MachinePipeliner pass.
550  if (getOptLevel() != CodeGenOpt::None)
551  addPass(createPPCCTRLoopsPass());
552 
553  if (getOptLevel() != CodeGenOpt::None)
554  addPass(&MachinePipelinerID);
555 }
556 
557 void PPCPassConfig::addPreSched2() {
558  if (getOptLevel() != CodeGenOpt::None)
559  addPass(&IfConverterID);
560 }
561 
562 void PPCPassConfig::addPreEmitPass() {
563  addPass(createPPCPreEmitPeepholePass());
564  addPass(createPPCExpandISELPass());
565 
566  if (getOptLevel() != CodeGenOpt::None)
567  addPass(createPPCEarlyReturnPass());
568 }
569 
570 void PPCPassConfig::addPreEmitPass2() {
571  // Schedule the expansion of AMOs at the last possible moment, avoiding the
572  // possibility for other passes to break the requirements for forward
573  // progress in the LL/SC block.
575  // Must run branch selection immediately preceding the asm printer.
576  addPass(createPPCBranchSelectionPass());
577 }
578 
581  return TargetTransformInfo(PPCTTIImpl(this, F));
582 }
583 
585  assert(Endianness != Endian::NOT_DETECTED &&
586  "Unable to determine endianness");
587  return Endianness == Endian::LITTLE;
588 }
589 
591 PPCPreRASchedRegistry("ppc-prera",
592  "Run PowerPC PreRA specific scheduler",
594 
596 PPCPostRASchedRegistry("ppc-postra",
597  "Run PowerPC PostRA specific scheduler",
599 
600 // Global ISEL
601 bool PPCPassConfig::addIRTranslator() {
602  addPass(new IRTranslator());
603  return false;
604 }
605 
606 bool PPCPassConfig::addLegalizeMachineIR() {
607  addPass(new Legalizer());
608  return false;
609 }
610 
611 bool PPCPassConfig::addRegBankSelect() {
612  addPass(new RegBankSelect());
613  return false;
614 }
615 
616 bool PPCPassConfig::addGlobalInstructionSelect() {
617  addPass(new InstructionSelect(getOptLevel()));
618  return false;
619 }
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Get a TargetTransformInfo implementation for the target.
Definition: PPCTargetMachine.cpp:580
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Definition: TargetMachine.cpp:186
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Definition: PPCTargetMachine.cpp:305
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Definition: PPCTargetMachine.h:27
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Definition: MsgPack.h:24
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Definition: Attributes.h:182
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Definition: SeparateConstOffsetFromGEP.cpp:498
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Definition: Triple.h:193
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Definition: TargetOptions.h:124
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Definition: PPCTargetMachine.cpp:324
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Definition: MachinePipeliner.cpp:182
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Definition: TargetRegistry.h:145
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Definition: CodeGen.h:28
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Definition: MachineScheduler.h:141
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Definition: TargetTransformInfo.h:168
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Definition: PPCTargetMachine.h:27
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Definition: PPCLoopInstrFormPrep.cpp:351
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Definition: Triple.h:44
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Definition: PPCTargetMachine.cpp:584
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Definition: CommandLine.h:139
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static std::string getDataLayoutString(const Triple &T)
Return the datalayout string of a subtarget.
Definition: PPCTargetMachine.cpp:145
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Definition: DataLayout.cpp:153
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Note that you have to add: DAG.addMutation(createPowerPCMacroFusionDAGMutation()); to PPCPassConfig::...
Definition: PPCMacroFusion.cpp:290
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Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
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Definition: MipsISelLowering.h:119
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Definition: PPCTargetMachine.h:27
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Definition: PPCTargetMachine.cpp:289
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Definition: CodeGen.h:28
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Definition: PPCCTRLoopsVerify.cpp:79
llvm::initializePPCVSXCopyPass
void initializePPCVSXCopyPass(PassRegistry &)
PPCMachineScheduler.h
llvm::initializePPCLoopInstrFormPrepPass
void initializePPCLoopInstrFormPrepPass(PassRegistry &)
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::initializePPCExpandAtomicPseudoPass
void initializePPCExpandAtomicPseudoPass(PassRegistry &)
llvm::PPCTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: PPCTargetMachine.cpp:430
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
DisableInstrFormPrep
static cl::opt< bool > DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden, cl::desc("Disable PPC loop instr form prep"))
llvm::initializePPCLowerMASSVEntriesPass
void initializePPCLowerMASSVEntriesPass(PassRegistry &)
PPCSubtarget.h
CommandLine.h
llvm::getThePPC64LETarget
Target & getThePPC64LETarget()
Definition: PowerPCTargetInfo.cpp:25
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
DisableMIPeephole
static cl::opt< bool > DisableMIPeephole("disable-ppc-peephole", cl::Hidden, cl::desc("Disable machine peepholes for PPC"))
llvm::Legalizer
Definition: Legalizer.h:36
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
isLittleEndianTriple
static bool isLittleEndianTriple(const Triple &T)
Definition: PPCTargetMachine.cpp:140
llvm::createCopyConstrainDAGMutation
std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1794
llvm::RegisterCoalescerID
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
Definition: RegisterCoalescer.cpp:410
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:782
llvm::createPPCGenScalarMASSEntriesPass
ModulePass * createPPCGenScalarMASSEntriesPass()
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::Triple::ppc64
@ ppc64
Definition: Triple.h:71
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
EnableExtraTOCRegDeps
static cl::opt< bool > EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps", cl::desc("Add extra TOC register dependencies"), cl::init(true), cl::Hidden)
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1318
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::initializePPCBSelPass
void initializePPCBSelPass(PassRegistry &)
PPC.h
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:395
llvm::createPPCCTRLoopsPass
FunctionPass * createPPCCTRLoopsPass()
Definition: PPCCTRLoops.cpp:93
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:98
llvm::PPCTargetMachine::PPC_ABI_ELFv1
@ PPC_ABI_ELFv1
Definition: PPCTargetMachine.h:27
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:249
EnablePrefetch
static cl::opt< bool > EnablePrefetch("enable-ppc-prefetching", cl::desc("enable software prefetching on PPC"), cl::init(false), cl::Hidden)
llvm::initializePPCTOCRegDepsPass
void initializePPCTOCRegDepsPass(PassRegistry &)
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
PPCMacroFusion.h
PPCTargetObjectFile.h
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
llvm::PPCTargetMachine::Endian
Endian
Definition: PPCTargetMachine.h:28
llvm::createPPCVSXCopyPass
FunctionPass * createPPCVSXCopyPass()
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
InstructionSelector.h
llvm::PPCTargetMachine::getSubtargetImpl
const PPCSubtarget * getSubtargetImpl() const =delete
DisableVSXSwapRemoval
static cl::opt< bool > DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden, cl::desc("Disable VSX Swap Removal for PPC"))
PPCPreRASchedRegistry
static MachineSchedRegistry PPCPreRASchedRegistry("ppc-prera", "Run PowerPC PreRA specific scheduler", createPPCMachineScheduler)
llvm::Triple::ppc64le
@ ppc64le
Definition: Triple.h:72
LLVMInitializePowerPCTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget()
Definition: PPCTargetMachine.cpp:108
llvm::initializePPCMIPeepholePass
void initializePPCMIPeepholePass(PassRegistry &)
llvm::cl::opt< bool >
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
EnableBranchCoalescing
static cl::opt< bool > EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden, cl::desc("enable coalescing of duplicate branches for PPC"))
llvm::createPPCLowerMASSVEntriesPass
ModulePass * createPPCLowerMASSVEntriesPass()
llvm::CodeGenOpt::Default
@ Default
Definition: CodeGen.h:55
llvm::PPCVSXFMAMutateID
char & PPCVSXFMAMutateID
Definition: PPCVSXFMAMutate.cpp:389
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
EnableGEPOpt
static cl::opt< bool > EnableGEPOpt("ppc-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(true))
llvm::PPCTTIImpl
Definition: PPCTargetTransformInfo.h:26
llvm::createPPCTLSDynamicCallPass
FunctionPass * createPPCTLSDynamicCallPass()
Definition: PPCTLSDynamicCall.cpp:237
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:125
I
#define I(x, y, z)
Definition: MD5.cpp:58
PowerPCTargetInfo.h
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:853
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::LiveVariablesID
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
Definition: LiveVariables.cpp:45
TargetPassConfig.h
Localizer.h
llvm::createPPCTOCRegDepsPass
FunctionPass * createPPCTOCRegDepsPass()
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::X86AS::FS
@ FS
Definition: X86.h:192
DisableCTRLoops
static cl::opt< bool > DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, cl::desc("Disable CTR loops for PPC"))
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
VSXFMAMutateEarly
static cl::opt< bool > VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"))
Triple.h
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
getEffectivePPCCodeModel
static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT, Optional< CodeModel::Model > CM, bool JIT)
Definition: PPCTargetMachine.cpp:263
PPCPostRASchedRegistry
static MachineSchedRegistry PPCPostRASchedRegistry("ppc-postra", "Run PowerPC PostRA specific scheduler", createPPCPostMachineScheduler)
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:469
llvm::initializePPCCTRLoopsVerifyPass
void initializePPCCTRLoopsVerifyPass(PassRegistry &)
llvm::createPPCBranchSelectionPass
FunctionPass * createPPCBranchSelectionPass()
llvm::createPPCPreEmitPeepholePass
FunctionPass * createPPCPreEmitPeepholePass()
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
DataLayout.h
llvm::initializePPCTLSDynamicCallPass
void initializePPCTLSDynamicCallPass(PassRegistry &)
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::createHardwareLoopsPass
FunctionPass * createHardwareLoopsPass()
Create Hardware Loop pass.
Definition: HardwareLoops.cpp:543
llvm::Triple::ppcle
@ ppcle
Definition: Triple.h:70
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
IRTranslator.h
ReduceCRLogical
static cl::opt< bool > ReduceCRLogical("ppc-reduce-cr-logicals", cl::desc("Expand eligible cr-logical binary ops to branches"), cl::init(true), cl::Hidden)
EnableMachineCombinerPass
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
llvm::createPPCBranchCoalescingPass
FunctionPass * createPPCBranchCoalescingPass()
createPPCBranchCoalescingPass - returns an instance of the Branch Coalescing Pass
Definition: PPCBranchCoalescing.cpp:193
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
llvm::getThePPC64Target
Target & getThePPC64Target()
Definition: PowerPCTargetInfo.cpp:21
Attributes.h
llvm::createPPCMIPeepholePass
FunctionPass * createPPCMIPeepholePass()
Definition: PPCMIPeephole.cpp:1740
llvm::createPPCVSXSwapRemovalPass
FunctionPass * createPPCVSXSwapRemovalPass()
Definition: PPCVSXSwapRemoval.cpp:1074
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1306
llvm::createPPCReduceCRLogicalsPass
FunctionPass * createPPCReduceCRLogicalsPass()
Definition: PPCReduceCRLogicals.cpp:738
RegBankSelect.h
llvm::initializePPCExpandISELPass
void initializePPCExpandISELPass(PassRegistry &)
Function.h
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:411
llvm::DeadMachineInstructionElimID
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Definition: DeadMachineInstructionElim.cpp:56
llvm::PPCTargetMachine
Common code between 32-bit and 64-bit PowerPC targets.
Definition: PPCTargetMachine.h:25
PPCTargetTransformInfo.h
computeTargetABI
static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT, const TargetOptions &Options)
Definition: PPCTargetMachine.cpp:224
llvm::getThePPC32LETarget
Target & getThePPC32LETarget()
Definition: PowerPCTargetInfo.cpp:17
llvm::initializePPCEarlyReturnPass
void initializePPCEarlyReturnPass(PassRegistry &)
llvm::MachineSchedulerID
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
Definition: MachineScheduler.cpp:213
CodeGen.h
llvm::initializePPCCTRLoopsPass
void initializePPCCTRLoopsPass(PassRegistry &)
Legalizer.h
llvm::createLICMPass
Pass * createLICMPass()
Definition: LICM.cpp:345
MachineScheduler.h
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:197
llvm::initializePPCBoolRetToIntPass
void initializePPCBoolRetToIntPass(PassRegistry &)
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:126
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: PPCTargetMachine.cpp:217
llvm::initializePPCBranchCoalescingPass
void initializePPCBranchCoalescingPass(PassRegistry &)
llvm::MachineCombinerID
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
Definition: MachineCombiner.cpp:129
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::createStoreClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1580
llvm::IRTranslator
Definition: IRTranslator.h:62
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
computeFSAdditions
static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, const Triple &TT)
Definition: PPCTargetMachine.cpp:181
llvm::createPPCISelDag
FunctionPass * createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL)
createPPCISelDag - This pass converts a legalized DAG into a PowerPC-specific DAG,...
Definition: PPCISelDAGToDAG.cpp:7489
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:244
llvm::cl::desc
Definition: CommandLine.h:405
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:390
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::IfConverterID
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
Definition: IfConversion.cpp:434
TargetRegistry.h
llvm::initializePPCReduceCRLogicalsPass
void initializePPCReduceCRLogicalsPass(PassRegistry &)
InitializePasses.h
llvm::initializePPCVSXSwapRemovalPass
void initializePPCVSXSwapRemovalPass(PassRegistry &)
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:97
PPCTargetMachine.h
llvm::createPPCExpandAtomicPseudoPass
FunctionPass * createPPCExpandAtomicPseudoPass()
llvm::createLoopDataPrefetchPass
FunctionPass * createLoopDataPrefetchPass()
Definition: LoopDataPrefetch.cpp:152
llvm::getThePPC32Target
Target & getThePPC32Target()
Definition: PowerPCTargetInfo.cpp:13