LLVM  14.0.0git
PPCMIPeephole.cpp
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1 //===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===---------------------------------------------------------------------===//
8 //
9 // This pass performs peephole optimizations to clean up ugly code
10 // sequences at the MachineInstruction layer. It runs at the end of
11 // the SSA phases, following VSX swap removal. A pass of dead code
12 // elimination follows this one for quick clean-up of any dead
13 // instructions introduced here. Although we could do this as callbacks
14 // from the generic peephole pass, this would have a couple of bad
15 // effects: it might remove optimization opportunities for VSX swap
16 // removal, and it would miss cleanups made possible following VSX
17 // swap removal.
18 //
19 //===---------------------------------------------------------------------===//
20 
23 #include "PPC.h"
24 #include "PPCInstrBuilder.h"
25 #include "PPCInstrInfo.h"
26 #include "PPCMachineFunctionInfo.h"
27 #include "PPCTargetMachine.h"
28 #include "llvm/ADT/Statistic.h"
35 #include "llvm/InitializePasses.h"
36 #include "llvm/Support/Debug.h"
37 
38 using namespace llvm;
39 
40 #define DEBUG_TYPE "ppc-mi-peepholes"
41 
42 STATISTIC(RemoveTOCSave, "Number of TOC saves removed");
43 STATISTIC(MultiTOCSaves,
44  "Number of functions with multiple TOC saves that must be kept");
45 STATISTIC(NumTOCSavesInPrologue, "Number of TOC saves placed in the prologue");
46 STATISTIC(NumEliminatedSExt, "Number of eliminated sign-extensions");
47 STATISTIC(NumEliminatedZExt, "Number of eliminated zero-extensions");
48 STATISTIC(NumOptADDLIs, "Number of optimized ADD instruction fed by LI");
49 STATISTIC(NumConvertedToImmediateForm,
50  "Number of instructions converted to their immediate form");
51 STATISTIC(NumFunctionsEnteredInMIPeephole,
52  "Number of functions entered in PPC MI Peepholes");
53 STATISTIC(NumFixedPointIterations,
54  "Number of fixed-point iterations converting reg-reg instructions "
55  "to reg-imm ones");
56 STATISTIC(NumRotatesCollapsed,
57  "Number of pairs of rotate left, clear left/right collapsed");
58 STATISTIC(NumEXTSWAndSLDICombined,
59  "Number of pairs of EXTSW and SLDI combined as EXTSWSLI");
60 STATISTIC(NumLoadImmZeroFoldedAndRemoved,
61  "Number of LI(8) reg, 0 that are folded to r0 and removed");
62 
63 static cl::opt<bool>
64 FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true),
65  cl::desc("Iterate to a fixed point when attempting to "
66  "convert reg-reg instructions to reg-imm"));
67 
68 static cl::opt<bool>
69 ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true),
70  cl::desc("Convert eligible reg+reg instructions to reg+imm"));
71 
72 static cl::opt<bool>
73  EnableSExtElimination("ppc-eliminate-signext",
74  cl::desc("enable elimination of sign-extensions"),
75  cl::init(false), cl::Hidden);
76 
77 static cl::opt<bool>
78  EnableZExtElimination("ppc-eliminate-zeroext",
79  cl::desc("enable elimination of zero-extensions"),
80  cl::init(false), cl::Hidden);
81 
82 static cl::opt<bool>
83  EnableTrapOptimization("ppc-opt-conditional-trap",
84  cl::desc("enable optimization of conditional traps"),
85  cl::init(false), cl::Hidden);
86 
87 namespace {
88 
89 struct PPCMIPeephole : public MachineFunctionPass {
90 
91  static char ID;
92  const PPCInstrInfo *TII;
93  MachineFunction *MF;
95 
96  PPCMIPeephole() : MachineFunctionPass(ID) {
98  }
99 
100 private:
104  uint64_t EntryFreq;
105 
106  // Initialize class variables.
107  void initialize(MachineFunction &MFParm);
108 
109  // Perform peepholes.
110  bool simplifyCode(void);
111 
112  // Perform peepholes.
113  bool eliminateRedundantCompare(void);
114  bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves);
115  bool combineSEXTAndSHL(MachineInstr &MI, MachineInstr *&ToErase);
116  bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI);
117  void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves,
118  MachineInstr *MI);
119 
120 public:
121 
122  void getAnalysisUsage(AnalysisUsage &AU) const override {
130  }
131 
132  // Main entry point for this pass.
133  bool runOnMachineFunction(MachineFunction &MF) override {
134  initialize(MF);
135  // At this point, TOC pointer should not be used in a function that uses
136  // PC-Relative addressing.
137  assert((MF.getRegInfo().use_empty(PPC::X2) ||
139  "TOC pointer used in a function using PC-Relative addressing!");
140  if (skipFunction(MF.getFunction()))
141  return false;
142  return simplifyCode();
143  }
144 };
145 
146 // Initialize class variables.
148  MF = &MFParm;
149  MRI = &MF->getRegInfo();
150  MDT = &getAnalysis<MachineDominatorTree>();
151  MPDT = &getAnalysis<MachinePostDominatorTree>();
152  MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
153  EntryFreq = MBFI->getEntryFreq();
154  TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
155  LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n");
156  LLVM_DEBUG(MF->dump());
157 }
158 
159 static MachineInstr *getVRegDefOrNull(MachineOperand *Op,
161  assert(Op && "Invalid Operand!");
162  if (!Op->isReg())
163  return nullptr;
164 
165  Register Reg = Op->getReg();
167  return nullptr;
168 
169  return MRI->getVRegDef(Reg);
170 }
171 
172 // This function returns number of known zero bits in output of MI
173 // starting from the most significant bit.
174 static unsigned
175 getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) {
176  unsigned Opcode = MI->getOpcode();
177  if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
178  Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec)
179  return MI->getOperand(3).getImm();
180 
181  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) &&
182  MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
183  return MI->getOperand(3).getImm();
184 
185  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
186  Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec ||
187  Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
188  MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
189  return 32 + MI->getOperand(3).getImm();
190 
191  if (Opcode == PPC::ANDI_rec) {
192  uint16_t Imm = MI->getOperand(2).getImm();
193  return 48 + countLeadingZeros(Imm);
194  }
195 
196  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec ||
197  Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec ||
198  Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8)
199  // The result ranges from 0 to 32.
200  return 58;
201 
202  if (Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec ||
203  Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec)
204  // The result ranges from 0 to 64.
205  return 57;
206 
207  if (Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
208  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
209  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
210  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8)
211  return 48;
212 
213  if (Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
214  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
215  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
216  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8)
217  return 56;
218 
219  if (TII->isZeroExtended(*MI))
220  return 32;
221 
222  return 0;
223 }
224 
225 // This function maintains a map for the pairs <TOC Save Instr, Keep>
226 // Each time a new TOC save is encountered, it checks if any of the existing
227 // ones are dominated by the new one. If so, it marks the existing one as
228 // redundant by setting it's entry in the map as false. It then adds the new
229 // instruction to the map with either true or false depending on if any
230 // existing instructions dominated the new one.
231 void PPCMIPeephole::UpdateTOCSaves(
232  std::map<MachineInstr *, bool> &TOCSaves, MachineInstr *MI) {
233  assert(TII->isTOCSaveMI(*MI) && "Expecting a TOC save instruction here");
234  // FIXME: Saving TOC in prologue hasn't been implemented well in AIX ABI part,
235  // here only support it under ELFv2.
236  if (MF->getSubtarget<PPCSubtarget>().isELFv2ABI()) {
238 
239  MachineBasicBlock *Entry = &MF->front();
240  uint64_t CurrBlockFreq = MBFI->getBlockFreq(MI->getParent()).getFrequency();
241 
242  // If the block in which the TOC save resides is in a block that
243  // post-dominates Entry, or a block that is hotter than entry (keep in mind
244  // that early MachineLICM has already run so the TOC save won't be hoisted)
245  // we can just do the save in the prologue.
246  if (CurrBlockFreq > EntryFreq || MPDT->dominates(MI->getParent(), Entry))
247  FI->setMustSaveTOC(true);
248 
249  // If we are saving the TOC in the prologue, all the TOC saves can be
250  // removed from the code.
251  if (FI->mustSaveTOC()) {
252  for (auto &TOCSave : TOCSaves)
253  TOCSave.second = false;
254  // Add new instruction to map.
255  TOCSaves[MI] = false;
256  return;
257  }
258  }
259 
260  bool Keep = true;
261  for (auto It = TOCSaves.begin(); It != TOCSaves.end(); It++ ) {
262  MachineInstr *CurrInst = It->first;
263  // If new instruction dominates an existing one, mark existing one as
264  // redundant.
265  if (It->second && MDT->dominates(MI, CurrInst))
266  It->second = false;
267  // Check if the new instruction is redundant.
268  if (MDT->dominates(CurrInst, MI)) {
269  Keep = false;
270  break;
271  }
272  }
273  // Add new instruction to map.
274  TOCSaves[MI] = Keep;
275 }
276 
277 // This function returns a list of all PHI nodes in the tree starting from
278 // the RootPHI node. We perform a BFS traversal to get an ordered list of nodes.
279 // The list initially only contains the root PHI. When we visit a PHI node, we
280 // add it to the list. We continue to look for other PHI node operands while
281 // there are nodes to visit in the list. The function returns false if the
282 // optimization cannot be applied on this tree.
283 static bool collectUnprimedAccPHIs(MachineRegisterInfo *MRI,
284  MachineInstr *RootPHI,
286  PHIs.push_back(RootPHI);
287  unsigned VisitedIndex = 0;
288  while (VisitedIndex < PHIs.size()) {
289  MachineInstr *VisitedPHI = PHIs[VisitedIndex];
290  for (unsigned PHIOp = 1, NumOps = VisitedPHI->getNumOperands();
291  PHIOp != NumOps; PHIOp += 2) {
292  Register RegOp = VisitedPHI->getOperand(PHIOp).getReg();
293  if (!Register::isVirtualRegister(RegOp))
294  return false;
295  MachineInstr *Instr = MRI->getVRegDef(RegOp);
296  // While collecting the PHI nodes, we check if they can be converted (i.e.
297  // all the operands are either copies, implicit defs or PHI nodes).
298  unsigned Opcode = Instr->getOpcode();
299  if (Opcode == PPC::COPY) {
300  Register Reg = Instr->getOperand(1).getReg();
302  MRI->getRegClass(Reg) != &PPC::ACCRCRegClass)
303  return false;
304  } else if (Opcode != PPC::IMPLICIT_DEF && Opcode != PPC::PHI)
305  return false;
306  // If we detect a cycle in the PHI nodes, we exit. It would be
307  // possible to change cycles as well, but that would add a lot
308  // of complexity for a case that is unlikely to occur with MMA
309  // code.
310  if (Opcode != PPC::PHI)
311  continue;
312  if (llvm::is_contained(PHIs, Instr))
313  return false;
314  PHIs.push_back(Instr);
315  }
316  VisitedIndex++;
317  }
318  return true;
319 }
320 
321 // This function changes the unprimed accumulator PHI nodes in the PHIs list to
322 // primed accumulator PHI nodes. The list is traversed in reverse order to
323 // change all the PHI operands of a PHI node before changing the node itself.
324 // We keep a map to associate each changed PHI node to its non-changed form.
325 static void convertUnprimedAccPHIs(const PPCInstrInfo *TII,
328  Register Dst) {
330  for (MachineInstr *PHI : llvm::reverse(PHIs)) {
332  // We check if the current PHI node can be changed by looking at its
333  // operands. If all the operands are either copies from primed
334  // accumulators, implicit definitions or other unprimed accumulator
335  // PHI nodes, we change it.
336  for (unsigned PHIOp = 1, NumOps = PHI->getNumOperands(); PHIOp != NumOps;
337  PHIOp += 2) {
338  Register RegOp = PHI->getOperand(PHIOp).getReg();
339  MachineInstr *PHIInput = MRI->getVRegDef(RegOp);
340  unsigned Opcode = PHIInput->getOpcode();
341  assert((Opcode == PPC::COPY || Opcode == PPC::IMPLICIT_DEF ||
342  Opcode == PPC::PHI) &&
343  "Unexpected instruction");
344  if (Opcode == PPC::COPY) {
345  assert(MRI->getRegClass(PHIInput->getOperand(1).getReg()) ==
346  &PPC::ACCRCRegClass &&
347  "Unexpected register class");
348  PHIOps.push_back({PHIInput->getOperand(1), PHI->getOperand(PHIOp + 1)});
349  } else if (Opcode == PPC::IMPLICIT_DEF) {
350  Register AccReg = MRI->createVirtualRegister(&PPC::ACCRCRegClass);
351  BuildMI(*PHIInput->getParent(), PHIInput, PHIInput->getDebugLoc(),
352  TII->get(PPC::IMPLICIT_DEF), AccReg);
353  PHIOps.push_back({MachineOperand::CreateReg(AccReg, false),
354  PHI->getOperand(PHIOp + 1)});
355  } else if (Opcode == PPC::PHI) {
356  // We found a PHI operand. At this point we know this operand
357  // has already been changed so we get its associated changed form
358  // from the map.
359  assert(ChangedPHIMap.count(PHIInput) == 1 &&
360  "This PHI node should have already been changed.");
361  MachineInstr *PrimedAccPHI = ChangedPHIMap.lookup(PHIInput);
362  PHIOps.push_back({MachineOperand::CreateReg(
363  PrimedAccPHI->getOperand(0).getReg(), false),
364  PHI->getOperand(PHIOp + 1)});
365  }
366  }
367  Register AccReg = Dst;
368  // If the PHI node we are changing is the root node, the register it defines
369  // will be the destination register of the original copy (of the PHI def).
370  // For all other PHI's in the list, we need to create another primed
371  // accumulator virtual register as the PHI will no longer define the
372  // unprimed accumulator.
373  if (PHI != PHIs[0])
374  AccReg = MRI->createVirtualRegister(&PPC::ACCRCRegClass);
375  MachineInstrBuilder NewPHI = BuildMI(
376  *PHI->getParent(), PHI, PHI->getDebugLoc(), TII->get(PPC::PHI), AccReg);
377  for (auto RegMBB : PHIOps)
378  NewPHI.add(RegMBB.first).add(RegMBB.second);
379  ChangedPHIMap[PHI] = NewPHI.getInstr();
380  }
381 }
382 
383 // Perform peephole optimizations.
384 bool PPCMIPeephole::simplifyCode(void) {
385  bool Simplified = false;
386  bool TrapOpt = false;
387  MachineInstr* ToErase = nullptr;
388  std::map<MachineInstr *, bool> TOCSaves;
389  const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
390  NumFunctionsEnteredInMIPeephole++;
391  if (ConvertRegReg) {
392  // Fixed-point conversion of reg/reg instructions fed by load-immediate
393  // into reg/imm instructions. FIXME: This is expensive, control it with
394  // an option.
395  bool SomethingChanged = false;
396  do {
397  NumFixedPointIterations++;
398  SomethingChanged = false;
399  for (MachineBasicBlock &MBB : *MF) {
400  for (MachineInstr &MI : MBB) {
401  if (MI.isDebugInstr())
402  continue;
403 
404  if (TII->convertToImmediateForm(MI)) {
405  // We don't erase anything in case the def has other uses. Let DCE
406  // remove it if it can be removed.
407  LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
408  LLVM_DEBUG(MI.dump());
409  NumConvertedToImmediateForm++;
410  SomethingChanged = true;
411  Simplified = true;
412  continue;
413  }
414  }
415  }
416  } while (SomethingChanged && FixedPointRegToImm);
417  }
418 
419  for (MachineBasicBlock &MBB : *MF) {
420  for (MachineInstr &MI : MBB) {
421 
422  // If the previous instruction was marked for elimination,
423  // remove it now.
424  if (ToErase) {
425  ToErase->eraseFromParent();
426  ToErase = nullptr;
427  }
428  // If a conditional trap instruction got optimized to an
429  // unconditional trap, eliminate all the instructions after
430  // the trap.
431  if (EnableTrapOptimization && TrapOpt) {
432  ToErase = &MI;
433  continue;
434  }
435 
436  // Ignore debug instructions.
437  if (MI.isDebugInstr())
438  continue;
439 
440  // Per-opcode peepholes.
441  switch (MI.getOpcode()) {
442 
443  default:
444  break;
445  case PPC::COPY: {
446  Register Src = MI.getOperand(1).getReg();
447  Register Dst = MI.getOperand(0).getReg();
448  if (!Register::isVirtualRegister(Src) ||
450  break;
451  if (MRI->getRegClass(Src) != &PPC::UACCRCRegClass ||
452  MRI->getRegClass(Dst) != &PPC::ACCRCRegClass)
453  break;
454 
455  // We are copying an unprimed accumulator to a primed accumulator.
456  // If the input to the copy is a PHI that is fed only by (i) copies in
457  // the other direction (ii) implicitly defined unprimed accumulators or
458  // (iii) other PHI nodes satisfying (i) and (ii), we can change
459  // the PHI to a PHI on primed accumulators (as long as we also change
460  // its operands). To detect and change such copies, we first get a list
461  // of all the PHI nodes starting from the root PHI node in BFS order.
462  // We then visit all these PHI nodes to check if they can be changed to
463  // primed accumulator PHI nodes and if so, we change them.
464  MachineInstr *RootPHI = MRI->getVRegDef(Src);
465  if (RootPHI->getOpcode() != PPC::PHI)
466  break;
467 
469  if (!collectUnprimedAccPHIs(MRI, RootPHI, PHIs))
470  break;
471 
472  convertUnprimedAccPHIs(TII, MRI, PHIs, Dst);
473 
474  ToErase = &MI;
475  break;
476  }
477  case PPC::LI:
478  case PPC::LI8: {
479  // If we are materializing a zero, look for any use operands for which
480  // zero means immediate zero. All such operands can be replaced with
481  // PPC::ZERO.
482  if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != 0)
483  break;
484  unsigned MIDestReg = MI.getOperand(0).getReg();
485  for (MachineInstr& UseMI : MRI->use_instructions(MIDestReg))
486  Simplified |= TII->onlyFoldImmediate(UseMI, MI, MIDestReg);
487  if (MRI->use_nodbg_empty(MIDestReg)) {
488  ++NumLoadImmZeroFoldedAndRemoved;
489  ToErase = &MI;
490  }
491  break;
492  }
493  case PPC::STW:
494  case PPC::STD: {
495  MachineFrameInfo &MFI = MF->getFrameInfo();
496  if (MFI.hasVarSizedObjects() ||
497  (!MF->getSubtarget<PPCSubtarget>().isELFv2ABI() &&
498  !MF->getSubtarget<PPCSubtarget>().isAIXABI()))
499  break;
500  // When encountering a TOC save instruction, call UpdateTOCSaves
501  // to add it to the TOCSaves map and mark any existing TOC saves
502  // it dominates as redundant.
503  if (TII->isTOCSaveMI(MI))
504  UpdateTOCSaves(TOCSaves, &MI);
505  break;
506  }
507  case PPC::XXPERMDI: {
508  // Perform simplifications of 2x64 vector swaps and splats.
509  // A swap is identified by an immediate value of 2, and a splat
510  // is identified by an immediate value of 0 or 3.
511  int Immed = MI.getOperand(3).getImm();
512 
513  if (Immed == 1)
514  break;
515 
516  // For each of these simplifications, we need the two source
517  // regs to match. Unfortunately, MachineCSE ignores COPY and
518  // SUBREG_TO_REG, so for example we can see
519  // XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed.
520  // We have to look through chains of COPY and SUBREG_TO_REG
521  // to find the real source values for comparison.
522  unsigned TrueReg1 =
523  TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
524  unsigned TrueReg2 =
525  TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI);
526 
527  if (!(TrueReg1 == TrueReg2 && Register::isVirtualRegister(TrueReg1)))
528  break;
529 
530  MachineInstr *DefMI = MRI->getVRegDef(TrueReg1);
531 
532  if (!DefMI)
533  break;
534 
535  unsigned DefOpc = DefMI->getOpcode();
536 
537  // If this is a splat fed by a splatting load, the splat is
538  // redundant. Replace with a copy. This doesn't happen directly due
539  // to code in PPCDAGToDAGISel.cpp, but it can happen when converting
540  // a load of a double to a vector of 64-bit integers.
541  auto isConversionOfLoadAndSplat = [=]() -> bool {
542  if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS)
543  return false;
544  unsigned FeedReg1 =
546  if (Register::isVirtualRegister(FeedReg1)) {
547  MachineInstr *LoadMI = MRI->getVRegDef(FeedReg1);
548  if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX)
549  return true;
550  }
551  return false;
552  };
553  if ((Immed == 0 || Immed == 3) &&
554  (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat())) {
555  LLVM_DEBUG(dbgs() << "Optimizing load-and-splat/splat "
556  "to load-and-splat/copy: ");
557  LLVM_DEBUG(MI.dump());
558  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
559  MI.getOperand(0).getReg())
560  .add(MI.getOperand(1));
561  ToErase = &MI;
562  Simplified = true;
563  }
564 
565  // If this is a splat or a swap fed by another splat, we
566  // can replace it with a copy.
567  if (DefOpc == PPC::XXPERMDI) {
568  unsigned DefReg1 = DefMI->getOperand(1).getReg();
569  unsigned DefReg2 = DefMI->getOperand(2).getReg();
570  unsigned DefImmed = DefMI->getOperand(3).getImm();
571 
572  // If the two inputs are not the same register, check to see if
573  // they originate from the same virtual register after only
574  // copy-like instructions.
575  if (DefReg1 != DefReg2) {
576  unsigned FeedReg1 = TRI->lookThruCopyLike(DefReg1, MRI);
577  unsigned FeedReg2 = TRI->lookThruCopyLike(DefReg2, MRI);
578 
579  if (!(FeedReg1 == FeedReg2 &&
580  Register::isVirtualRegister(FeedReg1)))
581  break;
582  }
583 
584  if (DefImmed == 0 || DefImmed == 3) {
585  LLVM_DEBUG(dbgs() << "Optimizing splat/swap or splat/splat "
586  "to splat/copy: ");
587  LLVM_DEBUG(MI.dump());
588  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
589  MI.getOperand(0).getReg())
590  .add(MI.getOperand(1));
591  ToErase = &MI;
592  Simplified = true;
593  }
594 
595  // If this is a splat fed by a swap, we can simplify modify
596  // the splat to splat the other value from the swap's input
597  // parameter.
598  else if ((Immed == 0 || Immed == 3) && DefImmed == 2) {
599  LLVM_DEBUG(dbgs() << "Optimizing swap/splat => splat: ");
600  LLVM_DEBUG(MI.dump());
601  MI.getOperand(1).setReg(DefReg1);
602  MI.getOperand(2).setReg(DefReg2);
603  MI.getOperand(3).setImm(3 - Immed);
604  Simplified = true;
605  }
606 
607  // If this is a swap fed by a swap, we can replace it
608  // with a copy from the first swap's input.
609  else if (Immed == 2 && DefImmed == 2) {
610  LLVM_DEBUG(dbgs() << "Optimizing swap/swap => copy: ");
611  LLVM_DEBUG(MI.dump());
612  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
613  MI.getOperand(0).getReg())
614  .add(DefMI->getOperand(1));
615  ToErase = &MI;
616  Simplified = true;
617  }
618  } else if ((Immed == 0 || Immed == 3 || Immed == 2) &&
619  DefOpc == PPC::XXPERMDIs &&
620  (DefMI->getOperand(2).getImm() == 0 ||
621  DefMI->getOperand(2).getImm() == 3)) {
622  ToErase = &MI;
623  Simplified = true;
624  // Swap of a splat, convert to copy.
625  if (Immed == 2) {
626  LLVM_DEBUG(dbgs() << "Optimizing swap(splat) => copy(splat): ");
627  LLVM_DEBUG(MI.dump());
628  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
629  MI.getOperand(0).getReg())
630  .add(MI.getOperand(1));
631  break;
632  }
633  // Splat fed by another splat - switch the output of the first
634  // and remove the second.
635  DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
636  LLVM_DEBUG(dbgs() << "Removing redundant splat: ");
637  LLVM_DEBUG(MI.dump());
638  }
639  break;
640  }
641  case PPC::VSPLTB:
642  case PPC::VSPLTH:
643  case PPC::XXSPLTW: {
644  unsigned MyOpcode = MI.getOpcode();
645  unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2;
646  unsigned TrueReg =
647  TRI->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI);
648  if (!Register::isVirtualRegister(TrueReg))
649  break;
650  MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
651  if (!DefMI)
652  break;
653  unsigned DefOpcode = DefMI->getOpcode();
654  auto isConvertOfSplat = [=]() -> bool {
655  if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS)
656  return false;
657  Register ConvReg = DefMI->getOperand(1).getReg();
658  if (!Register::isVirtualRegister(ConvReg))
659  return false;
660  MachineInstr *Splt = MRI->getVRegDef(ConvReg);
661  return Splt && (Splt->getOpcode() == PPC::LXVWSX ||
662  Splt->getOpcode() == PPC::XXSPLTW);
663  };
664  bool AlreadySplat = (MyOpcode == DefOpcode) ||
665  (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) ||
666  (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) ||
667  (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) ||
668  (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) ||
669  (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)||
670  (MyOpcode == PPC::XXSPLTW && isConvertOfSplat());
671  // If the instruction[s] that feed this splat have already splat
672  // the value, this splat is redundant.
673  if (AlreadySplat) {
674  LLVM_DEBUG(dbgs() << "Changing redundant splat to a copy: ");
675  LLVM_DEBUG(MI.dump());
676  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
677  MI.getOperand(0).getReg())
678  .add(MI.getOperand(OpNo));
679  ToErase = &MI;
680  Simplified = true;
681  }
682  // Splat fed by a shift. Usually when we align value to splat into
683  // vector element zero.
684  if (DefOpcode == PPC::XXSLDWI) {
685  Register ShiftRes = DefMI->getOperand(0).getReg();
686  Register ShiftOp1 = DefMI->getOperand(1).getReg();
687  Register ShiftOp2 = DefMI->getOperand(2).getReg();
688  unsigned ShiftImm = DefMI->getOperand(3).getImm();
689  unsigned SplatImm =
690  MI.getOperand(MyOpcode == PPC::XXSPLTW ? 2 : 1).getImm();
691  if (ShiftOp1 == ShiftOp2) {
692  unsigned NewElem = (SplatImm + ShiftImm) & 0x3;
693  if (MRI->hasOneNonDBGUse(ShiftRes)) {
694  LLVM_DEBUG(dbgs() << "Removing redundant shift: ");
695  LLVM_DEBUG(DefMI->dump());
696  ToErase = DefMI;
697  }
698  Simplified = true;
699  LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm
700  << " to " << NewElem << " in instruction: ");
701  LLVM_DEBUG(MI.dump());
702  MI.getOperand(1).setReg(ShiftOp1);
703  MI.getOperand(2).setImm(NewElem);
704  }
705  }
706  break;
707  }
708  case PPC::XVCVDPSP: {
709  // If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant.
710  unsigned TrueReg =
711  TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
712  if (!Register::isVirtualRegister(TrueReg))
713  break;
714  MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
715 
716  // This can occur when building a vector of single precision or integer
717  // values.
718  if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) {
719  unsigned DefsReg1 =
721  unsigned DefsReg2 =
723  if (!Register::isVirtualRegister(DefsReg1) ||
724  !Register::isVirtualRegister(DefsReg2))
725  break;
726  MachineInstr *P1 = MRI->getVRegDef(DefsReg1);
727  MachineInstr *P2 = MRI->getVRegDef(DefsReg2);
728 
729  if (!P1 || !P2)
730  break;
731 
732  // Remove the passed FRSP/XSRSP instruction if it only feeds this MI
733  // and set any uses of that FRSP/XSRSP (in this MI) to the source of
734  // the FRSP/XSRSP.
735  auto removeFRSPIfPossible = [&](MachineInstr *RoundInstr) {
736  unsigned Opc = RoundInstr->getOpcode();
737  if ((Opc == PPC::FRSP || Opc == PPC::XSRSP) &&
738  MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) {
739  Simplified = true;
740  Register ConvReg1 = RoundInstr->getOperand(1).getReg();
741  Register FRSPDefines = RoundInstr->getOperand(0).getReg();
742  MachineInstr &Use = *(MRI->use_instr_nodbg_begin(FRSPDefines));
743  for (int i = 0, e = Use.getNumOperands(); i < e; ++i)
744  if (Use.getOperand(i).isReg() &&
745  Use.getOperand(i).getReg() == FRSPDefines)
746  Use.getOperand(i).setReg(ConvReg1);
747  LLVM_DEBUG(dbgs() << "Removing redundant FRSP/XSRSP:\n");
748  LLVM_DEBUG(RoundInstr->dump());
749  LLVM_DEBUG(dbgs() << "As it feeds instruction:\n");
750  LLVM_DEBUG(MI.dump());
751  LLVM_DEBUG(dbgs() << "Through instruction:\n");
752  LLVM_DEBUG(DefMI->dump());
753  RoundInstr->eraseFromParent();
754  }
755  };
756 
757  // If the input to XVCVDPSP is a vector that was built (even
758  // partially) out of FRSP's, the FRSP(s) can safely be removed
759  // since this instruction performs the same operation.
760  if (P1 != P2) {
761  removeFRSPIfPossible(P1);
762  removeFRSPIfPossible(P2);
763  break;
764  }
765  removeFRSPIfPossible(P1);
766  }
767  break;
768  }
769  case PPC::EXTSH:
770  case PPC::EXTSH8:
771  case PPC::EXTSH8_32_64: {
772  if (!EnableSExtElimination) break;
773  Register NarrowReg = MI.getOperand(1).getReg();
774  if (!Register::isVirtualRegister(NarrowReg))
775  break;
776 
777  MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg);
778  // If we've used a zero-extending load that we will sign-extend,
779  // just do a sign-extending load.
780  if (SrcMI->getOpcode() == PPC::LHZ ||
781  SrcMI->getOpcode() == PPC::LHZX) {
782  if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
783  break;
784  auto is64Bit = [] (unsigned Opcode) {
785  return Opcode == PPC::EXTSH8;
786  };
787  auto isXForm = [] (unsigned Opcode) {
788  return Opcode == PPC::LHZX;
789  };
790  auto getSextLoadOp = [] (bool is64Bit, bool isXForm) {
791  if (is64Bit)
792  if (isXForm) return PPC::LHAX8;
793  else return PPC::LHA8;
794  else
795  if (isXForm) return PPC::LHAX;
796  else return PPC::LHA;
797  };
798  unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
799  isXForm(SrcMI->getOpcode()));
800  LLVM_DEBUG(dbgs() << "Zero-extending load\n");
801  LLVM_DEBUG(SrcMI->dump());
802  LLVM_DEBUG(dbgs() << "and sign-extension\n");
803  LLVM_DEBUG(MI.dump());
804  LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
805  SrcMI->setDesc(TII->get(Opc));
806  SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
807  ToErase = &MI;
808  Simplified = true;
809  NumEliminatedSExt++;
810  }
811  break;
812  }
813  case PPC::EXTSW:
814  case PPC::EXTSW_32:
815  case PPC::EXTSW_32_64: {
816  if (!EnableSExtElimination) break;
817  Register NarrowReg = MI.getOperand(1).getReg();
818  if (!Register::isVirtualRegister(NarrowReg))
819  break;
820 
821  MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg);
822  // If we've used a zero-extending load that we will sign-extend,
823  // just do a sign-extending load.
824  if (SrcMI->getOpcode() == PPC::LWZ ||
825  SrcMI->getOpcode() == PPC::LWZX) {
826  if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
827  break;
828  auto is64Bit = [] (unsigned Opcode) {
829  return Opcode == PPC::EXTSW || Opcode == PPC::EXTSW_32_64;
830  };
831  auto isXForm = [] (unsigned Opcode) {
832  return Opcode == PPC::LWZX;
833  };
834  auto getSextLoadOp = [] (bool is64Bit, bool isXForm) {
835  if (is64Bit)
836  if (isXForm) return PPC::LWAX;
837  else return PPC::LWA;
838  else
839  if (isXForm) return PPC::LWAX_32;
840  else return PPC::LWA_32;
841  };
842  unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
843  isXForm(SrcMI->getOpcode()));
844  LLVM_DEBUG(dbgs() << "Zero-extending load\n");
845  LLVM_DEBUG(SrcMI->dump());
846  LLVM_DEBUG(dbgs() << "and sign-extension\n");
847  LLVM_DEBUG(MI.dump());
848  LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
849  SrcMI->setDesc(TII->get(Opc));
850  SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
851  ToErase = &MI;
852  Simplified = true;
853  NumEliminatedSExt++;
854  } else if (MI.getOpcode() == PPC::EXTSW_32_64 &&
855  TII->isSignExtended(*SrcMI)) {
856  // We can eliminate EXTSW if the input is known to be already
857  // sign-extended.
858  LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
859  Register TmpReg =
860  MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
861  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF),
862  TmpReg);
863  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG),
864  MI.getOperand(0).getReg())
865  .addReg(TmpReg)
866  .addReg(NarrowReg)
867  .addImm(PPC::sub_32);
868  ToErase = &MI;
869  Simplified = true;
870  NumEliminatedSExt++;
871  }
872  break;
873  }
874  case PPC::RLDICL: {
875  // We can eliminate RLDICL (e.g. for zero-extension)
876  // if all bits to clear are already zero in the input.
877  // This code assume following code sequence for zero-extension.
878  // %6 = COPY %5:sub_32; (optional)
879  // %8 = IMPLICIT_DEF;
880  // %7<def,tied1> = INSERT_SUBREG %8<tied0>, %6, sub_32;
881  if (!EnableZExtElimination) break;
882 
883  if (MI.getOperand(2).getImm() != 0)
884  break;
885 
886  Register SrcReg = MI.getOperand(1).getReg();
887  if (!Register::isVirtualRegister(SrcReg))
888  break;
889 
890  MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
891  if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG &&
892  SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg()))
893  break;
894 
895  MachineInstr *ImpDefMI, *SubRegMI;
896  ImpDefMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
897  SubRegMI = MRI->getVRegDef(SrcMI->getOperand(2).getReg());
898  if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break;
899 
900  SrcMI = SubRegMI;
901  if (SubRegMI->getOpcode() == PPC::COPY) {
902  Register CopyReg = SubRegMI->getOperand(1).getReg();
903  if (Register::isVirtualRegister(CopyReg))
904  SrcMI = MRI->getVRegDef(CopyReg);
905  }
906 
907  unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII);
908  if (MI.getOperand(3).getImm() <= KnownZeroCount) {
909  LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n");
910  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
911  MI.getOperand(0).getReg())
912  .addReg(SrcReg);
913  ToErase = &MI;
914  Simplified = true;
915  NumEliminatedZExt++;
916  }
917  break;
918  }
919 
920  // TODO: Any instruction that has an immediate form fed only by a PHI
921  // whose operands are all load immediate can be folded away. We currently
922  // do this for ADD instructions, but should expand it to arithmetic and
923  // binary instructions with immediate forms in the future.
924  case PPC::ADD4:
925  case PPC::ADD8: {
926  auto isSingleUsePHI = [&](MachineOperand *PhiOp) {
927  assert(PhiOp && "Invalid Operand!");
928  MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI);
929 
930  return DefPhiMI && (DefPhiMI->getOpcode() == PPC::PHI) &&
931  MRI->hasOneNonDBGUse(DefPhiMI->getOperand(0).getReg());
932  };
933 
934  auto dominatesAllSingleUseLIs = [&](MachineOperand *DominatorOp,
935  MachineOperand *PhiOp) {
936  assert(PhiOp && "Invalid Operand!");
937  assert(DominatorOp && "Invalid Operand!");
938  MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI);
939  MachineInstr *DefDomMI = getVRegDefOrNull(DominatorOp, MRI);
940 
941  // Note: the vregs only show up at odd indices position of PHI Node,
942  // the even indices position save the BB info.
943  for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) {
944  MachineInstr *LiMI =
945  getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI);
946  if (!LiMI ||
947  (LiMI->getOpcode() != PPC::LI && LiMI->getOpcode() != PPC::LI8)
948  || !MRI->hasOneNonDBGUse(LiMI->getOperand(0).getReg()) ||
949  !MDT->dominates(DefDomMI, LiMI))
950  return false;
951  }
952 
953  return true;
954  };
955 
956  MachineOperand Op1 = MI.getOperand(1);
957  MachineOperand Op2 = MI.getOperand(2);
958  if (isSingleUsePHI(&Op2) && dominatesAllSingleUseLIs(&Op1, &Op2))
959  std::swap(Op1, Op2);
960  else if (!isSingleUsePHI(&Op1) || !dominatesAllSingleUseLIs(&Op2, &Op1))
961  break; // We don't have an ADD fed by LI's that can be transformed
962 
963  // Now we know that Op1 is the PHI node and Op2 is the dominator
964  Register DominatorReg = Op2.getReg();
965 
966  const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8
967  ? &PPC::G8RC_and_G8RC_NOX0RegClass
968  : &PPC::GPRC_and_GPRC_NOR0RegClass;
969  MRI->setRegClass(DominatorReg, TRC);
970 
971  // replace LIs with ADDIs
972  MachineInstr *DefPhiMI = getVRegDefOrNull(&Op1, MRI);
973  for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) {
974  MachineInstr *LiMI = getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI);
975  LLVM_DEBUG(dbgs() << "Optimizing LI to ADDI: ");
976  LLVM_DEBUG(LiMI->dump());
977 
978  // There could be repeated registers in the PHI, e.g: %1 =
979  // PHI %6, <%bb.2>, %8, <%bb.3>, %8, <%bb.6>; So if we've
980  // already replaced the def instruction, skip.
981  if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8)
982  continue;
983 
984  assert((LiMI->getOpcode() == PPC::LI ||
985  LiMI->getOpcode() == PPC::LI8) &&
986  "Invalid Opcode!");
987  auto LiImm = LiMI->getOperand(1).getImm(); // save the imm of LI
988  LiMI->RemoveOperand(1); // remove the imm of LI
989  LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI
990  : PPC::ADDI8));
991  MachineInstrBuilder(*LiMI->getParent()->getParent(), *LiMI)
992  .addReg(DominatorReg)
993  .addImm(LiImm); // restore the imm of LI
994  LLVM_DEBUG(LiMI->dump());
995  }
996 
997  // Replace ADD with COPY
998  LLVM_DEBUG(dbgs() << "Optimizing ADD to COPY: ");
999  LLVM_DEBUG(MI.dump());
1000  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
1001  MI.getOperand(0).getReg())
1002  .add(Op1);
1003  ToErase = &MI;
1004  Simplified = true;
1005  NumOptADDLIs++;
1006  break;
1007  }
1008  case PPC::RLDICR: {
1009  Simplified |= emitRLDICWhenLoweringJumpTables(MI) ||
1010  combineSEXTAndSHL(MI, ToErase);
1011  break;
1012  }
1013  case PPC::RLWINM:
1014  case PPC::RLWINM_rec:
1015  case PPC::RLWINM8:
1016  case PPC::RLWINM8_rec: {
1017  Simplified = TII->combineRLWINM(MI, &ToErase);
1018  if (Simplified)
1019  ++NumRotatesCollapsed;
1020  break;
1021  }
1022  // We will replace TD/TW/TDI/TWI with an unconditional trap if it will
1023  // always trap, we will delete the node if it will never trap.
1024  case PPC::TDI:
1025  case PPC::TWI:
1026  case PPC::TD:
1027  case PPC::TW: {
1028  if (!EnableTrapOptimization) break;
1029  MachineInstr *LiMI1 = getVRegDefOrNull(&MI.getOperand(1), MRI);
1030  MachineInstr *LiMI2 = getVRegDefOrNull(&MI.getOperand(2), MRI);
1031  bool IsOperand2Immediate = MI.getOperand(2).isImm();
1032  // We can only do the optimization if we can get immediates
1033  // from both operands
1034  if (!(LiMI1 && (LiMI1->getOpcode() == PPC::LI ||
1035  LiMI1->getOpcode() == PPC::LI8)))
1036  break;
1037  if (!IsOperand2Immediate &&
1038  !(LiMI2 && (LiMI2->getOpcode() == PPC::LI ||
1039  LiMI2->getOpcode() == PPC::LI8)))
1040  break;
1041 
1042  auto ImmOperand0 = MI.getOperand(0).getImm();
1043  auto ImmOperand1 = LiMI1->getOperand(1).getImm();
1044  auto ImmOperand2 = IsOperand2Immediate ? MI.getOperand(2).getImm()
1045  : LiMI2->getOperand(1).getImm();
1046 
1047  // We will replace the MI with an unconditional trap if it will always
1048  // trap.
1049  if ((ImmOperand0 == 31) ||
1050  ((ImmOperand0 & 0x10) &&
1051  ((int64_t)ImmOperand1 < (int64_t)ImmOperand2)) ||
1052  ((ImmOperand0 & 0x8) &&
1053  ((int64_t)ImmOperand1 > (int64_t)ImmOperand2)) ||
1054  ((ImmOperand0 & 0x2) &&
1055  ((uint64_t)ImmOperand1 < (uint64_t)ImmOperand2)) ||
1056  ((ImmOperand0 & 0x1) &&
1057  ((uint64_t)ImmOperand1 > (uint64_t)ImmOperand2)) ||
1058  ((ImmOperand0 & 0x4) && (ImmOperand1 == ImmOperand2))) {
1059  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::TRAP));
1060  TrapOpt = true;
1061  }
1062  // We will delete the MI if it will never trap.
1063  ToErase = &MI;
1064  Simplified = true;
1065  break;
1066  }
1067  }
1068  }
1069 
1070  // If the last instruction was marked for elimination,
1071  // remove it now.
1072  if (ToErase) {
1073  ToErase->eraseFromParent();
1074  ToErase = nullptr;
1075  }
1076  // Reset TrapOpt to false at the end of the basic block.
1078  TrapOpt = false;
1079  }
1080 
1081  // Eliminate all the TOC save instructions which are redundant.
1082  Simplified |= eliminateRedundantTOCSaves(TOCSaves);
1083  PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
1084  if (FI->mustSaveTOC())
1085  NumTOCSavesInPrologue++;
1086 
1087  // We try to eliminate redundant compare instruction.
1088  Simplified |= eliminateRedundantCompare();
1089 
1090  return Simplified;
1091 }
1092 
1093 // helper functions for eliminateRedundantCompare
1094 static bool isEqOrNe(MachineInstr *BI) {
1096  unsigned PredCond = PPC::getPredicateCondition(Pred);
1097  return (PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE);
1098 }
1099 
1100 static bool isSupportedCmpOp(unsigned opCode) {
1101  return (opCode == PPC::CMPLD || opCode == PPC::CMPD ||
1102  opCode == PPC::CMPLW || opCode == PPC::CMPW ||
1103  opCode == PPC::CMPLDI || opCode == PPC::CMPDI ||
1104  opCode == PPC::CMPLWI || opCode == PPC::CMPWI);
1105 }
1106 
1107 static bool is64bitCmpOp(unsigned opCode) {
1108  return (opCode == PPC::CMPLD || opCode == PPC::CMPD ||
1109  opCode == PPC::CMPLDI || opCode == PPC::CMPDI);
1110 }
1111 
1112 static bool isSignedCmpOp(unsigned opCode) {
1113  return (opCode == PPC::CMPD || opCode == PPC::CMPW ||
1114  opCode == PPC::CMPDI || opCode == PPC::CMPWI);
1115 }
1116 
1117 static unsigned getSignedCmpOpCode(unsigned opCode) {
1118  if (opCode == PPC::CMPLD) return PPC::CMPD;
1119  if (opCode == PPC::CMPLW) return PPC::CMPW;
1120  if (opCode == PPC::CMPLDI) return PPC::CMPDI;
1121  if (opCode == PPC::CMPLWI) return PPC::CMPWI;
1122  return opCode;
1123 }
1124 
1125 // We can decrement immediate x in (GE x) by changing it to (GT x-1) or
1126 // (LT x) to (LE x-1)
1127 static unsigned getPredicateToDecImm(MachineInstr *BI, MachineInstr *CMPI) {
1128  uint64_t Imm = CMPI->getOperand(2).getImm();
1129  bool SignedCmp = isSignedCmpOp(CMPI->getOpcode());
1130  if ((!SignedCmp && Imm == 0) || (SignedCmp && Imm == 0x8000))
1131  return 0;
1132 
1134  unsigned PredCond = PPC::getPredicateCondition(Pred);
1135  unsigned PredHint = PPC::getPredicateHint(Pred);
1136  if (PredCond == PPC::PRED_GE)
1137  return PPC::getPredicate(PPC::PRED_GT, PredHint);
1138  if (PredCond == PPC::PRED_LT)
1139  return PPC::getPredicate(PPC::PRED_LE, PredHint);
1140 
1141  return 0;
1142 }
1143 
1144 // We can increment immediate x in (GT x) by changing it to (GE x+1) or
1145 // (LE x) to (LT x+1)
1146 static unsigned getPredicateToIncImm(MachineInstr *BI, MachineInstr *CMPI) {
1147  uint64_t Imm = CMPI->getOperand(2).getImm();
1148  bool SignedCmp = isSignedCmpOp(CMPI->getOpcode());
1149  if ((!SignedCmp && Imm == 0xFFFF) || (SignedCmp && Imm == 0x7FFF))
1150  return 0;
1151 
1153  unsigned PredCond = PPC::getPredicateCondition(Pred);
1154  unsigned PredHint = PPC::getPredicateHint(Pred);
1155  if (PredCond == PPC::PRED_GT)
1156  return PPC::getPredicate(PPC::PRED_GE, PredHint);
1157  if (PredCond == PPC::PRED_LE)
1158  return PPC::getPredicate(PPC::PRED_LT, PredHint);
1159 
1160  return 0;
1161 }
1162 
1163 // This takes a Phi node and returns a register value for the specified BB.
1164 static unsigned getIncomingRegForBlock(MachineInstr *Phi,
1166  for (unsigned I = 2, E = Phi->getNumOperands() + 1; I != E; I += 2) {
1167  MachineOperand &MO = Phi->getOperand(I);
1168  if (MO.getMBB() == MBB)
1169  return Phi->getOperand(I-1).getReg();
1170  }
1171  llvm_unreachable("invalid src basic block for this Phi node\n");
1172  return 0;
1173 }
1174 
1175 // This function tracks the source of the register through register copy.
1176 // If BB1 and BB2 are non-NULL, we also track PHI instruction in BB2
1177 // assuming that the control comes from BB1 into BB2.
1178 static unsigned getSrcVReg(unsigned Reg, MachineBasicBlock *BB1,
1180  unsigned SrcReg = Reg;
1181  while (1) {
1182  unsigned NextReg = SrcReg;
1183  MachineInstr *Inst = MRI->getVRegDef(SrcReg);
1184  if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) {
1185  NextReg = getIncomingRegForBlock(Inst, BB1);
1186  // We track through PHI only once to avoid infinite loop.
1187  BB1 = nullptr;
1188  }
1189  else if (Inst->isFullCopy())
1190  NextReg = Inst->getOperand(1).getReg();
1191  if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg))
1192  break;
1193  SrcReg = NextReg;
1194  }
1195  return SrcReg;
1196 }
1197 
1198 static bool eligibleForCompareElimination(MachineBasicBlock &MBB,
1199  MachineBasicBlock *&PredMBB,
1200  MachineBasicBlock *&MBBtoMoveCmp,
1202 
1203  auto isEligibleBB = [&](MachineBasicBlock &BB) {
1204  auto BII = BB.getFirstInstrTerminator();
1205  // We optimize BBs ending with a conditional branch.
1206  // We check only for BCC here, not BCCLR, because BCCLR
1207  // will be formed only later in the pipeline.
1208  if (BB.succ_size() == 2 &&
1209  BII != BB.instr_end() &&
1210  (*BII).getOpcode() == PPC::BCC &&
1211  (*BII).getOperand(1).isReg()) {
1212  // We optimize only if the condition code is used only by one BCC.
1213  Register CndReg = (*BII).getOperand(1).getReg();
1214  if (!Register::isVirtualRegister(CndReg) || !MRI->hasOneNonDBGUse(CndReg))
1215  return false;
1216 
1217  MachineInstr *CMPI = MRI->getVRegDef(CndReg);
1218  // We assume compare and branch are in the same BB for ease of analysis.
1219  if (CMPI->getParent() != &BB)
1220  return false;
1221 
1222  // We skip this BB if a physical register is used in comparison.
1223  for (MachineOperand &MO : CMPI->operands())
1224  if (MO.isReg() && !Register::isVirtualRegister(MO.getReg()))
1225  return false;
1226 
1227  return true;
1228  }
1229  return false;
1230  };
1231 
1232  // If this BB has more than one successor, we can create a new BB and
1233  // move the compare instruction in the new BB.
1234  // So far, we do not move compare instruction to a BB having multiple
1235  // successors to avoid potentially increasing code size.
1236  auto isEligibleForMoveCmp = [](MachineBasicBlock &BB) {
1237  return BB.succ_size() == 1;
1238  };
1239 
1240  if (!isEligibleBB(MBB))
1241  return false;
1242 
1243  unsigned NumPredBBs = MBB.pred_size();
1244  if (NumPredBBs == 1) {
1245  MachineBasicBlock *TmpMBB = *MBB.pred_begin();
1246  if (isEligibleBB(*TmpMBB)) {
1247  PredMBB = TmpMBB;
1248  MBBtoMoveCmp = nullptr;
1249  return true;
1250  }
1251  }
1252  else if (NumPredBBs == 2) {
1253  // We check for partially redundant case.
1254  // So far, we support cases with only two predecessors
1255  // to avoid increasing the number of instructions.
1257  MachineBasicBlock *Pred1MBB = *PI;
1258  MachineBasicBlock *Pred2MBB = *(PI+1);
1259 
1260  if (isEligibleBB(*Pred1MBB) && isEligibleForMoveCmp(*Pred2MBB)) {
1261  // We assume Pred1MBB is the BB containing the compare to be merged and
1262  // Pred2MBB is the BB to which we will append a compare instruction.
1263  // Hence we can proceed as is.
1264  }
1265  else if (isEligibleBB(*Pred2MBB) && isEligibleForMoveCmp(*Pred1MBB)) {
1266  // We need to swap Pred1MBB and Pred2MBB to canonicalize.
1267  std::swap(Pred1MBB, Pred2MBB);
1268  }
1269  else return false;
1270 
1271  // Here, Pred2MBB is the BB to which we need to append a compare inst.
1272  // We cannot move the compare instruction if operands are not available
1273  // in Pred2MBB (i.e. defined in MBB by an instruction other than PHI).
1275  MachineInstr *CMPI = MRI->getVRegDef(BI->getOperand(1).getReg());
1276  for (int I = 1; I <= 2; I++)
1277  if (CMPI->getOperand(I).isReg()) {
1278  MachineInstr *Inst = MRI->getVRegDef(CMPI->getOperand(I).getReg());
1279  if (Inst->getParent() == &MBB && Inst->getOpcode() != PPC::PHI)
1280  return false;
1281  }
1282 
1283  PredMBB = Pred1MBB;
1284  MBBtoMoveCmp = Pred2MBB;
1285  return true;
1286  }
1287 
1288  return false;
1289 }
1290 
1291 // This function will iterate over the input map containing a pair of TOC save
1292 // instruction and a flag. The flag will be set to false if the TOC save is
1293 // proven redundant. This function will erase from the basic block all the TOC
1294 // saves marked as redundant.
1295 bool PPCMIPeephole::eliminateRedundantTOCSaves(
1296  std::map<MachineInstr *, bool> &TOCSaves) {
1297  bool Simplified = false;
1298  int NumKept = 0;
1299  for (auto TOCSave : TOCSaves) {
1300  if (!TOCSave.second) {
1301  TOCSave.first->eraseFromParent();
1302  RemoveTOCSave++;
1303  Simplified = true;
1304  } else {
1305  NumKept++;
1306  }
1307  }
1308 
1309  if (NumKept > 1)
1310  MultiTOCSaves++;
1311 
1312  return Simplified;
1313 }
1314 
1315 // If multiple conditional branches are executed based on the (essentially)
1316 // same comparison, we merge compare instructions into one and make multiple
1317 // conditional branches on this comparison.
1318 // For example,
1319 // if (a == 0) { ... }
1320 // else if (a < 0) { ... }
1321 // can be executed by one compare and two conditional branches instead of
1322 // two pairs of a compare and a conditional branch.
1323 //
1324 // This method merges two compare instructions in two MBBs and modifies the
1325 // compare and conditional branch instructions if needed.
1326 // For the above example, the input for this pass looks like:
1327 // cmplwi r3, 0
1328 // beq 0, .LBB0_3
1329 // cmpwi r3, -1
1330 // bgt 0, .LBB0_4
1331 // So, before merging two compares, we need to modify these instructions as
1332 // cmpwi r3, 0 ; cmplwi and cmpwi yield same result for beq
1333 // beq 0, .LBB0_3
1334 // cmpwi r3, 0 ; greather than -1 means greater or equal to 0
1335 // bge 0, .LBB0_4
1336 
1337 bool PPCMIPeephole::eliminateRedundantCompare(void) {
1338  bool Simplified = false;
1339 
1340  for (MachineBasicBlock &MBB2 : *MF) {
1341  MachineBasicBlock *MBB1 = nullptr, *MBBtoMoveCmp = nullptr;
1342 
1343  // For fully redundant case, we select two basic blocks MBB1 and MBB2
1344  // as an optimization target if
1345  // - both MBBs end with a conditional branch,
1346  // - MBB1 is the only predecessor of MBB2, and
1347  // - compare does not take a physical register as a operand in both MBBs.
1348  // In this case, eligibleForCompareElimination sets MBBtoMoveCmp nullptr.
1349  //
1350  // As partially redundant case, we additionally handle if MBB2 has one
1351  // additional predecessor, which has only one successor (MBB2).
1352  // In this case, we move the compare instruction originally in MBB2 into
1353  // MBBtoMoveCmp. This partially redundant case is typically appear by
1354  // compiling a while loop; here, MBBtoMoveCmp is the loop preheader.
1355  //
1356  // Overview of CFG of related basic blocks
1357  // Fully redundant case Partially redundant case
1358  // -------- ---------------- --------
1359  // | MBB1 | (w/ 2 succ) | MBBtoMoveCmp | | MBB1 | (w/ 2 succ)
1360  // -------- ---------------- --------
1361  // | \ (w/ 1 succ) \ | \
1362  // | \ \ | \
1363  // | \ |
1364  // -------- --------
1365  // | MBB2 | (w/ 1 pred | MBB2 | (w/ 2 pred
1366  // -------- and 2 succ) -------- and 2 succ)
1367  // | \ | \
1368  // | \ | \
1369  //
1370  if (!eligibleForCompareElimination(MBB2, MBB1, MBBtoMoveCmp, MRI))
1371  continue;
1372 
1373  MachineInstr *BI1 = &*MBB1->getFirstInstrTerminator();
1374  MachineInstr *CMPI1 = MRI->getVRegDef(BI1->getOperand(1).getReg());
1375 
1376  MachineInstr *BI2 = &*MBB2.getFirstInstrTerminator();
1377  MachineInstr *CMPI2 = MRI->getVRegDef(BI2->getOperand(1).getReg());
1378  bool IsPartiallyRedundant = (MBBtoMoveCmp != nullptr);
1379 
1380  // We cannot optimize an unsupported compare opcode or
1381  // a mix of 32-bit and 64-bit comaprisons
1382  if (!isSupportedCmpOp(CMPI1->getOpcode()) ||
1383  !isSupportedCmpOp(CMPI2->getOpcode()) ||
1384  is64bitCmpOp(CMPI1->getOpcode()) != is64bitCmpOp(CMPI2->getOpcode()))
1385  continue;
1386 
1387  unsigned NewOpCode = 0;
1388  unsigned NewPredicate1 = 0, NewPredicate2 = 0;
1389  int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0;
1390  bool SwapOperands = false;
1391 
1392  if (CMPI1->getOpcode() != CMPI2->getOpcode()) {
1393  // Typically, unsigned comparison is used for equality check, but
1394  // we replace it with a signed comparison if the comparison
1395  // to be merged is a signed comparison.
1396  // In other cases of opcode mismatch, we cannot optimize this.
1397 
1398  // We cannot change opcode when comparing against an immediate
1399  // if the most significant bit of the immediate is one
1400  // due to the difference in sign extension.
1401  auto CmpAgainstImmWithSignBit = [](MachineInstr *I) {
1402  if (!I->getOperand(2).isImm())
1403  return false;
1404  int16_t Imm = (int16_t)I->getOperand(2).getImm();
1405  return Imm < 0;
1406  };
1407 
1408  if (isEqOrNe(BI2) && !CmpAgainstImmWithSignBit(CMPI2) &&
1409  CMPI1->getOpcode() == getSignedCmpOpCode(CMPI2->getOpcode()))
1410  NewOpCode = CMPI1->getOpcode();
1411  else if (isEqOrNe(BI1) && !CmpAgainstImmWithSignBit(CMPI1) &&
1412  getSignedCmpOpCode(CMPI1->getOpcode()) == CMPI2->getOpcode())
1413  NewOpCode = CMPI2->getOpcode();
1414  else continue;
1415  }
1416 
1417  if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) {
1418  // In case of comparisons between two registers, these two registers
1419  // must be same to merge two comparisons.
1420  unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(),
1421  nullptr, nullptr, MRI);
1422  unsigned Cmp1Operand2 = getSrcVReg(CMPI1->getOperand(2).getReg(),
1423  nullptr, nullptr, MRI);
1424  unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(),
1425  MBB1, &MBB2, MRI);
1426  unsigned Cmp2Operand2 = getSrcVReg(CMPI2->getOperand(2).getReg(),
1427  MBB1, &MBB2, MRI);
1428 
1429  if (Cmp1Operand1 == Cmp2Operand1 && Cmp1Operand2 == Cmp2Operand2) {
1430  // Same pair of registers in the same order; ready to merge as is.
1431  }
1432  else if (Cmp1Operand1 == Cmp2Operand2 && Cmp1Operand2 == Cmp2Operand1) {
1433  // Same pair of registers in different order.
1434  // We reverse the predicate to merge compare instructions.
1435  PPC::Predicate Pred = (PPC::Predicate)BI2->getOperand(0).getImm();
1436  NewPredicate2 = (unsigned)PPC::getSwappedPredicate(Pred);
1437  // In case of partial redundancy, we need to swap operands
1438  // in another compare instruction.
1439  SwapOperands = true;
1440  }
1441  else continue;
1442  }
1443  else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()) {
1444  // In case of comparisons between a register and an immediate,
1445  // the operand register must be same for two compare instructions.
1446  unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(),
1447  nullptr, nullptr, MRI);
1448  unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(),
1449  MBB1, &MBB2, MRI);
1450  if (Cmp1Operand1 != Cmp2Operand1)
1451  continue;
1452 
1453  NewImm1 = Imm1 = (int16_t)CMPI1->getOperand(2).getImm();
1454  NewImm2 = Imm2 = (int16_t)CMPI2->getOperand(2).getImm();
1455 
1456  // If immediate are not same, we try to adjust by changing predicate;
1457  // e.g. GT imm means GE (imm+1).
1458  if (Imm1 != Imm2 && (!isEqOrNe(BI2) || !isEqOrNe(BI1))) {
1459  int Diff = Imm1 - Imm2;
1460  if (Diff < -2 || Diff > 2)
1461  continue;
1462 
1463  unsigned PredToInc1 = getPredicateToIncImm(BI1, CMPI1);
1464  unsigned PredToDec1 = getPredicateToDecImm(BI1, CMPI1);
1465  unsigned PredToInc2 = getPredicateToIncImm(BI2, CMPI2);
1466  unsigned PredToDec2 = getPredicateToDecImm(BI2, CMPI2);
1467  if (Diff == 2) {
1468  if (PredToInc2 && PredToDec1) {
1469  NewPredicate2 = PredToInc2;
1470  NewPredicate1 = PredToDec1;
1471  NewImm2++;
1472  NewImm1--;
1473  }
1474  }
1475  else if (Diff == 1) {
1476  if (PredToInc2) {
1477  NewImm2++;
1478  NewPredicate2 = PredToInc2;
1479  }
1480  else if (PredToDec1) {
1481  NewImm1--;
1482  NewPredicate1 = PredToDec1;
1483  }
1484  }
1485  else if (Diff == -1) {
1486  if (PredToDec2) {
1487  NewImm2--;
1488  NewPredicate2 = PredToDec2;
1489  }
1490  else if (PredToInc1) {
1491  NewImm1++;
1492  NewPredicate1 = PredToInc1;
1493  }
1494  }
1495  else if (Diff == -2) {
1496  if (PredToDec2 && PredToInc1) {
1497  NewPredicate2 = PredToDec2;
1498  NewPredicate1 = PredToInc1;
1499  NewImm2--;
1500  NewImm1++;
1501  }
1502  }
1503  }
1504 
1505  // We cannot merge two compares if the immediates are not same.
1506  if (NewImm2 != NewImm1)
1507  continue;
1508  }
1509 
1510  LLVM_DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n");
1511  LLVM_DEBUG(CMPI1->dump());
1512  LLVM_DEBUG(BI1->dump());
1513  LLVM_DEBUG(CMPI2->dump());
1514  LLVM_DEBUG(BI2->dump());
1515 
1516  // We adjust opcode, predicates and immediate as we determined above.
1517  if (NewOpCode != 0 && NewOpCode != CMPI1->getOpcode()) {
1518  CMPI1->setDesc(TII->get(NewOpCode));
1519  }
1520  if (NewPredicate1) {
1521  BI1->getOperand(0).setImm(NewPredicate1);
1522  }
1523  if (NewPredicate2) {
1524  BI2->getOperand(0).setImm(NewPredicate2);
1525  }
1526  if (NewImm1 != Imm1) {
1527  CMPI1->getOperand(2).setImm(NewImm1);
1528  }
1529 
1530  if (IsPartiallyRedundant) {
1531  // We touch up the compare instruction in MBB2 and move it to
1532  // a previous BB to handle partially redundant case.
1533  if (SwapOperands) {
1534  Register Op1 = CMPI2->getOperand(1).getReg();
1535  Register Op2 = CMPI2->getOperand(2).getReg();
1536  CMPI2->getOperand(1).setReg(Op2);
1537  CMPI2->getOperand(2).setReg(Op1);
1538  }
1539  if (NewImm2 != Imm2)
1540  CMPI2->getOperand(2).setImm(NewImm2);
1541 
1542  for (int I = 1; I <= 2; I++) {
1543  if (CMPI2->getOperand(I).isReg()) {
1544  MachineInstr *Inst = MRI->getVRegDef(CMPI2->getOperand(I).getReg());
1545  if (Inst->getParent() != &MBB2)
1546  continue;
1547 
1548  assert(Inst->getOpcode() == PPC::PHI &&
1549  "We cannot support if an operand comes from this BB.");
1550  unsigned SrcReg = getIncomingRegForBlock(Inst, MBBtoMoveCmp);
1551  CMPI2->getOperand(I).setReg(SrcReg);
1552  }
1553  }
1554  auto I = MachineBasicBlock::iterator(MBBtoMoveCmp->getFirstTerminator());
1555  MBBtoMoveCmp->splice(I, &MBB2, MachineBasicBlock::iterator(CMPI2));
1556 
1557  DebugLoc DL = CMPI2->getDebugLoc();
1558  Register NewVReg = MRI->createVirtualRegister(&PPC::CRRCRegClass);
1559  BuildMI(MBB2, MBB2.begin(), DL,
1560  TII->get(PPC::PHI), NewVReg)
1561  .addReg(BI1->getOperand(1).getReg()).addMBB(MBB1)
1562  .addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp);
1563  BI2->getOperand(1).setReg(NewVReg);
1564  }
1565  else {
1566  // We finally eliminate compare instruction in MBB2.
1567  BI2->getOperand(1).setReg(BI1->getOperand(1).getReg());
1568  CMPI2->eraseFromParent();
1569  }
1570  BI2->getOperand(1).setIsKill(true);
1571  BI1->getOperand(1).setIsKill(false);
1572 
1573  LLVM_DEBUG(dbgs() << "into a compare and two branches:\n");
1574  LLVM_DEBUG(CMPI1->dump());
1575  LLVM_DEBUG(BI1->dump());
1576  LLVM_DEBUG(BI2->dump());
1577  if (IsPartiallyRedundant) {
1578  LLVM_DEBUG(dbgs() << "The following compare is moved into "
1579  << printMBBReference(*MBBtoMoveCmp)
1580  << " to handle partial redundancy.\n");
1581  LLVM_DEBUG(CMPI2->dump());
1582  }
1583 
1584  Simplified = true;
1585  }
1586 
1587  return Simplified;
1588 }
1589 
1590 // We miss the opportunity to emit an RLDIC when lowering jump tables
1591 // since ISEL sees only a single basic block. When selecting, the clear
1592 // and shift left will be in different blocks.
1593 bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) {
1594  if (MI.getOpcode() != PPC::RLDICR)
1595  return false;
1596 
1597  Register SrcReg = MI.getOperand(1).getReg();
1598  if (!Register::isVirtualRegister(SrcReg))
1599  return false;
1600 
1601  MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
1602  if (SrcMI->getOpcode() != PPC::RLDICL)
1603  return false;
1604 
1605  MachineOperand MOpSHSrc = SrcMI->getOperand(2);
1606  MachineOperand MOpMBSrc = SrcMI->getOperand(3);
1607  MachineOperand MOpSHMI = MI.getOperand(2);
1608  MachineOperand MOpMEMI = MI.getOperand(3);
1609  if (!(MOpSHSrc.isImm() && MOpMBSrc.isImm() && MOpSHMI.isImm() &&
1610  MOpMEMI.isImm()))
1611  return false;
1612 
1613  uint64_t SHSrc = MOpSHSrc.getImm();
1614  uint64_t MBSrc = MOpMBSrc.getImm();
1615  uint64_t SHMI = MOpSHMI.getImm();
1616  uint64_t MEMI = MOpMEMI.getImm();
1617  uint64_t NewSH = SHSrc + SHMI;
1618  uint64_t NewMB = MBSrc - SHMI;
1619  if (NewMB > 63 || NewSH > 63)
1620  return false;
1621 
1622  // The bits cleared with RLDICL are [0, MBSrc).
1623  // The bits cleared with RLDICR are (MEMI, 63].
1624  // After the sequence, the bits cleared are:
1625  // [0, MBSrc-SHMI) and (MEMI, 63).
1626  //
1627  // The bits cleared with RLDIC are [0, NewMB) and (63-NewSH, 63].
1628  if ((63 - NewSH) != MEMI)
1629  return false;
1630 
1631  LLVM_DEBUG(dbgs() << "Converting pair: ");
1632  LLVM_DEBUG(SrcMI->dump());
1633  LLVM_DEBUG(MI.dump());
1634 
1635  MI.setDesc(TII->get(PPC::RLDIC));
1636  MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
1637  MI.getOperand(2).setImm(NewSH);
1638  MI.getOperand(3).setImm(NewMB);
1639  MI.getOperand(1).setIsKill(SrcMI->getOperand(1).isKill());
1640  SrcMI->getOperand(1).setIsKill(false);
1641 
1642  LLVM_DEBUG(dbgs() << "To: ");
1643  LLVM_DEBUG(MI.dump());
1644  NumRotatesCollapsed++;
1645  // If SrcReg has no non-debug use it's safe to delete its def SrcMI.
1646  if (MRI->use_nodbg_empty(SrcReg)) {
1647  assert(!SrcMI->hasImplicitDef() &&
1648  "Not expecting an implicit def with this instr.");
1649  SrcMI->eraseFromParent();
1650  }
1651  return true;
1652 }
1653 
1654 // For case in LLVM IR
1655 // entry:
1656 // %iconv = sext i32 %index to i64
1657 // br i1 undef label %true, label %false
1658 // true:
1659 // %ptr = getelementptr inbounds i32, i32* null, i64 %iconv
1660 // ...
1661 // PPCISelLowering::combineSHL fails to combine, because sext and shl are in
1662 // different BBs when conducting instruction selection. We can do a peephole
1663 // optimization to combine these two instructions into extswsli after
1664 // instruction selection.
1665 bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI,
1666  MachineInstr *&ToErase) {
1667  if (MI.getOpcode() != PPC::RLDICR)
1668  return false;
1669 
1670  if (!MF->getSubtarget<PPCSubtarget>().isISA3_0())
1671  return false;
1672 
1673  assert(MI.getNumOperands() == 4 && "RLDICR should have 4 operands");
1674 
1675  MachineOperand MOpSHMI = MI.getOperand(2);
1676  MachineOperand MOpMEMI = MI.getOperand(3);
1677  if (!(MOpSHMI.isImm() && MOpMEMI.isImm()))
1678  return false;
1679 
1680  uint64_t SHMI = MOpSHMI.getImm();
1681  uint64_t MEMI = MOpMEMI.getImm();
1682  if (SHMI + MEMI != 63)
1683  return false;
1684 
1685  Register SrcReg = MI.getOperand(1).getReg();
1686  if (!Register::isVirtualRegister(SrcReg))
1687  return false;
1688 
1689  MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
1690  if (SrcMI->getOpcode() != PPC::EXTSW &&
1691  SrcMI->getOpcode() != PPC::EXTSW_32_64)
1692  return false;
1693 
1694  // If the register defined by extsw has more than one use, combination is not
1695  // needed.
1696  if (!MRI->hasOneNonDBGUse(SrcReg))
1697  return false;
1698 
1699  assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands");
1700  assert(SrcMI->getOperand(1).isReg() &&
1701  "EXTSW's second operand should be a register");
1702  if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg()))
1703  return false;
1704 
1705  LLVM_DEBUG(dbgs() << "Combining pair: ");
1706  LLVM_DEBUG(SrcMI->dump());
1707  LLVM_DEBUG(MI.dump());
1708 
1709  MachineInstr *NewInstr =
1710  BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
1711  SrcMI->getOpcode() == PPC::EXTSW ? TII->get(PPC::EXTSWSLI)
1712  : TII->get(PPC::EXTSWSLI_32_64),
1713  MI.getOperand(0).getReg())
1714  .add(SrcMI->getOperand(1))
1715  .add(MOpSHMI);
1716  (void)NewInstr;
1717 
1718  LLVM_DEBUG(dbgs() << "TO: ");
1719  LLVM_DEBUG(NewInstr->dump());
1720  ++NumEXTSWAndSLDICombined;
1721  ToErase = &MI;
1722  // SrcMI, which is extsw, is of no use now, erase it.
1723  SrcMI->eraseFromParent();
1724  return true;
1725 }
1726 
1727 } // end default namespace
1728 
1729 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE,
1730  "PowerPC MI Peephole Optimization", false, false)
1735  "PowerPC MI Peephole Optimization", false, false)
1736 
1737 char PPCMIPeephole::ID = 0;
1738 FunctionPass*
1739 llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); }
1740 
i
i
Definition: README.txt:29
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:353
llvm::MachineBasicBlock::pred_begin
pred_iterator pred_begin()
Definition: MachineBasicBlock.h:316
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
ConvertRegReg
static cl::opt< bool > ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true), cl::desc("Convert eligible reg+reg instructions to reg+imm"))
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::PPC::PRED_LT
@ PRED_LT
Definition: PPCPredicates.h:27
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::lookup
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:197
llvm::PPC::PRED_GE
@ PRED_GE
Definition: PPCPredicates.h:30
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1019
llvm::MachineInstr::RemoveOperand
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:306
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:500
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
PPCInstrBuilder.h
Statistic.h
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:119
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
EnableTrapOptimization
static cl::opt< bool > EnableTrapOptimization("ppc-opt-conditional-trap", cl::desc("enable optimization of conditional traps"), cl::init(false), cl::Hidden)
llvm::PPCInstrInfo
Definition: PPCInstrInfo.h:191
llvm::MachineRegisterInfo::use_instr_nodbg_begin
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:535
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:655
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::MachineRegisterInfo::use_instructions
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:485
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:359
Optimization
PowerPC MI Peephole Optimization
Definition: PPCMIPeephole.cpp:1735
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
llvm::PPCFunctionInfo
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
Definition: PPCMachineFunctionInfo.h:24
EnableZExtElimination
static cl::opt< bool > EnableZExtElimination("ppc-eliminate-zeroext", cl::desc("enable elimination of zero-extensions"), cl::init(false), cl::Hidden)
initialize
static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, ArrayRef< StringLiteral > StandardNames)
Initialize the set of available library functions based on the specified target triple.
Definition: TargetLibraryInfo.cpp:116
llvm::MachineDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachineDominators.h:109
llvm::PPC::PRED_GT
@ PRED_GT
Definition: PPCPredicates.h:31
PPCMCTargetDesc.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::MachineBlockFrequencyInfo::getBlockFreq
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
Definition: MachineBlockFrequencyInfo.cpp:230
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MachineRegisterInfo.h
llvm::PPCFunctionInfo::setMustSaveTOC
void setMustSaveTOC(bool U)
Definition: PPCMachineFunctionInfo.h:189
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
llvm::MachineBasicBlock::pred_size
unsigned pred_size() const
Definition: MachineBasicBlock.h:328
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::MachineBasicBlock::getFirstInstrTerminator
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
Definition: MachineBasicBlock.cpp:250
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:828
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:644
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MachineBlockFrequencyInfo
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
Definition: MachineBlockFrequencyInfo.h:33
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
P2
This might compile to this xmm1 xorps xmm0 movss xmm0 ret Now consider if the code caused xmm1 to get spilled This might produce this xmm1 movaps xmm0 movaps xmm1 movss xmm0 ret since the reload is only used by these we could fold it into the producing something like xmm1 movaps xmm0 ret saving two instructions The basic idea is that a reload from a spill if only one byte chunk is bring in zeros the one element instead of elements This can be used to simplify a variety of shuffle where the elements are fixed zeros This code generates ugly probably due to costs being off or< 4 x float > * P2
Definition: README-SSE.txt:278
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:732
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::JumpTable::Simplified
@ Simplified
Definition: TargetOptions.h:47
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::PPC::getSwappedPredicate
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...
Definition: PPCPredicates.cpp:52
llvm::PPCSubtarget::isISA3_0
bool isISA3_0() const
Definition: PPCSubtarget.h:336
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
PPC.h
llvm::PPC::PRED_LE
@ PRED_LE
Definition: PPCPredicates.h:28
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:398
llvm::MachineRegisterInfo::use_empty
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:506
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE, "PowerPC MI Peephole Optimization", false, false) INITIALIZE_PASS_END(PPCMIPeephole
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::PPC::PRED_EQ
@ PRED_EQ
Definition: PPCPredicates.h:29
llvm::PPC::getPredicateCondition
unsigned getPredicateCondition(Predicate Opcode)
Return the condition without hint bits.
Definition: PPCPredicates.h:77
llvm::PPCSubtarget::isAIXABI
bool isAIXABI() const
Definition: PPCSubtarget.h:363
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:634
llvm::initializePPCMIPeepholePass
void initializePPCMIPeepholePass(PassRegistry &)
llvm::cl::opt< bool >
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
x2
gcc mainline compiles it x2(%rip)
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
NewImm2
T NewImm2
Definition: AArch64MIPeepholeOpt.cpp:105
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1088
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap
Definition: DenseMap.h:714
PPCInstrInfo.h
llvm::MachineFunction::dump
void dump() const
dump - Print the current MachineFunction to cerr, useful for debugger use.
Definition: MachineFunction.cpp:537
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1646
MachineFunctionPass.h
llvm::MachineBasicBlock::pred_iterator
std::vector< MachineBasicBlock * >::iterator pred_iterator
Definition: MachineBasicBlock.h:304
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::PPC::PRED_NE
@ PRED_NE
Definition: PPCPredicates.h:32
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::PPC::getPredicateHint
unsigned getPredicateHint(Predicate Opcode)
Return the hint bits of the predicate.
Definition: PPCPredicates.h:82
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
MachinePostDominators.h
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::MachineInstr::dump
void dump() const
Definition: MachineInstr.cpp:1541
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:566
llvm::MachineInstr::hasImplicitDef
bool hasImplicitDef() const
Returns true if the instruction has implicit definition.
Definition: MachineInstr.h:572
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:241
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:950
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:417
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
if
if(llvm_vc STREQUAL "") set(fake_version_inc "$
Definition: CMakeLists.txt:14
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
FixedPointRegToImm
static cl::opt< bool > FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true), cl::desc("Iterate to a fixed point when attempting to " "convert reg-reg instructions to reg-imm"))
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::Pass::dump
void dump() const
Definition: Pass.cpp:131
llvm::PPCFunctionInfo::mustSaveTOC
bool mustSaveTOC() const
Definition: PPCMachineFunctionInfo.h:190
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::MachinePostDominatorTree
MachinePostDominatorTree - an analysis pass wrapper for DominatorTree used to compute the post-domina...
Definition: MachinePostDominators.h:27
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachinePostDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachinePostDominators.h:54
llvm::createPPCMIPeepholePass
FunctionPass * createPPCMIPeepholePass()
Definition: PPCMIPeephole.cpp:1739
llvm::PPC::getPredicate
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:87
llvm::TargetRegisterInfo::lookThruCopyLike
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
Definition: TargetRegisterInfo.cpp:595
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:600
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::countLeadingZeros
unsigned countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1.
Definition: MathExtras.h:225
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
NewImm1
T NewImm1
Definition: AArch64MIPeepholeOpt.cpp:101
llvm::PPCISD::EXTSWSLI
@ EXTSWSLI
EXTSWSLI = The PPC extswsli instruction, which does an extend-sign word and shift left immediate.
Definition: PPCISelLowering.h:174
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::PPCSubtarget::isUsingPCRelativeCalls
bool isUsingPCRelativeCalls() const
Definition: PPCSubtarget.cpp:254
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
PPCMachineFunctionInfo.h
llvm::PPCISD::XXPERMDI
@ XXPERMDI
XXPERMDI - The PPC XXPERMDI instruction.
Definition: PPCISelLowering.h:125
llvm::SmallVectorImpl< MachineInstr * >
llvm::MachineInstr::setDesc
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition: MachineInstr.h:1742
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:412
DEBUG_TYPE
#define DEBUG_TYPE
Definition: PPCMIPeephole.cpp:40
EnableSExtElimination
static cl::opt< bool > EnableSExtElimination("ppc-eliminate-signext", cl::desc("enable elimination of sign-extensions"), cl::init(false), cl::Hidden)
llvm::MachineInstr::isFullCopy
bool isFullCopy() const
Definition: MachineInstr.h:1295
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:46
PPCPredicates.h
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:680
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MachineBlockFrequencyInfo::getEntryFreq
uint64_t getEntryFreq() const
Divide a block's BlockFrequency::getFrequency() value by this value to obtain the entry block - relat...
Definition: MachineBlockFrequencyInfo.cpp:289
InitializePasses.h
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:618
MachineBlockFrequencyInfo.h
Debug.h
PPCTargetMachine.h
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:58
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
MachineDominators.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::PPCSubtarget::isELFv2ABI
bool isELFv2ABI() const
Definition: PPCSubtarget.cpp:251