LLVM 17.0.0git
PPCTargetTransformInfo.h
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1//===-- PPCTargetTransformInfo.h - PPC specific TTI -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file a TargetTransformInfo::Concept conforming object specific to the
10/// PPC target machine. It uses the target's detailed information to
11/// provide more precise answers to certain TTI queries, while letting the
12/// target independent and default TTI implementations handle the rest.
13///
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H
17#define LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H
18
19#include "PPCTargetMachine.h"
23#include <optional>
24
25namespace llvm {
26
27class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> {
30 friend BaseT;
31
32 const PPCSubtarget *ST;
33 const PPCTargetLowering *TLI;
34
35 const PPCSubtarget *getST() const { return ST; }
36 const PPCTargetLowering *getTLI() const { return TLI; }
37 bool mightUseCTR(BasicBlock *BB, TargetLibraryInfo *LibInfo,
39
40public:
41 explicit PPCTTIImpl(const PPCTargetMachine *TM, const Function &F)
42 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
43 TLI(ST->getTargetLowering()) {}
44
45 std::optional<Instruction *> instCombineIntrinsic(InstCombiner & IC,
46 IntrinsicInst & II) const;
47
48 /// \name Scalar TTI Implementations
49 /// @{
50
54
55 InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
56 const APInt &Imm, Type *Ty,
58 Instruction *Inst = nullptr);
60 const APInt &Imm, Type *Ty,
62
66
70 TargetLibraryInfo *LibInfo,
71 HardwareLoopInfo &HWLoopInfo);
72 bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI,
74 TargetLibraryInfo *LibInfo);
84 bool shouldBuildRelLookupTables() const;
85 /// @}
86
87 /// \name Vector TTI Implementations
88 /// @{
90 bool enableAggressiveInterleaving(bool LoopHasReductions);
92 bool IsZeroCmp) const;
94
97 };
98 unsigned getNumberOfRegisters(unsigned ClassID) const;
99 unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const;
100 const char* getRegisterClassName(unsigned ClassID) const;
102 unsigned getCacheLineSize() const override;
103 unsigned getPrefetchDistance() const override;
104 unsigned getMaxInterleaveFactor(unsigned VF);
105 InstructionCost vectorCostAdjustmentFactor(unsigned Opcode, Type *Ty1,
106 Type *Ty2);
108 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
110 TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
111 ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
112 const Instruction *CxtI = nullptr);
113 InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp,
114 ArrayRef<int> Mask,
116 Type *SubTp,
117 ArrayRef<const Value *> Args = std::nullopt);
118 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
121 const Instruction *I = nullptr);
122 InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
123 const Instruction *I = nullptr);
124 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
125 CmpInst::Predicate VecPred,
127 const Instruction *I = nullptr);
129 InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
131 unsigned Index, Value *Op0, Value *Op1);
132 InstructionCost
133 getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
135 TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
136 const Instruction *I = nullptr);
137 InstructionCost getInterleavedMemoryOpCost(
138 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
139 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
140 bool UseMaskForCond = false, bool UseMaskForGaps = false);
141 InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
143 bool areTypesABICompatible(const Function *Caller, const Function *Callee,
144 const ArrayRef<Type *> &Types) const;
145 bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
146 Align Alignment) const;
147 InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
148 unsigned AddressSpace,
150 const Instruction *I = nullptr);
151 bool supportsTailCallFor(const CallBase *CB) const;
152
153private:
154 // The following constant is used for estimating costs on power9.
155 static const InstructionCost::CostType P9PipelineFlushEstimate = 80;
156
157 /// @}
158};
159
160} // end namespace llvm
161
162#endif
amdgpu Simplify well known AMD library false FunctionCallee Callee
static const Function * getParent(const Value *V)
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
This pass exposes codegen information to IR-level passes.
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A cache of @llvm.assume calls within a function.
LLVM Basic Block Representation.
Definition: BasicBlock.h:56
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:79
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
Conditional or Unconditional Branch instruction.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:718
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:166
The core instruction combiner logic.
Definition: InstCombiner.h:45
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
The optimization diagnostic interface.
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
const char * getRegisterClassName(unsigned ClassID) const
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool useColdCCForColdCall(Function &F)
InstructionCost vectorCostAdjustmentFactor(unsigned Opcode, Type *Ty1, Type *Ty2)
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, Type *SubTp, ArrayRef< const Value * > Args=std::nullopt)
bool supportsTailCallFor(const CallBase *CB) const
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info)
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
unsigned getCacheLineSize() const override
PPCTTIImpl(const PPCTargetMachine *TM, const Function &F)
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
bool enableAggressiveInterleaving(bool LoopHasReductions)
unsigned getPrefetchDistance() const override
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
unsigned getNumberOfRegisters(unsigned ClassID) const
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
bool shouldBuildRelLookupTables() const
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo)
InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
unsigned getMaxInterleaveFactor(unsigned VF)
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Common code between 32-bit and 64-bit PowerPC targets.
The main scalar evolution driver.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
Provides information about what library functions are available for the current target.
const DataLayout & getDataLayout() const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
TargetCostKind
The kind of cost model.
PopcntSupportKind
Flags indicating the kind of support for population count.
ShuffleKind
The various kinds of shuffle patterns for vector queries.
CastContextHint
Represents a hint about the context in which a cast is used.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
AddressSpace
Definition: NVPTXBaseInfo.h:21
Attributes of a target dependent hardware loop.
Information about a load/store intrinsic defined by the target.
Returns options for expansion of memcmp. IsZeroCmp is.
Parameters that control the generic loop unrolling transformation.