35#define DEBUG_TYPE "asm-printer"
37#define PRINT_ALIAS_INSTR
38#include "ARMGenAsmWriter.inc"
45 assert((imm & ~0x1f) == 0 &&
"Invalid shift encoding");
54 unsigned ShImm,
bool UseMarkup) {
60 O << getShiftOpcStr(ShOpc);
77 if (Opt ==
"reg-names-std") {
78 DefaultAltIdx = ARM::NoRegAltName;
81 if (Opt ==
"reg-names-raw") {
82 DefaultAltIdx = ARM::RegNamesRaw;
95 unsigned Opcode =
MI->getOpcode();
142 O <<
", " <<
markup(
"<imm:") <<
"#"
150 case ARM::t2STMDB_UPD:
151 if (
MI->getOperand(0).getReg() == ARM::SP &&
MI->getNumOperands() > 5) {
155 if (Opcode == ARM::t2STMDB_UPD)
164 case ARM::STR_PRE_IMM:
165 if (
MI->getOperand(2).getReg() == ARM::SP &&
166 MI->getOperand(3).getImm() == -4) {
179 case ARM::t2LDMIA_UPD:
180 if (
MI->getOperand(0).getReg() == ARM::SP &&
MI->getNumOperands() > 5) {
184 if (Opcode == ARM::t2LDMIA_UPD)
193 case ARM::LDR_POST_IMM:
194 if (
MI->getOperand(2).getReg() == ARM::SP &&
195 MI->getOperand(4).getImm() == 4) {
207 case ARM::VSTMSDB_UPD:
208 case ARM::VSTMDDB_UPD:
209 if (
MI->getOperand(0).getReg() == ARM::SP) {
210 O <<
'\t' <<
"vpush";
220 case ARM::VLDMSIA_UPD:
221 case ARM::VLDMDIA_UPD:
222 if (
MI->getOperand(0).getReg() == ARM::SP) {
233 bool Writeback =
true;
234 unsigned BaseReg =
MI->getOperand(0).getReg();
235 for (
unsigned i = 3; i <
MI->getNumOperands(); ++i) {
236 if (
MI->getOperand(i).getReg() == BaseReg)
264 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
265 unsigned Reg =
MI->getOperand(
isStore ? 1 : 0).getReg();
278 for (
unsigned i =
isStore ? 3 : 2; i <
MI->getNumOperands(); ++i)
290 switch (
MI->getOperand(0).getImm()) {
316 unsigned Reg = Op.getReg();
318 }
else if (Op.isImm()) {
321 assert(Op.isExpr() &&
"unknown operand kind in printOperand");
322 const MCExpr *Expr = Op.getExpr();
333 int64_t TargetAddress;
334 if (!
Constant->evaluateAsAbsolute(TargetAddress)) {
339 O.write_hex(
static_cast<uint32_t>(TargetAddress));
375 O <<
markup(
"<mem:") <<
"[pc, ";
377 int32_t OffImm = (int32_t)MO1.
getImm();
378 bool isSub = OffImm < 0;
381 if (OffImm == INT32_MIN)
440 O <<
markup(
"<mem:") <<
"[";
445 O <<
", " <<
markup(
"<imm:") <<
"#"
467 O <<
markup(
"<mem:") <<
"[";
479 O <<
markup(
"<mem:") <<
"[";
514 O <<
markup(
"<imm:") <<
'#'
533 bool AlwaysPrintImm0) {
538 O <<
markup(
"<mem:") <<
'[';
559template <
bool AlwaysPr
intImm0>
571 "unexpected idxmode");
589 O <<
markup(
"<imm:") <<
'#'
598 unsigned Imm = MO.
getImm();
599 O <<
markup(
"<imm:") <<
'#' << ((Imm & 256) ?
"" :
"-") << (Imm & 0xff)
609 O << (MO2.
getImm() ?
"" :
"-");
617 unsigned Imm = MO.
getImm();
618 O <<
markup(
"<imm:") <<
'#' << ((Imm & 256) ?
"" :
"-") << ((Imm & 0xff) << 2)
629 O <<
markup(
"<mem:") <<
"[";
648template <
bool AlwaysPr
intImm0>
660 O <<
markup(
"<mem:") <<
"[";
665 if (AlwaysPrintImm0 || ImmOffs || Op ==
ARM_AM::sub) {
667 << ImmOffs * 4 <<
markup(
">");
672template <
bool AlwaysPr
intImm0>
684 O <<
markup(
"<mem:") <<
"[";
689 if (AlwaysPrintImm0 || ImmOffs || Op ==
ARM_AM::sub) {
706 O <<
markup(
"<mem:") <<
"[";
709 O <<
":" << (MO2.
getImm() << 3);
718 O <<
markup(
"<mem:") <<
"[";
744 assert(MO.
isImm() &&
"Not a valid bf_inv_mask_imm value!");
746 <<
'#' << width <<
markup(
">");
752 unsigned val =
MI->getOperand(OpNum).getImm();
759 unsigned val =
MI->getOperand(OpNum).getImm();
766 unsigned val =
MI->getOperand(OpNum).getImm();
773 unsigned ShiftOp =
MI->getOperand(OpNum).getImm();
774 bool isASR = (ShiftOp & (1 << 5)) != 0;
775 unsigned Amt = ShiftOp & 0x1f;
777 O <<
", asr " <<
markup(
"<imm:") <<
"#" << (Amt == 0 ? 32 : Amt)
780 O <<
", lsl " <<
markup(
"<imm:") <<
"#" << Amt <<
markup(
">");
787 unsigned Imm =
MI->getOperand(OpNum).getImm();
790 assert(Imm > 0 && Imm < 32 &&
"Invalid PKH shift immediate value!");
791 O <<
", lsl " <<
markup(
"<imm:") <<
"#" << Imm <<
markup(
">");
797 unsigned Imm =
MI->getOperand(OpNum).getImm();
801 assert(Imm > 0 && Imm <= 32 &&
"Invalid PKH shift immediate value!");
802 O <<
", asr " <<
markup(
"<imm:") <<
"#" << Imm <<
markup(
">");
808 if (
MI->getOpcode() != ARM::t2CLRM) {
817 for (
unsigned i = OpNum, e =
MI->getNumOperands(); i != e; ++i) {
828 unsigned Reg =
MI->getOperand(OpNum).getReg();
853 unsigned IFlags = Op.getImm();
854 for (
int i = 2; i >= 0; --i)
855 if (IFlags & (1 << i))
867 if (FeatureBits[ARM::FeatureMClass]) {
869 unsigned SYSm = Op.getImm() & 0xFFF;
870 unsigned Opcode =
MI->getOpcode();
873 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
875 if (TheReg && TheReg->isInRequiredFeatures({ARM::FeatureDSP})) {
883 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
906 unsigned SpecRegRBit = Op.getImm() >> 4;
907 unsigned Mask = Op.getImm() & 0xf;
909 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
947 uint32_t Banked =
MI->getOperand(OpNum).getImm();
948 auto TheReg = ARMBankedReg::lookupBankedRegByEncoding(Banked);
949 assert(TheReg &&
"invalid banked register operand");
950 std::string
Name = TheReg->Name;
952 uint32_t isSPSR = (Banked & 0x20) >> 5;
954 Name.replace(0, 4,
"SPSR");
963 if ((
unsigned)
CC == 15)
997 if (
MI->getOperand(OpNum).getReg()) {
998 assert(
MI->getOperand(OpNum).getReg() == ARM::CPSR &&
999 "Expect ARM CPSR register!");
1007 O <<
MI->getOperand(OpNum).getImm();
1013 O <<
"p" <<
MI->getOperand(OpNum).getImm();
1019 O <<
"c" <<
MI->getOperand(OpNum).getImm();
1025 O <<
"{" <<
MI->getOperand(OpNum).getImm() <<
"}";
1033template <
unsigned scale>
1047 if (OffImm == INT32_MIN)
1049 else if (OffImm < 0)
1050 O <<
"#-" << -OffImm;
1066 unsigned Imm =
MI->getOperand(OpNum).getImm();
1075 unsigned Mask =
MI->getOperand(OpNum).getImm();
1077 assert(NumTZ <= 3 &&
"Invalid IT mask!");
1078 for (
unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1079 if ((Mask >> Pos) & 1)
1097 O <<
markup(
"<mem:") <<
"[";
1099 if (
unsigned RegNum = MO2.
getReg()) {
1119 O <<
markup(
"<mem:") <<
"[";
1121 if (
unsigned ImmOffs = MO2.
getImm()) {
1165 unsigned Reg = MO1.
getReg();
1169 assert(MO2.
isImm() &&
"Not a valid t2_so_reg value!");
1174template <
bool AlwaysPr
intImm0>
1186 O <<
markup(
"<mem:") <<
"[";
1189 int32_t OffImm = (int32_t)MO2.
getImm();
1190 bool isSub = OffImm < 0;
1192 if (OffImm == INT32_MIN)
1196 }
else if (AlwaysPrintImm0 || OffImm > 0) {
1202template <
bool AlwaysPr
intImm0>
1210 O <<
markup(
"<mem:") <<
"[";
1213 int32_t OffImm = (int32_t)MO2.
getImm();
1214 bool isSub = OffImm < 0;
1216 if (OffImm == INT32_MIN)
1219 O <<
", " <<
markup(
"<imm:") <<
"#-" << -OffImm <<
markup(
">");
1220 }
else if (AlwaysPrintImm0 || OffImm > 0) {
1221 O <<
", " <<
markup(
"<imm:") <<
"#" << OffImm <<
markup(
">");
1226template <
bool AlwaysPr
intImm0>
1239 O <<
markup(
"<mem:") <<
"[";
1242 int32_t OffImm = (int32_t)MO2.
getImm();
1243 bool isSub = OffImm < 0;
1245 assert(((OffImm & 0x3) == 0) &&
"Not a valid immediate!");
1248 if (OffImm == INT32_MIN)
1251 O <<
", " <<
markup(
"<imm:") <<
"#-" << -OffImm <<
markup(
">");
1252 }
else if (AlwaysPrintImm0 || OffImm > 0) {
1253 O <<
", " <<
markup(
"<imm:") <<
"#" << OffImm <<
markup(
">");
1264 O <<
markup(
"<mem:") <<
"[";
1277 int32_t OffImm = (int32_t)MO1.
getImm();
1278 O <<
", " <<
markup(
"<imm:");
1279 if (OffImm == INT32_MIN)
1281 else if (OffImm < 0)
1282 O <<
"#-" << -OffImm;
1292 int32_t OffImm = (int32_t)MO1.
getImm();
1294 assert(((OffImm & 0x3) == 0) &&
"Not a valid immediate!");
1296 O <<
", " <<
markup(
"<imm:");
1297 if (OffImm == INT32_MIN)
1299 else if (OffImm < 0)
1300 O <<
"#-" << -OffImm;
1314 O <<
markup(
"<mem:") <<
"[";
1317 assert(MO2.
getReg() &&
"Invalid so_reg load / store address!");
1321 unsigned ShAmt = MO3.
getImm();
1323 assert(ShAmt <= 3 &&
"Not a valid Thumb2 addressing mode!");
1324 O <<
", lsl " <<
markup(
"<imm:") <<
"#" << ShAmt <<
markup(
">");
1340 unsigned EncodedImm =
MI->getOperand(OpNum).getImm();
1343 O <<
markup(
"<imm:") <<
"#0x";
1351 unsigned Imm =
MI->getOperand(OpNum).getImm();
1358 unsigned Imm =
MI->getOperand(OpNum).getImm();
1361 assert(Imm <= 3 &&
"illegal ror immediate!");
1362 O <<
", ror " <<
markup(
"<imm:") <<
"#" << 8 * Imm <<
markup(
">");
1374 unsigned Bits = Op.getImm() & 0xFF;
1375 unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1377 bool PrintUnsigned =
false;
1378 switch (
MI->getOpcode()) {
1381 PrintUnsigned = (
MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1385 PrintUnsigned =
true;
1389 int32_t Rotated = llvm::rotr<uint32_t>(Bits, Rot);
1392 O <<
"#" <<
markup(
"<imm:");
1394 O << static_cast<uint32_t>(Rotated);
1408 O <<
markup(
"<imm:") <<
"#" << 16 -
MI->getOperand(OpNum).getImm()
1414 O <<
markup(
"<imm:") <<
"#" << 32 -
MI->getOperand(OpNum).getImm()
1421 O <<
"[" <<
MI->getOperand(OpNum).getImm() <<
"]";
1435 unsigned Reg =
MI->getOperand(OpNum).getReg();
1448 unsigned Reg =
MI->getOperand(OpNum).getReg();
1503 unsigned Reg =
MI->getOperand(OpNum).getReg();
1550 unsigned Reg =
MI->getOperand(OpNum).getReg();
1625template<
unsigned NumRegs>
1629 unsigned Reg =
MI->getOperand(OpNum).getReg();
1630 const char *Prefix =
"{";
1631 for (
unsigned i = 0; i < NumRegs; i++) {
1639template<
int64_t Angle,
int64_t Remainder>
1643 unsigned Val =
MI->getOperand(OpNo).getImm();
1644 O <<
"#" << (Val * Angle) + Remainder;
1659 unsigned Mask =
MI->getOperand(OpNum).getImm();
1661 assert(NumTZ <= 3 &&
"Invalid VPT mask!");
1662 for (
unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1663 bool T = ((Mask >> Pos) & 1) == 0;
1674 uint32_t Val =
MI->getOperand(OpNum).getImm();
1675 assert(Val <= 1 &&
"Invalid MVE saturate operand");
1676 O <<
"#" << (Val == 1 ? 48 : 64);
unsigned const MachineRegisterInfo * MRI
static bool isStore(int Opcode)
static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, unsigned ShImm, bool UseMarkup)
Prints the shift value with an immediate value.
static unsigned translateShiftImm(unsigned imm)
translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMVEVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCPSIFlag(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFour(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVPTPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInstSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode7Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegisterList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printComplexRotationOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMveSaturateOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwo(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFBits16(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPCLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCPSIMod(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool applyTargetSpecificCLOption(StringRef Opt) override
Customize the printer according to a command line option.
virtual bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2SOOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListOne(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbITMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printTraceSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printGPRPairOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFBits32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRotImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=ARM::NoRegAltName)
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCoprocOptionImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printShiftImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printBankedRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbSRImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSetendOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryRestrictedPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVPTMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThree(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVMOVModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O, bool AlwaysPrintImm0)
void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, unsigned Scale)
void printAddrModeTBH(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNoHashImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryInvertedPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
This is an important base class in LLVM.
Container class for subtarget features.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Base class for the full range of assembler expressions which are needed for parsing.
@ Constant
Constant expressions.
@ Binary
Binary expressions.
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
bool UseMarkup
True if we are printing marked up assembly.
format_object< int64_t > formatHex(int64_t Value) const
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
const MCRegisterInfo & MRI
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
bool getUseMarkup() const
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Instances of this class represent a single low-level machine instruction.
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
MCRegisterClass - Base class of TargetRegisterClass.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
StringRef - Represent a constant reference to a string, i.e.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static CondCodes getOppositeCondition(CondCodes CC)
const MClassSysReg * lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
const MClassSysReg * lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
const MClassSysReg * lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
unsigned char getAM3Offset(unsigned AM3Opc)
unsigned char getAM5FP16Offset(unsigned AM5Opc)
unsigned getSORegOffset(unsigned Op)
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
uint64_t decodeVMOVModImm(unsigned ModImm, unsigned &EltBits)
decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the element value and the element ...
unsigned getAM2IdxMode(unsigned AM2Opc)
unsigned getAM3IdxMode(unsigned AM3Opc)
unsigned getAM2Offset(unsigned AM2Opc)
const char * getAMSubModeStr(AMSubMode Mode)
float getFPImmFloat(unsigned Imm)
ShiftOpc getSORegShOp(unsigned Op)
AddrOpc getAM5Op(unsigned AM5Opc)
AddrOpc getAM5FP16Op(unsigned AM5Opc)
const char * getAddrOpcStr(AddrOpc Op)
const char * getShiftOpcStr(ShiftOpc Op)
unsigned char getAM5Offset(unsigned AM5Opc)
AddrOpc getAM2Op(unsigned AM2Opc)
AddrOpc getAM3Op(unsigned AM3Opc)
AMSubMode getAM4SubMode(unsigned Mode)
static const char * InstSyncBOptToString(unsigned val)
static const char * MemBOptToString(unsigned val, bool HasV8)
uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, int64_t Imm)
static const char * IModToString(unsigned val)
static const char * IFlagsToString(unsigned val)
static const char * TraceSyncBOptToString(unsigned val)
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
static const char * ARMVPTPredToString(ARMVCC::VPTCodes CC)
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
static const char * ARMCondCodeToString(ARMCC::CondCodes CC)