35#define DEBUG_TYPE "asm-printer"
37#define PRINT_ALIAS_INSTR
38#include "ARMGenAsmWriter.inc"
45 assert((imm & ~0x1f) == 0 &&
"Invalid shift encoding");
59 O << getShiftOpcStr(ShOpc);
73 if (Opt ==
"reg-names-std") {
74 DefaultAltIdx = ARM::NoRegAltName;
77 if (Opt ==
"reg-names-raw") {
78 DefaultAltIdx = ARM::RegNamesRaw;
147 case ARM::t2STMDB_UPD:
148 if (
MI->getOperand(0).getReg() == ARM::SP &&
MI->getNumOperands() > 5) {
152 if (
Opcode == ARM::t2STMDB_UPD)
161 case ARM::STR_PRE_IMM:
162 if (
MI->getOperand(2).getReg() == ARM::SP &&
163 MI->getOperand(3).getImm() == -4) {
176 case ARM::t2LDMIA_UPD:
177 if (
MI->getOperand(0).getReg() == ARM::SP &&
MI->getNumOperands() > 5) {
181 if (
Opcode == ARM::t2LDMIA_UPD)
190 case ARM::LDR_POST_IMM:
191 if (
MI->getOperand(2).getReg() == ARM::SP &&
192 MI->getOperand(4).getImm() == 4) {
204 case ARM::VSTMSDB_UPD:
205 case ARM::VSTMDDB_UPD:
206 if (
MI->getOperand(0).getReg() == ARM::SP) {
207 O <<
'\t' <<
"vpush";
217 case ARM::VLDMSIA_UPD:
218 case ARM::VLDMDIA_UPD:
219 if (
MI->getOperand(0).getReg() == ARM::SP) {
230 bool Writeback =
true;
231 unsigned BaseReg =
MI->getOperand(0).getReg();
232 for (
unsigned i = 3; i <
MI->getNumOperands(); ++i) {
233 if (
MI->getOperand(i).getReg() == BaseReg)
262 unsigned Reg =
MI->getOperand(
isStore ? 1 : 0).getReg();
275 for (
unsigned i =
isStore ? 3 : 2; i <
MI->getNumOperands(); ++i)
287 switch (
MI->getOperand(0).getImm()) {
313 unsigned Reg =
Op.getReg();
315 }
else if (
Op.isImm()) {
318 assert(
Op.isExpr() &&
"unknown operand kind in printOperand");
330 int64_t TargetAddress;
331 if (!
Constant->evaluateAsAbsolute(TargetAddress)) {
336 O.write_hex(
static_cast<uint32_t>(TargetAddress));
375 int32_t OffImm = (int32_t)MO1.
getImm();
376 bool isSub = OffImm < 0;
379 if (OffImm == INT32_MIN)
538 bool AlwaysPrintImm0) {
565template <
bool AlwaysPr
intImm0>
577 "unexpected idxmode");
604 unsigned Imm = MO.
getImm();
606 <<
'#' << ((Imm & 256) ?
"" :
"-") << (Imm & 0xff);
615 O << (MO2.
getImm() ?
"" :
"-");
623 unsigned Imm = MO.
getImm();
625 <<
'#' << ((Imm & 256) ?
"" :
"-") << ((Imm & 0xff) << 2);
655template <
bool AlwaysPr
intImm0>
681template <
bool AlwaysPr
intImm0>
718 O <<
":" << (MO2.
getImm() << 3);
754 assert(MO.
isImm() &&
"Not a valid bf_inv_mask_imm value!");
763 unsigned val =
MI->getOperand(OpNum).getImm();
770 unsigned val =
MI->getOperand(OpNum).getImm();
777 unsigned val =
MI->getOperand(OpNum).getImm();
784 unsigned ShiftOp =
MI->getOperand(OpNum).getImm();
785 bool isASR = (ShiftOp & (1 << 5)) != 0;
786 unsigned Amt = ShiftOp & 0x1f;
799 unsigned Imm =
MI->getOperand(OpNum).getImm();
802 assert(Imm > 0 && Imm < 32 &&
"Invalid PKH shift immediate value!");
810 unsigned Imm =
MI->getOperand(OpNum).getImm();
814 assert(Imm > 0 && Imm <= 32 &&
"Invalid PKH shift immediate value!");
822 if (
MI->getOpcode() != ARM::t2CLRM) {
831 for (
unsigned i = OpNum, e =
MI->getNumOperands(); i != e; ++i) {
842 unsigned Reg =
MI->getOperand(OpNum).getReg();
867 unsigned IFlags =
Op.getImm();
868 for (
int i = 2; i >= 0; --i)
869 if (IFlags & (1 << i))
881 if (FeatureBits[ARM::FeatureMClass]) {
883 unsigned SYSm =
Op.getImm() & 0xFFF;
887 if (
Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
889 if (TheReg && TheReg->isInRequiredFeatures({ARM::FeatureDSP})) {
897 if (
Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
920 unsigned SpecRegRBit =
Op.getImm() >> 4;
921 unsigned Mask =
Op.getImm() & 0xf;
923 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
961 uint32_t Banked =
MI->getOperand(OpNum).getImm();
962 auto TheReg = ARMBankedReg::lookupBankedRegByEncoding(Banked);
963 assert(TheReg &&
"invalid banked register operand");
964 std::string
Name = TheReg->Name;
966 uint32_t isSPSR = (Banked & 0x20) >> 5;
968 Name.replace(0, 4,
"SPSR");
977 if ((
unsigned)
CC == 15)
1011 if (
MI->getOperand(OpNum).getReg()) {
1012 assert(
MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1013 "Expect ARM CPSR register!");
1021 O <<
MI->getOperand(OpNum).getImm();
1027 O <<
"p" <<
MI->getOperand(OpNum).getImm();
1033 O <<
"c" <<
MI->getOperand(OpNum).getImm();
1039 O <<
"{" <<
MI->getOperand(OpNum).getImm() <<
"}";
1047template <
unsigned scale>
1061 if (OffImm == INT32_MIN)
1063 else if (OffImm < 0)
1064 O <<
"#-" << -OffImm;
1073 <<
"#" <<
formatImm(
MI->getOperand(OpNum).getImm() * 4);
1079 unsigned Imm =
MI->getOperand(OpNum).getImm();
1087 unsigned Mask =
MI->getOperand(OpNum).getImm();
1089 assert(NumTZ <= 3 &&
"Invalid IT mask!");
1090 for (
unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1091 if ((Mask >> Pos) & 1)
1112 if (
unsigned RegNum = MO2.
getReg()) {
1135 if (
unsigned ImmOffs = MO2.
getImm()) {
1179 unsigned Reg = MO1.
getReg();
1183 assert(MO2.
isImm() &&
"Not a valid t2_so_reg value!");
1188template <
bool AlwaysPr
intImm0>
1204 int32_t OffImm = (int32_t)MO2.
getImm();
1205 bool isSub = OffImm < 0;
1207 if (OffImm == INT32_MIN)
1212 }
else if (AlwaysPrintImm0 || OffImm > 0) {
1219template <
bool AlwaysPr
intImm0>
1231 int32_t OffImm = (int32_t)MO2.
getImm();
1232 bool isSub = OffImm < 0;
1234 if (OffImm == INT32_MIN)
1239 }
else if (AlwaysPrintImm0 || OffImm > 0) {
1246template <
bool AlwaysPr
intImm0>
1263 int32_t OffImm = (int32_t)MO2.
getImm();
1264 bool isSub = OffImm < 0;
1266 assert(((OffImm & 0x3) == 0) &&
"Not a valid immediate!");
1269 if (OffImm == INT32_MIN)
1274 }
else if (AlwaysPrintImm0 || OffImm > 0) {
1301 int32_t OffImm = (int32_t)MO1.
getImm();
1304 if (OffImm == INT32_MIN)
1306 else if (OffImm < 0)
1307 O <<
"#-" << -OffImm;
1316 int32_t OffImm = (int32_t)MO1.
getImm();
1318 assert(((OffImm & 0x3) == 0) &&
"Not a valid immediate!");
1322 if (OffImm == INT32_MIN)
1324 else if (OffImm < 0)
1325 O <<
"#-" << -OffImm;
1342 assert(MO2.
getReg() &&
"Invalid so_reg load / store address!");
1346 unsigned ShAmt = MO3.
getImm();
1348 assert(ShAmt <= 3 &&
"Not a valid Thumb2 addressing mode!");
1365 unsigned EncodedImm =
MI->getOperand(OpNum).getImm();
1377 unsigned Imm =
MI->getOperand(OpNum).getImm();
1384 unsigned Imm =
MI->getOperand(OpNum).getImm();
1387 assert(Imm <= 3 &&
"illegal ror immediate!");
1401 unsigned Bits =
Op.getImm() & 0xFF;
1402 unsigned Rot = (
Op.getImm() & 0xF00) >> 7;
1404 bool PrintUnsigned =
false;
1405 switch (
MI->getOpcode()) {
1408 PrintUnsigned = (
MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1412 PrintUnsigned =
true;
1416 int32_t Rotated = llvm::rotr<uint32_t>(Bits, Rot);
1447 O <<
"[" <<
MI->getOperand(OpNum).getImm() <<
"]";
1461 unsigned Reg =
MI->getOperand(OpNum).getReg();
1474 unsigned Reg =
MI->getOperand(OpNum).getReg();
1529 unsigned Reg =
MI->getOperand(OpNum).getReg();
1576 unsigned Reg =
MI->getOperand(OpNum).getReg();
1651template<
unsigned NumRegs>
1655 unsigned Reg =
MI->getOperand(OpNum).getReg();
1656 const char *Prefix =
"{";
1657 for (
unsigned i = 0; i < NumRegs; i++) {
1665template<
int64_t Angle,
int64_t Remainder>
1669 unsigned Val =
MI->getOperand(OpNo).getImm();
1670 O <<
"#" << (Val * Angle) + Remainder;
1685 unsigned Mask =
MI->getOperand(OpNum).getImm();
1687 assert(NumTZ <= 3 &&
"Invalid VPT mask!");
1688 for (
unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1689 bool T = ((Mask >> Pos) & 1) == 0;
1700 uint32_t Val =
MI->getOperand(OpNum).getImm();
1701 assert(Val <= 1 &&
"Invalid MVE saturate operand");
1702 O <<
"#" << (Val == 1 ? 48 : 64);
unsigned const MachineRegisterInfo * MRI
static bool isStore(int Opcode)
static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, unsigned ShImm, const ARMInstPrinter &printer)
static unsigned translateShiftImm(unsigned imm)
translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static constexpr uint32_t Opcode
void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMVEVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCPSIFlag(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFour(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVPTPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInstSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode7Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegisterList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printComplexRotationOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMveSaturateOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwo(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFBits16(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPCLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCPSIMod(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool applyTargetSpecificCLOption(StringRef Opt) override
Customize the printer according to a command line option.
virtual bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2SOOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListOne(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbITMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printTraceSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printGPRPairOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFBits32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRotImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=ARM::NoRegAltName)
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCoprocOptionImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printShiftImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printBankedRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbSRImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSetendOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryRestrictedPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVPTMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThree(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVMOVModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O, bool AlwaysPrintImm0)
void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, unsigned Scale)
void printAddrModeTBH(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNoHashImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryInvertedPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
This is an important base class in LLVM.
This class represents an Operation in the Expression.
Container class for subtarget features.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Base class for the full range of assembler expressions which are needed for parsing.
@ Constant
Constant expressions.
@ Binary
Binary expressions.
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
format_object< int64_t > formatHex(int64_t Value) const
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
WithMarkup markup(raw_ostream &OS, Markup M) const
const MCRegisterInfo & MRI
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
bool getUseMarkup() const
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Instances of this class represent a single low-level machine instruction.
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
MCRegisterClass - Base class of TargetRegisterClass.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
StringRef - Represent a constant reference to a string, i.e.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static CondCodes getOppositeCondition(CondCodes CC)
const MClassSysReg * lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
const MClassSysReg * lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
const MClassSysReg * lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
unsigned char getAM3Offset(unsigned AM3Opc)
unsigned char getAM5FP16Offset(unsigned AM5Opc)
unsigned getSORegOffset(unsigned Op)
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
uint64_t decodeVMOVModImm(unsigned ModImm, unsigned &EltBits)
decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the element value and the element ...
unsigned getAM2IdxMode(unsigned AM2Opc)
unsigned getAM3IdxMode(unsigned AM3Opc)
unsigned getAM2Offset(unsigned AM2Opc)
const char * getAMSubModeStr(AMSubMode Mode)
float getFPImmFloat(unsigned Imm)
ShiftOpc getSORegShOp(unsigned Op)
AddrOpc getAM5Op(unsigned AM5Opc)
AddrOpc getAM5FP16Op(unsigned AM5Opc)
const char * getAddrOpcStr(AddrOpc Op)
const char * getShiftOpcStr(ShiftOpc Op)
unsigned char getAM5Offset(unsigned AM5Opc)
AddrOpc getAM2Op(unsigned AM2Opc)
AddrOpc getAM3Op(unsigned AM3Opc)
AMSubMode getAM4SubMode(unsigned Mode)
static const char * InstSyncBOptToString(unsigned val)
static const char * MemBOptToString(unsigned val, bool HasV8)
uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, int64_t Imm)
static const char * IModToString(unsigned val)
static const char * IFlagsToString(unsigned val)
static const char * TraceSyncBOptToString(unsigned val)
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
static const char * ARMVPTPredToString(ARMVCC::VPTCodes CC)
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
static const char * ARMCondCodeToString(ARMCC::CondCodes CC)